®
Data Sheet 
 
PCapØ2A 
Single-chip Solution for Capacitance Measurement 
Volume 1: General Data and Front-end Description 
May 29, 2014, Version 1.6 
Document-No: DB_PCapØ2A_Vol1_en.pdf 
 
 
 
 
®
PCapØ2A
 
P u b l i s h e d   b y   a c a m - m e s s e l e c t r o n i c   g m b h    
©acam-messelectronic gmbh 2014 
 
 
 
 
 
 
 
L i m i t a t i o n   o f   L i a b i l i t y /  W a r r a n t y /   C o p y r i g h t    
 
The information and data contained in this document are believed to be accurate and 
reliable. acam assumes no liability for errors and gives no warranty representation or 
guarantee regarding the suitability of its products for any particular purpose due  to these 
specifications. Any information and data which may be provided in the document can and 
do vary in different applications, and actual performance may vary over time. All operating 
parameters must be validated for each customer application by customers’ technical 
experts. 
 
The information contained therein may be protected by copyright, patent, trademark 
and/or other intellectual property rights of acam. acam does not assume responsibility for 
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production so that full information about the product is not available yet.  
 
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the acam web site at: 
 
http://www.acam.de/sales/distributors/ 
 
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support@acam.de 
 
or by phone 
 
+49-7244-74190. 
 
 
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PCapØ2A
 
Content 
 
1  Overview .................................................................................................. 1-1 
1.1 
Features ............................................................................................. 1-1 
1.2  Applications ........................................................................................ 1-2 
1.3  Blockdiagram ...................................................................................... 1-2 
2  Characteristics & Specifications ................................................................... 2-1 
2.1 
Electrical Characteristics ....................................................................... 2-1 
2.2  CDC Precision ..................................................................................... 2-2 
2.3  RDC Precision ..................................................................................... 2-3 
2.4  Oscillators .......................................................................................... 2-4 
2.5  Power Consumption .............................................................................. 2-1 
2.6  Package Information ............................................................................. 2-2 
2.7  QFN Packages ..................................................................................... 2-4 
3  Converter Frontend .................................................................................... 3-1 
3.1  CDC, Capacitance-to-Digital Converter ...................................................... 3-1 
3.2  CDC Compensation Options .................................................................... 3-7 
3.3  CDC Important Parameters .................................................................... 3-9 
3.4  RDC Resistance-to-Digital Converter ...................................................... 3-12 
3.5  RDC Important Parameters .................................................................. 3-15 
4 
Interfaces (Serial & PDM/PWM) .................................................................. 4-1 
4.1 
4.2 
4.3 
4.4 
Serial Interfaces................................................................................... 4-1 
I²C Compatible Interface ........................................................................ 4-2 
SPI interface ....................................................................................... 4-3 
Special Timings .................................................................................... 4-5 
4.5  OTP Timings ........................................................................................ 4-7 
4.6  GPIO and PDM/PWM ......................................................................... 4-10 
4.7 
Interfaces Parameters ........................................................................ 4-15 
5  Configuration & Read Registers .................................................................... 5-1 
5.1  Configuration registers .......................................................................... 5-1 
5.2  Configuration Registers in Detail ............................................................. 5-4 
5.3  Oscillator Configuration ....................................................................... 5-20 
5.4 
Low Battery Detection (LBD) ................................................................ 5-21 
5.5  Read Registers .................................................................................. 5-22 
6  DSP & Memory.......................................................................................... 6-1 
6.1  Memory Map ....................................................................................... 6-2 
6.2  Memory Management ........................................................................... 6-3 
6.3  Getting started .................................................................................... 6-5 
acam messelectronic gmbh - Friedrich-List-Str.4 - 76297 Stutensee - Germany - www.acam.de 
1 
®
PCapØ2A
 
7  Miscellaneous ........................................................................................... 7-1 
7.1  Bug Report ......................................................................................... 7-1 
7.2 
7.3 
I²C Bug with POR directly after rd/wr OTP/SRAM ...................................... 7-1 
Limitation of Parameter2 ....................................................................... 7-1 
7.4  History ............................................................................................... 7-2 
 
 
2 
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PCapØ2A
 
1  Overview 
PCapØ2Y is a capacitance-to-digital converter (CDC) with integrated digital signal 
processor (DSP) for on-chip data post-processing. Its front end is based on acam‘s 
patented ® principle. This conversion principle offers outstanding flexibility  with 
respect to power consumption, resolution and speed. This datasheet describes  PCapØ2A, 
in its basic converter functionality. The DSP description is reduced to the standard 
firmware that calculates pure capacitance ratios. A detail ed DSP and memory description 
is given in datasheet volume 2. PCapØ2 can be used for single and differential sensors  in 
grounded and floating application. Compensation of internal and external stray  capacitance 
is implemented as well as for parallel resistance. Additionally, the temperature can be 
measured by means of internal thermistors or external sensors.  
1.1 
Features 
 
  Digital measuring principle in CMOS 
  Dedicated ports for precision 
technology  
  Up to 8 capacitances in grounded mode  
  Up to 4 capacitances in floating mode 
temperature measurement (with Pt1000 
sensors, the resolution is 0.005 K)  
  Serial interface (SPI or IIC compatible)   
(potential- free and with zero bias 
voltage)  
  Two 10/12/14/16 bit PDM/PWM 
outputs for analog interfaces  
 
 
Integrated reference capacitance 1 pF to 
31 pF  
  Self-boot capability  
  Single power supply (2.1 to 3.6 V), 
Integrated discharge resistors up to      
1 MOhm  
integrated 1.8 V regulator for improved 
PSRR.  
  Compensation of internal (grounded) and 
 
Integrated voltage measurement  
external parasitic capacities (floating)  
  Pre-charge option for slow charging  
  No need for a clock 
  RISC processor core using Harvard architec-
  Self-test capability for differential sensors   
ture: 
  High resolution: up to 15 aF at 2.5 Hz 
and 10 pF base capacitance or, 17 bit 
resolution at 5 Hz with 100 pF base 
capacitance and 10 pF excitation  
  High measurement rate: up to 500 kHz  
  Extremely low current consumption 
possible: Down to 2.5 μA at 2.5 Hz with 
13.1 bit resolution  
  128 x 48/24 bit RAM Data (80x48 free) 
  4k x 8 bit SRAM program memory for 
high-speed operation (40 to 85 MHz)  
  4k (+4k for ECC)x 8 bit OTP (one-time 
programmable) program memory for 
normal speed operation (up to 40 MHz)  
  128 byte EEPROM for calibration data 
and user data (serial number etc.) 
  High stability with temperature, low 
offset drift (down to 20 aF per Kelvin), 
low gain drift when all compensation 
options are activated.  
 
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1-1 
PCapØ2A
 
  Tilt sensors  
  Angle sensors  
  Wireless applications  
  Level sensors  
  Microphones  
  MEMS sensors 
®
1.2 
Applications 
  Humidity sensors  
  Position sensors  
  Pressure sensors  
  Force sensors  
  Acceleration sensors  
 
Inclination sensors 
 
 
1.3 
Blockdiagram 
Figure 1-1 Blockdiagram 
 
 
1-2 
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RDCUnit(Temperature)4x Raw dataCDCUnit(Capacitance)17x Raw dataRAM128 wordsDSP48 bitConfigurationReg. ParameterReg. OTP4k x 8 bitSRAM4k x 8 bitEEPROM128 byte1.8V voltageregulatorOscillator Control UnitExt. Quartz      InternalIIC/SPIGPIOPDM/PWMPC0PC1PC2PC3PC4PC5PC6PC7PCAUXPT0PT1PT2REFIIC_ENINTNSCK_SCLSSN_PG0MISO_PG1MOSI_SDAPG2PG3PG4PG5VDD18VDD33OXIN  OXOUTInternal:PC8PC910µF4.7µFPTOUT10nFC0G3.3V
PCapØ2A
 
2  Characteristics & Specifications  
2.1 
Electrical Characteristics  
2.1.1 
Absolute Maximum Ratings  
Supply voltage VDD-to-GND  
- 0.3 to 4.0 V  
Storage temperature Tstg  
- 55 to 150 °C  
ESD rating (HBM), each pin  
> 2 kV  
Junction temperature (Tj)  
max. 125 °C  
OTP Data Retention Period  
10 years at 95 °C temperature  
EEPROM Data Retention Period 
10 years at 95 °C temperature  
 
2.1.2 
Recommended Operating Conditions  
Table 2-1 Operating conditions 
Quantity  
Supply voltage  
Symbol   Remarks  
VDD  
 
 
Min. 
2.1 
Typ. 
 
Max. 
3.6 
Unit 
V 
Vio_digital   Relative to ground  
- 0.6 
3.3 
VDD +0.6 
V 
HIGH LOW  
LOW HIGH  
 
Between “VPP_OTP” port 
and ground. Do not expo-
se other ports to pro-
gramming voltage.  
Clock frequency for the 4-
wire SPI bus operation  
Speed (data rate) of the 
2-wire I²C bus operation  
Bit hold time for OTP 
write  
Rise time of the input 
signal put to general-
purpose I/O 
Rise time of the output 
signal from a general-
purpose I/O 
MR1 
 
0.3 * VDD 
0.7 * VDD 
≤ 3.6 
 
- 0.6 
 
VDD +0.6 
 
6.5 
≤ 3.6 
7.0 
 
V 
V 
0 
0 
30 
 
 
0 
 
 
 
 
6 
 
20 
MHz 
100 
kHz 
500 
500 
μs 
ns 
t.b.d. 
ns 
40 
µs 
Digital  
port voltage  
Digital ports  
switching level  
Analog port  
voltage  
OTP 
Programming 
voltage 
 
Vio_analog  
VOTP  
SPI bus frequency   fSPI-bus  
I²C bus frequency 
OTP Bit hold time 
GPIO input rise 
time 
GPIO output rise 
time  
CDC discharge 
time 
 
 
 
 
 
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2-1 
®
RDC discharge 
time 
Junction 
Temperature  
Ambient 
Temperature  
 
Tj  
Ta  
 
Junction temperature 
must not exceed +125 °C  
At VDD = 2.4V -/+ 0.3V  
0 
- 40 
- 40 
 
 
 
PCapØ2A
 
100 
µs 
+ 125 
°C 
+ 125 
°C 
2.2 
CDC Precision  
2.2.1 
RMS Noise and Resolution vs. Output Data Rate  
Table 2-2 Typical capacitive noise & resolution vs. output data rate, 10 pF base + 1 pF span, fast 
settle, MR1, V = 3.0 V 
Output 
Data 
Rate 
[Hz] 
2.5 
5 
10 
25 
100 
250 
1,000 
2,000 
4,000 
10,000 
25,000 
FLOATING  
Fully compensated  
RMS 
Noise 
[aF] 
Eff. Resolu-
tion 10 pF 
base [Bits] 
Eff. 
Resolution 
1 pF span 
GROUNDED  
Internally compensated  
Eff. Resolu-
tion 10 pF 
base [Bits] 
RMS 
Noise 
[aF] 
15 
23 
35 
48 
134 
172 
330 
438 
603 
838 
 
19.3 
18.7 
18.1 
17.7 
16.2 
15.8 
14.9 
14.5 
14.0 
13.5 
 
[Bits] 
16.0 
15.4 
14.8 
14.4 
12.9 
12.5 
11.6 
11.2 
10.7 
10.2 
 
 
15 
23 
50 
81 
116 
147 
230 
327 
566 
817 
19.3 
18.7 
17.6 
16.9 
16.4 
16.0 
15.4 
14.9 
14.1 
13.6 
Eff. 
Resolution 
1 pF span 
[Bits] 
 
 
16.0 
15.4 
14.3 
13.6 
13.1 
12.7 
12.1 
11.6 
10.8 
10.3 
 
The table gives the root mean-square (RMS) noise in aF as a function of output data rate 
in Hz, measured at 3.0 V supply voltage using the maximum possible sample size for in -
chip averaging at the minimum possible cycle time. Bit values are calculated as a binary 
logarithm of noise over the span (BITs = ln(span/noise)/ln(2)). The measurements have 
been done with the PCapØ2 evaluation board, with fixed C0G ceramic capacitors.  
Both, sensor and reference are connected “floating” or “grounded”, as indicated. When 
floating, compensation mechanisms for both internal and external stray capacitances are 
activated, when grounded, internal ones only.  
 
 
2-2 
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