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Digital Systems Engineering.pdf_数字系统工程
Cover
Title
Tables
Physical Constants
Silicon Constants
Bulk Resistivity of Various Pure Metals
Relative Permittivity of Various Materials
MOSFET Equations
Power and Noise
Thermal Conductivity of Various Materials
Transmission-Line Equations
Contents
Preface
Acknowledgments
1. Introduction to Digital Systems Engineering
1.1 Why Study Digital Systems Engineering?
1.2 An Engineering View of a Digital System
1.2.1 Feeds and Speeds
1.2.2 Signaling Conventions
1.2.2.1 Signaling Speed
1.2.2.2 Signaling Power
1.2.2.3 Signal Integrity
1.2.2.4 Other Signaling Conventions
1.2.3 Timing and Synchronization
1.2.3.1 Synchronous Timing
1.2.3.2 Pipelined Timing
1.2.3.3 Closed-Loop Timing
1.2.3.4 Clock Distribution
1.2.3.5 Synchronization
1.2.4 Power Distribution
1.2.5 Noise
1.2.6 A Systems View of Circuits
1.3 Technology Trends and Digital Systems Engineering
1.3.1 Moore's Law
1.3.2 Scaling of Chip Parameters
1.3.3 Scaling of Wires
1.3.3.1 Scaling of Power Distribution
1.3.3.2 Scaling of On-Chip Communication
1.3.3.3 Scaling of Off-Chip Communications
1.3.4 High Levels of Integration Permit New Approaches
1.3.5 Digital Systems Problems and Solutions Continue to Change
1 .4 Organization of this Book
1 .5 Bibliographic Notes
1.6 Exercises
2. Packaging of Digital Systems
2.1 A Typical Digital System
2.2 Digital Integrated Circuits - On-Chip Wiring
2.3 Integrated Circuits Packaging
2.3.1 Wire Bonds and Solder Balls
2.3.2 Package Types
2.3.3 Package Manufacturing Processes
2.3.4 Multichip Modules
2.3.5 A Typical Package Model
2.3.5.1 Physical Construction
2.3.5.2 Package Electrical Model
2.4 Printed Circuit Boards
2.4.1 PC Board Construction
2.4.2 Electrical Properties
2.4.3 Manufacturing Process
2.4.4 Vias
2.4.5 Dimensional Constraints
2.4.6 Mounting Components: Surface-Mount and Through-Hole
2.4.7 Sockets
2.5 Chassis and Cabinets
2.6 Backplanes and Mother Boards
2.6.1 Daughter Cards
2.6.2 Backplanes
2.7 Wire and Cable
2.7.1 Wires
2.7.2 Signaling Cables
2.7.2.1 Coaxial Cable
2.7.2.2 Ribbon Cable
2.7.2.3 Twisted Pair
2.7.2.4 Flex-Circuit Cable
2.7.3 Bus Bars
2.8 Connectors
2.8.1 PC Board Connectors
2.8.2 Interposers
2.8.3 Elastomeric Connectors
2.8.4 Power Connectors
2.8.5 Wire and Cable Connectors
2.8.5.1 Wire Harness Connectors
2.8.5.2 Coaxial Connectors
2.8.5.3 Ribbon-Cable Connectors
2.8.5.4 Methods of Attachment
2.9 Optical Communication
2.9.1 Optical Transmitters
2.9.1.1 LEDs
2.9.1.2 Laser Diodes
2.9.2 Optical Fiber
2.9.2.1 Multimode Fiber
2.9.2.2 Single-Mode Fiber
2.9.2.3 Optical Connectors
2.9.3 Optical Receivers
2.9.4 Multiplexing
2.9.4.1 Wavelength-Division Multiplexing
2.9.4.2 Time-Division Multiplexing
2.9.5 Optical Amplifiers
2.9.6 Free-Space Optical Interconnect
2.10 Radio Communication
2.10.1 A Typical Digital Radio
2.10.2 The Power Equation
2.10.3 Modulation
2.10.3.1 Amplitude Modulation
2.10.3.2 Phase Modulation (PM)
2.10.3.3 Frequency Modulation
2.10.3.4 Code-Division Multiple Access (CDMA)
2.10.4 Multipath
2.11 Bibliographic Notes
2.12 Exercises
3. Modeling and Analysis of Wires
3.1 Geometry and Electrical Properties
3.1.1 Resistance
3.1.2 Capacitance
3.1.3 Inductance
3.2 Electrical Models of Wires
3.2.1 The Ideal Wire
3.2.2 The Transmission Line
3.2.2.1 Partial Differential Equation
3.2.2.2 Impedance of an Infinite Line
3.2.2.3 Frequency-Domain Solution
3.2.2.4 Signal Returns
3.2.2.5 Lumped Models of Transmission Lines
3.3 Simple Transmission Lines
3.3.1 Lumped Wires
3.3.1.1 Lumped Capacitive Loads
3.3.1.2 Lumped Resistive Lines
3.3.1.3 Lumped Inductive Lines
3.3.1.4 Lumped Models of Impedance Discontinuities
3.3.2 RC Transmission Lines
3.3.2.1 Step Response of an RC Line
3.3.2.2 Low-Frequency RC Lines
3.3.3 Lossless LC Transmission Lines
3.3.3.1 Traveling Waves
3.3.3.2 Intpedance
3.3.3.3 Driving LC Transntission Lines
3.3.3.4 Reflections and the Telegrapher's Equation
3.3.3.5 Some Common Terminations
3.3.3.6 Source Termination and Multiple Reflections
3.3.3.7 Arbitrary Termination
3.3.3.8 Standing Waves
3.3.3.9 Summary
3.3.4 Lossy LRC Transmission Lines
3.3.4.1 Wave Attenuation
3.3.4.2 DC Attenuation
3.3.4.3 Combined Traveling Wave and Diffusive Response
3.3.4.4 The Skin Effect
3.3.5 Dielectric Absorption
3.4 Special Transmission Lines
3.4.1 Multidrop Buses
3.4.2 Balanced Transmission Lines
3.4.3 Common- and Differential-Mode Impedance
3.4.4 Isolated Lines
3.4.4.1 AC Coupling
3.4.4.2 Optical Isolation
3.5 Wire Cost Models
3.5.1 Wire Area Costs
3.5.2 Terminal Costs
3.6 Measurement Techniques
3.6.1 Time-Domain Measurements
3.6.1.1 The Time-Domain Reflectometer
3.6.1.2 Rise Time and Resolution
3.6.1.3 Lumped Discontinuities
3.6.1.4 Transmission Measurements
3.6.1.5 Cross Talk Measurements
3.6.2 Network Analysis
3.6.3 CAD Tools for Characterizing Wires
3.6.3.1 Spreadsheets
3.6.3.2 Two-Dimensional Electromagnetic Field Solvers
3.6.3.3 Signal Integrity Software Packages
3.6.3.4 3D Electromagnetic Field Solvers
3.7 Some Experimental Measurements
3.7.1 Frequency-Dependent Attenuation in a PC Board Trace
3.7.1 .1 DC Resistance and Attenuation Calculations
3.7.1 .2 High-Frequency Attenuation Factors
3.7.2 Cross Talk in Coupled Lines
3.7.2. 1 Coupled Embedded Striplines
3.7.2.2 Coupled Inhomogeneous Lines
3.7.2.3 Coupling Between Lines at Right Angles
3.7.3 Inductive and Capacitive Discontinuities
3.7.4 Measurement ofIe Package Parasitics
3.7.5 Measurement Practice
3.8 Bibliographic Notes
3.9 Exercises
4. Circuits
4.1 MOS Transistors
4.1.1 MOS Device Structure
4.1.2 Current-Voltage Characteristics
4.1.2.1 Threshold Voltage
4.1.2.2 Resistive Region
4.1.2.3 Saturation Region
4.1.2.4 p-Channel FETs
4.1.2.5 Channel-Length Modulation
4.1.2.6 Body Effect
4.1.2.7 Velocity Saturation
4.1.2.8 Subthreshold Conduction
4.1.2.9 Typical I-V Curves
4.1.2.10 Enhancement and Depletion Devices
4.1.3 Parameters for a Typical O.35-um CMOS Process
4.2 Parasitic Circuit Elements
4.2.1 Parasitic Capacitors
4.2.1.1 Gate Capacitance
4.2.1.2 Source and Drain Diodes
4.2.2 Parasitic Resistance
4.2.3 A Typical Device
4.2.4 SPICE Models
4.3 Basic Circuit Forms
4.3.1 Switch Networks
4.3.1.1 Pass Gates
4.3.1.2 Logic with Switches
4.3.1.3 Circuits Using Switches
4.3.1.4 Transient Analysis of Switch Networks
4.3.2 The Static CMOS Gate
4.3.2.1 Inverter DC Transfer Characteristics
4.3.2.2 Inverter Gain
4.3.2.3 Transient Response
4.3.2.4 Propagation Delay and Nonzero Rise Time
4.3.2.5 The Effect of Input Rise Time on Delay
4.3.2.6 Asymmetrical Sizing
4.3.2.7 Miller-Effect Capacitance
4.3.2.8 Gain-Bandwidth Product
4.3.2.9 The Exponential Horn
4.3.2.10 SPICE Simulations of Gates
4.3.3 Dynamic Circuits
4.3.3.1 The Dynamic Latch
4.3.3.2 Precharged Gates
4.3.3.3 Domino Logic
4.3.3.4 Dual-Rail Domino
4.3.3.5 Bootstrap Circuits
4.3.4 Source Followers and Cascodes
4.3.4.1 Source Follower
4.3.4.2 Cascode
4.3.5 Current Mirrors
4.3.5.1 The Basic Current Mirror
4.3.5.2 The Cascode Current Mirror
4.3.6 The Source-Coupled Pair
4.3.6.1 V-I Characteristics of the Source-Coupled Pair
4.3.6.2 Differential Circuit Analysis
4.3.6.3 Differential Loads
4.3.6.4 Mode Coupling
4.3.6.5 FET Resistors
4.3.6.6 A Simple Differential Amplifier
4.3.7 Regenerative Circuits and Clocked Amplifiers
4.4 Circuit Analysis
4.4.1 Qualitative Circuit Analysis
4.4.1.1 Qualitative Analysis of a Differential Amplifier
4.4.1.2 Qualitative Analysis of a Voltage-Controlled Oscillator
4.4.2 Power Dissipation
4.4.2.1 Power Dissipation of a Static CMOS Gate
4.4.2.2 Energy-Delay Product of a CMOS Gate
4.4.2.3 AC Versus DC Power
4.4.2.4 Power Dissipation of Source-Coupled FET Logic
4.5 Bibliographic Notes
4.6 Exercises
5. Power Distribution
5.1 The Power Supply Network
5.1.1 Local Loads and Signal Loads
5.1.1.1 Local Loads
5.1.1.2 Signal Loads
5.1.2 Inductive Power Supply Noise
5.2 Local Regulation
5.2.1 Clamps and Shunt Regulators
5.2.2 Series Regulators
5.2.2.1 Linear Regulator
5.2.2.2 Switching Regulator
5.3 Logic Loads and On-Chip Power Supply Distribution
5.3.1 Logic Current Profile
5.3.2 IR Drops
5.3.3 Area Bonding
5.3.4 Metal Migration
5.3.5 On-Chip Bypass Capacitors
5.3.6 Symbiotic Bypass Capacitance
5.4 Power Supply Isolation
5.4.1 Supply-Supply Isolation
5.4.2 Signal-Supply Isolation
5.5 Bypass Capcitors
5.6 Example Power Distribution System
5.7 Bibliographic Notes
5.8 Exercises
6. Noise in Digital Systems
6.1 Noise Sources in a Digital System
6.2 Power Supply Noise
6.2.1 Single Supply Noise
6.2.2 Differential Supply Noise
6.2.3 Internal and External Supply Noise
6.3 Cross Talk
6.3.1 Cross Talk to Capacitive Lines
6.3.1.1 Coupling to a Floating Line
6.3.1.2 Coupling to a Driven Line
6.3.1.3 Typical Capacitance Values
6.3.1.4 Capacitive Cross Talk Countermeasures
6.3.2 Cross Talk Between Transmission Lines
6.3.2.1 Capacitive and Inductive Coupling of Transmission Lines
6.3.2.2 Lumped Inductive Coupling
6.3.2.3 Near- and Far-End Cross Talk
6.3.2.4 Typical Coupling Coefficients
6.3.2.5 Transmission Line Cross Talk Countermeasures
6.3.3 Signal Return Cross Talk
6.3.4 Power Supply Cross Talk
6.4 Intersymbol Interference
6.4.1 Impedance Mismatch and Reflections
6.4.2 Resonant Transmitter Circuits
6.4.3 Inertial Delay and Hidden State
6.5 Other Noise Sources
6.5.1 Alpha Particles
6.5.2 Electromagnetic Interference
6.5.3 Process Variation
6.5.3.1 Typical Process Variations
6.5.3.2 Inverter Offset
6.5.3.3 Inverter Compensation
6.5.3.4 Differential Pair Offset
6.5.4 Thermal (Johnson) Noise
6.5.5 Shot Noise
6.5.6 Flicker or 1/f Noise
6.6 Managing Noise
6.6.1 Bounded Noise and Noise Budgets
6.6.1.1 Proportional Noise Sources
6.6.1.2 Fixed Noise Sources
6.6.1.3 Overall Noise Budgets
6.6.2 Gaussian Noise and Bit Error Rates
6.7 Bibliographic Notes
6.8 Exercises
7. Signaling Conventions
7.1 A Comprison of Two Transmission Systems
7.1.1 Signal Energy and System Power
7.1.2 Noise Immunity Versus Noise Margin
7.1.3 Delay
7.1.4 Discussion
7.2 Considerations in Transmission System Design
7.3 Signaling Modes for Transmission Lines
7.3.1 Transmitter Signaling Methods
7.3.1.1 Current-Mode Transmission
7.3.1.2 Voltage-Mode Transmission
7.3.1.3 Transmitter Signal-Return Cross Talk
7.3.1.4 Bipolar Versus Unipolar Signaling
7.3.1.5 Transmitter-Generated References
7.3.2 Receiver Signal Detection
7.3.2.1 Generating the Receiver Reference
7.3.2.2 Receiver Return Cross Talk
7.3.2.3 Power Supply Noise
7.3.3 Source Termination
7.3.3.1 Noise Considerations
7.3.3.2 Power Dissipation
7.3.3.3 Current-Mode Source Termination
7.3.4 Underterminated Drivers
7.3.5 Differential Signaling
7.3.5.1 Symmetric Transmission Lines
7.4 Signaling Over Lumped Transmission Media
7.4.1 Signaling Over a Capacitive Transmission Medium
7.4.1.1 Voltage-Mode Signaling
7.4.1.2 Current-Mode Signaling
7.4.1.3 Resistive Voltage Divider
7.4.1.4 Pulsed Signaling
7.4.1.5 Return-to-Zero (Precharged) Pulsed Signaling
7.4.1.6 Band-Limited Pulsed Signaling
7.4.1.7 References
7.4.2 Signaling over Lumped LRC Interconnect
7.4.2.1 Rise-Time Control
7.4.2.2 Adding Parallel Termination
7.4.2.3 Reducing Power Supply Noise
7.5 Signal Encoding
7.5.1 Number of Signal Levels
7.5.2 Signal Magnitude
7.5.2.1 Hysteresis
7.5.3 Signal Transfer Function
7.5.4 Error Correcting Codes
7.5.5 Pulsed Signaling
7.5.6 Signal Level and Delay
7.6 Bibliographic Notes
7.7 Exercises
8. Advanced Signaling Techniques
8.1 Signaling over RC Interconnect
8.1.1 Circuit Model
8.1.2 Repeaters
8.1.3 Increasing Wire Width and Spacing
8.1.4 Overdrive of Low-Swing RC Lines
8.2 Driving Lossy LC Lines
8.2.1 The Lone Pulse
8.2.2 Equalization of LRC Lines
8.3 Simultaneous Bidirectional Signaling
8.3.1 Current-Mode Bidirectional Signaling
8.3.2 Bidirectional Signaling Waveforms
8.3.3 Differential Simultaneous Bidirectional Signaling
8.3.4 Voltage-Mode Simultaneous Bidirectional Signaling
8.3.5 Reverse-Channel Cross Talk
8.4 AC and N of M Balanced Signaling
8.4.1 Terminology
8.4.1.1 DC Offset
8.4.1.2 Run Length
8.4.1.3 Disparity or Digital-Sum Variation (DSV)
8.4.2 Codes for DC-Balancing Signals
8.4.2.1 Nonoveriapping Block Codes
8.4.2.2 Running-Disparity Encoding
8.4.2.3 Framing
8.4.2.4 Burst-Error Length
8.4.2.5 The 8b/10b Code
8.4.2.6 DC Restoration
8.4.3 Spatial N of M Balanced Signaling
8.4.3.1 Coding Efficiency
8.4.3.2 Systematic Encoding
8.5 Examples
8.5.1 Logic Signaling
8.5.2 SRAM Bit Lines
8.5.3 Signaling Over Long On-Chip Wires
8.5.4 Signaling Chip-to-Chip on a Board
8.5.5 Signaling across a Cable
8.6 Bibliographic Notes
8.7 Exercises
9. Timing Conventions
9.1 A Comparison of Two Timing Conventions
9.1.1 Skew and Jitter Analysis
9.1.2 Allowable Clock Rates
9.1.3 Discussion
9.2 Consideration in Timing Design
9.3 TIMING FUNDAMENTALS
9.3.1 Timing Nomenclature
9.3.1.1 Delay and Transition Times
9.3.1.2 Periodic Signals
9.3.1 .3 Maximum Absolute Value, Peak-to-Peak, and RMS
9.3.2 Timing Properties of Delay Elements
9.3.3 Timing Properties of Combinational Logic
9.3.4 Timing Properties of Clocked Storage Elements
9.3.4.1 Edge-Triggered Flip-Flop
9.3.4.2 Level-Sensitive Latch
9.3.4.3 Double-Edge-Triggered Flip-Flop
9.3 .. 5 The Eye Diagram
9.4 ENCODING TIMING: SIGNALS AND EVENTS
9.4.1 Encoding Aperiodic Events
9.4.1.1 Dual-Rail Signaling
9.4.1.2 Return-to-Zero (RZ)lNonreturn-to-Zero (NRZ) Signaling
9.4.1.3 Clocked Signaling and Bundling
9.4.1.4 Ternary Signaling
9.4.2 Encoding Periodic Signals
9.4.2.1 Required Transition Frequency
9.4.2.2 Bit Stuffing
9.4.2.3 Phase-Encoding
9.5 Open-Loop Synchronous Timing
9.5.1 Global Clock, Edge-Triggered Timing
9.5.1.1 Minimum Delay Constraint
9.5.1.2 Maximum Delay Constraint
9.5.2 Level-Sensitive Clocking
9.5.2.1 Basic Two-Phase Clocking
9.5.2.2 Borrowing Time
9.5.2.3 Effect of Skew
9.5.2.4 Qualified Clocks
9.5.2.5 Signal Labeling for Two-Phase Clocking
9.5.2.6 Single-Phase or Zero Nonoverlap Clocking
9.5.3 Pipeline Timing
9.5.3.1 Optimum Clock Delay
9.5.3.2 Level-Sensitive Pipeline Timing
9.5.3.3 Pipelines With Feedback
9.6 Closed-Loop Timing
9.6.1 A Simple Timing Loop
9.6.1.1 Residual Error
9.6.1.2 Loop Dynamics
9.6.2 Phase Comparators
9.6.2.1 Flip-Flop Phase Comparator
9.6.2.2 Exclusive-Or (XOR) Phase Comparator
9.6.2.3 Sequential Phase and Frequency Comparator
9.6.3 Variable Delay Line
9.6.4 Bundled Closed-Loop Timing
9.6.4.1 Canceled and Uncanceled Sources of Timing Uncertainty
9.6.4.2 Integrating Receivers
9.6.5 Per-Line Closed-Loop Timing
9.6.6 Phase-Locked Loops
9.6.6.1 Voltage-Controlled Oscillators
9.6.6.2 Frequency Comparator
9.6.6.3 Loop Dynamics and Loop Filter
9.6.6.4 Reducing Jitter with a Phase-Locked Loop
9.6.7 Oversampling Clock Recovery
9.7 Clock Distribution
9.7.1 Off-Chip Clock Distribution
9.7.1.1 Clock Distribution Trees
9.7.1.2 Phase-Locked Clock Distribution Networks
9.7.1.3 Salphasic Clock Distribution
9.7.1.4 Round-Trip Distribution
9.7.2 On-Chip Clock Distribution
9.7.2.1 On-Chip Clock Trees
9.7.2.2 Mesh Distribution
9.7.2.3 Jitter in On-Chip Clock Distribution
9.8 Bibliographic Notes
9.9 Exercises
10. Synchronization
10.1 A Comparison of Three Synchronization Strategies
10.2 Synchronization Fundamentals
10.2.1 Uses of Synchronization
10.2.1.1 Arbitration of Asynchronous Signals
10.2.1.2 Sampling Asynchronous Signals
10.2.1.3 Crossing Clock Domains
10.2.2 Synchronization Failure and Metastability
10.2.2.1 Synchronizer Dynamics and Synchronization Time
10.2.2.2 Metastability
10.2.2.3 Probability of Synchronization Failure
10.2.2.4 Example Synchronizer Calculation
10.2.2.5 Completion Detection
10.2.2.6 Common Synchronizer Mistakes
10.2.3 Clock Domains
10.2.3.1 Independent Clock Rates
10.2.3.2 Simplified Clock Distribution
10.2.3.3 Pipelined Signal Timing Eliminates Cable Delay Constraints
10.2.3.4 Aperiodic Clocks
10.2.4 Classification of Signal-Clock Synchronization
10.3 Synchronizer Design
10.3.1 Mesochronous Synchronizers
10.3.1.1 Delay-Line Synchronizer
10.3.1.2 Two-Register Synchronizer
10.3.1.3 FIFO Synchronizer
10.3.1.4 Brute-Force Synchronization
10.3.2 Plesiochronous Synchronizers
10.3.2.1 A Plesiochronous FIFO Synchronizer
10.3.2.2 Data Rate Mismatch
10.3.2.3 Detecting Phase Slip
10.3.2.4 Null Symbols and Flow Control
10.3.3 Periodic Asynchronous Synchronizers
10.3.3.1 Clock Predictor Circuit
10.3.3.2 Periodic Synchronizer
10.3.4 General Purpose Asynchronous Synchronizers
10.3.4.1 Waiting Synchronizer
10.3.4.2 Asynchronous FIFO Synchronizer
10.4 Asychronous Design
10.4.1 Stoppable Clocks
10.4.2 Asynchronous Signaling Protocols
10.4.2.1 Four-Phase Asynchronous Signaling
10.4.2.2 Two-Phase Asynchronous Signaling
10.4.2.3 The Weak Conditions
10.4.3 Asynchronous Module Design Methods
10.4.3.1 State Diagrams
10.4.3.2 Concurrency and Choice
10.4.3.3 Trajectory Maps for Designing Asynchronous Sequential Logic
10.4.3.4 Set-Reset Excitation Equations
10.4.3.5 Arbitration and Circuits with Choice
10.4.3.6 Delay-Insensitive versus Matched-Delay Modules
10.4.4 Composition of Asynchronous Circuits
10.4.4.1 Asynchronous Combinational Blocks
10.4.4.2 Align Blocks and Self-Timed Pipelines
10.4.4.3 Cyclic Asynchronous Circuits
10.5 Bibliographic Notes
10.6 Exercises
11. Signaling Circuits
11.1 Terminations
11.1.1 On-Chip Versus Off-Chip Termination
11.1.2 FET Terminations
11.1.3 Adjustable Terminators
11.1.3.1 Digital Versus Analog Adjustment
11.1.3.2 Binary Versus Thermometer Digital Adjustment Codes
11.1.4 Automatic Terminator Adjustment
11.1.4.1 Automated Adjustment Controllers
11.1.4.2 Thermometer-Coded Controllers
11.1.4.3 Self-Series Termination Control
11.2 Transmitter Circuits
11.2.1 Voltage-Mode Driver
11.2.1.1 Break-Before-Make Action
11.2.1.2 Pulse-Generating Driver
11.2.1.3 Tristate Driver
11.2.1.4 Open-Drain Outputs
11.2.2 Self-Series-Terminating Drivers
11.2.3 Current-Mode Drivers
11.2.3.1 Saturated FET Driver
11.2.3.2 Current-Mirror Drivers
11.2.3.3 Differential Current-Steering Driver
11.2.3.4 Bipolar Current-Mode Drivers
11.2.4 Rise-Time Control
11.2.4.1 Segmented Current Driver
11.2.4.2 The Problem with RC Rise-Time Control
11.2.4.3 Segmented Voltage Driver
11.2.4.4 Segmented Self-Series Terminated Driver
11.2.5 Drivers for Lumped Loads
11.2.5.1 On-Chip Drivers for Capacitive Loads
11.2.5.2 Off-Chip Drivers for LRC Loads
11.2.6 Multiplexing Transmitters
11.3 Receiver Circuits
11.3.1 Receivers Using Static Amplifiers
11.3.1.1 The Inverter As a Receiver
11.3.1.2 Source-Coupled FET Receivers
11.3.2 Receivers Using Clocked Differential Amplifiers
11.3.3 Integrating Amplifiers
11.3.3.1 An Integrating Amplifier
11.3.3.2 Receiver Impulse Response
11.3.3.3 A Matched-Filter Receive Amplifier
11.3.4 DemuItiplexing Receivers
11.4 Electrostatic Discharge (ESD) Protection
11.4.1 ESD Failure Mechanisms
11.4.1.1 Field-Induced Failures
11.4.1.2 Thermally Induced Failures
11.4.2 ESD Protection Devices
11.4.2.1 Primary Shunt
11.4.2.2 Series Resistor
11.4.2.3 Secondary Shunt
11.4.2.4 Protecting Output Drivers
11.4.2.5 Guard Rings
11.4.2.6 Wiring and Contacting
11.5 An Example Signaling System
11.5.1 Transmitter
11.5.1.1 Multiphase Clock Generator
11.5.1.2 Output Driver
11.5.1.3 Bias Generator
11.5.1.4 Predriver
11.5.1.5 Latches and Pass-Gate Clocking Network
11.5.1.6 Package Model
11.5.1.7 Transmission Line Model
11.5.1.8 Simulation Results for Package and Transmission-Line Models
1 1.5.1.9 Termination Schemes
11.5.1.10 Effectiveness of Slew-Rate Control
11.5.1.11 Noise Modeling
11.5.2 Receiver
11.5.2.1 Phase Shifter and Multiphase Clock Generator
1 1.5.2.2 Samplers
1 1.5.2.3 Retiming Latches
11.5.2.4 Clock Adjuster
11.6 Bibliographic Notes
11.7 Exercises
12. Timing Circuits
12.1 Latches and Flip-Flops
12.1.1 Level-Sensitive Latches
12.1.1.1 Dynamic Latches
12.1.1.2 CMOS Static Storage Element
12.1.1.3 CMOS Static Latches
12.1.2 Edge-Triggered Flip-Flops
12.1.2.1 Auxiliary Control Inputs
12.1.2.2 True Single-Phase-Clocked (TSPC) Flip-Flops
12.1.2.3 Differential Edge-Triggered Flip-Flop
12.1.2.4 Double-Edge-Triggered Flip-Flops
12.1.3 Failure Mechanisms in Flip-Flops and Latches
12.1.3.1 Race-Through
12.1.3.2 Dynamic Node Discharge
12.1.3.3 Power Supply Noise
12.1.3.4 Clock Slope
12.1.3.5 Charge Sharing
12.2 Delay Line Circuits
12.2.1 Inverter Delay Lines
12.2.1.1 Delay Adjustment Range
12.2.1.2 Power-Supply Rejection in Inverter Delay Elements
12.2.1.3 Inverters with Regulated Supply Voltage
12.2.2 Differential Delay Elements
12.2.2.1 Adjustable PFET Resistor
12.2.2.2 Replica-Biased Delay Line
12.2.2.3 Adjustment Range for Replica-Bias Delay Lines
12.2.2.4 Static Supply Sensitivity for the Replica-Biased Delay Stage
12.2.2.5 Dynamic Supply Sensitivity
12.2.3 Circuit and Layout Details
12.2.3.1 Replica Control Loop Stability
12.2.3.2 Power Routing and Bypassing
12.2.3.3 Matching and Balancing
12.2.3.4 Substrate Noise
12.2.4 Other Differential Timing Components
12.2.4.1 Small-Swing to Full-Swing Buffers
12.2.4.2 Interpolators
12.2.4.3 Duty-Cycle Correctors
12.2.4.4 Clock Input Conditioning
12.3 Voltage-Controlled Oscillators
12.3.1 First-Order Oscillators
12.3.1.1 Array Oscillators
12.3.2 Second-Order Oscillators
12.3.2.1 Crystal Oscillators
12.3.2.2 Frequency Multiplication
12.3.2.3 Lumped-Element Oscillators
12.4 Phase Comparators
12.4.1 XOR Comparator
12.4.2 Edge-Triggered Flip-Flop Phase Detector
12.4.3 Sequential Phase Detectors
12.5 Loop Filters
12.5.1 RC Loop Filters
12.5.2 Charge Pump Filters
12.5.2.1 Charge Pump Control Voltage Ripple
12.5.2.2 Self-Biased Loop Filters
12.5.3 Delay-Locked Loop Filters
12.5.3.1 Self-Biased DLL Loop Filter
12.5.3.2 Switched-Capacitor Loop Filters
12.5.3.3 Loop Initialization
12.5.3.4 "Thrbo" Mode
12.5.3.5 "Bang-Bang" Controllers
12.5.3.6 Digital Loop Controllers
12.6 Clock Aligners
12.6.1 PLL Versus DLL Implementations
12.6.2 Simple DLL-Based Aligners
12.6.3 Phase-Based Aligners
12.6.4 A Hybrid Phase/Delay-Based Clock Aligner
12.7 Bibliographic Notes
12.8 Problems
References
Index
Tables
Power and Noise
Thermal Conductivity of Various Materials
Transmission-Line Equations
DIGITAL
SYSTEMS
ENGINEERING
WILLIAM J . DALLY
JOHN W. POULTON
DIGITAL
SYSTEMS
ENGINEERING
WILLIAM J. DALLY
JOHN W. POULTON
... � ..... CAMBRIDGE
::: UNIVERSITY PRESS
PUBLISHED
The Pitt Building,
BY THE PRESS SYNDICATE OF THE UNIVERSITY
OF CAMBRIDGE
Trumpington
Street,
Cambridge
CB2 !RP, United
Kingdom
CAMBRIDGE UNIVERSITY
The Edinburgh
40 West 20th Street,
IO Stamford
New York,
Road, Oakleigh,
PRESS
Building, Cambridge
NY 10011-4211,
CB2 2RU, UK http://www
USA http://www
.cup.cam.ac.uk
.cup.org
Melbourne
3166, Australia
© William
J. Dally and John W. Poulton
1998
This book is in copyright.
and to the provisions
no reproduction
the written
Subject
of relevant
permission
of any part may take place without
of Cambridge
University
Press.
to statutory
exception
collective
licensing
agreements,
First published
1998
Printed
in the United
States
of America
Typeset
in Times Roman 10.5/13
pt. and
Copperplate
Gothic
in IbT}:lX [TB]
A catalog
the British
record
Library
for this book is available
from
Library of Congress
Cataloging-in-Publication
Data
Dally,
William
J.
Digital
systems
engineering
/ William
J. Dally,
John W. Poulton.
p. cm.
Includes
bibliographical
references
ISBN 0-521-59292-5
(hb)
I.Electronic
I. Poulton,
John W. II. Title.
digital
computers
-Design and construction.
2. Digital
Integrated
circuits.
TK7888.3.D2934
621.39
-dc2 I
1998
ISBN O 521 59292 5 hardback
97-4 3 730
CIP
The photo on the cover shows three of the authors'
trace showing
an eye diagram
of an equalized
projects.
4Gb/s signaling
J-Machine,
In the foreground
system jointly
an experimental
parallel
is
About the cover:
an oscilloscope
developed
computer
PixelF!ow
his colleagues
at UNC.
Behind this trace is a 512-processor
by the authors.
developed
EMC chip, the heart of a high-performance
by Dally and his group at MIT.
graphics
In the background
of a
is a plot of the layout
and
by Poulton
system developed
Physical Comtants
Name
Symbol
Value Unils
3.00x 108 mis
l.38x 10-23 J/K
l.60x 10-19 C
mV
F/m
Him
8.85 X 10-12
47tX 10-7
C
Speed of light in vacuum
Boltzmao's constant ku
Charge on e1ectron
q
Thennal voltage (@
Permittivity of vacuum
Permeability of vacuum J1o
E°<)
300 K) +!=k8T/q 25.9
Silicon Constants
Symbol or Formula Value Units Alternate
Units
Name
of Silicon £si= Ersi•f°<>
Pennittivity
Pennittivity
of SiO2
Breakdown
SiO2
Voltage,
Bulk Mobility, Electrons
Bulk Mobility,
Intrinsic
in Silicon
Carrier Concentration
Holes l1p
µn
Dj
£si = Ersi02•f°<>
l.04x 10-10 F/m 104 aF/µm
3.45 X 10-II F/m 34.5 aF/µm
Vim 0.7V/nm
7x 108
0.135 m2N•s
0.048
1.45 X (016 1/m3
N•s
2
m
Relative
Constant,
Permittivity (Dielectric
£i,) of Various Materials
Bull Resistirity of Various
Value
Value
Pure �etals (p in il•Dl)
Material
Silver
(Ag) 1.6 X 10-8
Copper(Cu) 1.7 X 10-8
Gold (Au) 2.2x to-8
Aluminum (Al) 2.8 X 10-B
Tungsten (W) 5.3 X 10-8
Material
Dioxide (SiO2)
Silicon
Silicon Nitride {Si3N4) 7.5
Beryllia
(BeO)
Alumina (Al2O3)
Epoxy Glass (FR-4) 4.5-5.0
Polyimide
Teflon
3.5--4.5
2.2-2.8
9.5
3.9
7.3
Drain Current
MOSFET Equations
W
Device
Proc:ess
Transconductance P = k "[
Transconductance
r ox
Subthreshold
k = µ£5;02
W.L = wid1h.
length
µ = µ11• electron
= µP. hole mobility (PFETs)
of device
mobili1y
(NFETs)
Conduction
IDS � 0 when VG T < 0
Subthresholcl
Drain Current
Body Effect
Threshold Voltage V'r = Vrj = Vro+Y[(2j41i:j+Vsal
112-<21$�)112I
Body-Effect
VsB>U
lg. a. and n are process dependent
Vro = Vrl. _ and lo,I
= kT1nt:!. N is lhe dopant atom concentratio
n
�-'" -0
q n;
Typical Parameters
for 0.35µrn Process
Parameter Description
v. = VrN+ �(
rnv
�
V00+ Vrrl t = v1>0c0a,,, t;11,. = 3t"
l + JP plji N " I DSSN (t,n,
...
-�< for 0.35µm process)
Oela)' lhruugh FOi in,-ener:
(iain-handwidth
producl
ofim,:rler:
Vr
k
y
NFET
voltage +o.5V
200µNV2
1ransconductance
Threshold
Process
Gate o>tide thickness
Channel length
Body effect parameter
modulation
7nm
1
PFET
-0.5 V
50µA/V2
0.1 v-
0.3 V112 -•on_
(',ain r-req r,
Inverter
� -··�h-
Power and Noise
Bypas.1ing
I I
O>c= -
�tF�
of LC Circull
Bypaa Capac1w
Sac Cs> AV k;fct+ AV lck is the clock period. la,·g is the time-averaged
current
ripple voltage.
consumption.
Typical values
and AV is the maximum allowed
for k; are 0.25-0.S
l,,..g( Llu,·g)
lavg)d�
k-= maxlJou-
, I la,·c1cA:
Noise 1
Sfpaliag
Noiselaa V
Syste m Noise = N Signal+ NFi.ud
K V V
kc+kl
kNeurEnd
= -4-
(kc-k1)
kFa,End =
C.,.......mefkients
bet-..coupled ............,
• ._
kc=kL, and:
For homogeneous coupled lines.
'(CM LM) CM
kNearEnd
= 4 C + T = 2C
'(CM LM)
kF,.rEnd = 2 C-L = O
is the resistance in 0.
where kc and kL are the
and inductive
capacitive
constants
coupling
between the two lines.
2 ,
in K. R
where Tis temperature
and 8 is the bandwidth
in Hz: v,R is in volts.
where q is the electron
charge. / is the current in the
circuit.
and B is the bandwidth in Hz; l,R is in amperes.
Bit Error Rate (BER)
(VSNR2
P(error) = exp - 2-
)
Pis the probability
VSNR voltage signal-to-noise
ratio. In
Pis sampled once per bit. and P = BER.
of an error in a signaling
typical
system with
signaling
systems
Thermal
Conductivity of
Various
Materials
(Kin W/m•K)
Material Value
Silicon
(Si)
Silicon Dioxide
150
(Si02) 1.5
Copper {Cu)
Aluminum (Al)
Berylia (BeO)
Alumina (Al203)
Epoxy Glass (FR-4)
420
240
220
35
0.2
Polyimide/Glass
0.3
Teflon/Glass
0.3
IIIIIII\\Hiillilllllll
WB208482
\l\il\\1\\\\1\1\1\1\1
WB208482
I
1,
-
-
-
:3E:]I"
Transmission-Line
Equations
Slighdy Lossy Line I
Zo = (R+Ls) �I
Characteristic
Impedantt Propagation
G+Cs = C R.G-o
V = lic lR,G�O
Velocity
Coupled Lines
Even-Mode
Impedance
�
Odd-Mode
Zodd = - -
� \..: Li.t c�
Impedance
I ef. R zfa·n = --
Telegrapher's Equation I
V, I, Zr-Zo
Reflection k =-=-=-
7.e - :J zr
Coefficient ' V; I; Zr+Z0
g 4
Skin Effect I 1-w -lj_
Skin Depth 6= _l_ �i:;;;;JT6
,Jxfµo
Skin Depth Frequency Is= p 1tµ(112/
I = .....e_ s 2nµr
�6
Skin Depth Resistance R(/) = J,c/µp = Rnc(.L)112 R(/) = .//µpin=Rnc(L)112
2w
2r 2 /.r
Attenuation
in Lossy Line I
[ ( R GZo) ]
Vi(L)
n)L) = exp -220 + 2 L x.!.
V;(O)= exp(-(cxR + cx
Attenuation
Rnc( 1y12
Rnc( !)'12
Condnctor
CXR(/) = 220 fs (Strip)
a.if) = 42 7 (Round)
Loss
0 .f
Dielectric Loss ran 6 = � = Oo;.,/
Loss
Dielectric
n.Ji,1ano
Tangent
CXn(/) = r I
we we,
(Homogeneous)
L = £µ/C ) I
R,C,7,o for Various Geometries (Homogeneous Dielectric,
t-W-1 h
r
r
t- w ---1 1 @....,.. s
_L--,-s I
e:;: s'
•ts
Rnc = 2:hRnc = .£... + p
Rnc = .£..xr2
Rnc = .£..wh
Rnc = -2 1tr
2 2 2
1tr1 1t(r3 -r2)
C = 1t£
c £w 2Jte
C = Jtt log(s/r)
C = 21ttlog(r2/r1)
C = £W
==-+ s log(s/w)
log(2s/r)
_ �log(r2/r1)
20 = jJog(s/r)
z = �log(2s/r)
0 £ 1t
Zo=� C
£ Jt
Zo - -e 2n
V�L)I
-----
s
Zo = �.!..
e.W
e-1- 2p
tnV�WIIVe
V;(O)I
C
....L..
f.r
x=L
-
CONTENTS
Preface
Acknowledgment
1 INTRODUCTION TO DIGITAL SYSTEMS
ENGINEERING
1.1 Why Study Digital
Systems
Engineering?
1.2 An Engineering
View of a Digital
System
1.2.1 Feeds and Speeds
xxi
XXV
page 1
2
4
5
6
1.2.2 Signaling
Signaling
Integrity,
Conventions
Speed, 7 • Signaling
8 • Other Signaling
Power, 7 • Signal
Conventions,
8
1.2.3 Timing and Synchronization
8 • Pipelined
9 •
9 • Clock Distribution,
Timing,
Timing,
Timing,
Synchronous
Closed-Loop
Synchron
ization,
10
9 •
8
1.2.4 Power Distribution
1.2.5 Noise
1.2.6 A Systems
View of Circuits
10
10
12
1.3 Technology
Trends
and Digital
Systems
Engineering 12
1.3.1 Moore's
Law
1.3.2 Scaling
of Chip Parameters
1.3.3 Scaling
Scaling
Communication,
Communication,
of Wires
of Power Distribution,
18 • Scaling
of Off-Chip
18 • Scaling
19
of On-Chip
1.3.4 High Levels
of Integration
Permit
New Approaches 21
1.3.5 Digital
to Change
Systems
Problems
and Solutions
Continue
12
16
17
21
22
22
22
1.4 Organization
of this Book
1.5 Bibliographic
Notes
1.6 Exercises
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