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msp430f5529数据手册.pdf
Features
Description
Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
Functional Block Diagram – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGCMSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQEMSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE, MSP430F5513IZQE
Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC
Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE
Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
Short-Form Description
CPU
Operating Modes
Interrupt Vector Addresses
Memory Organization
Bootstrap Loader (BSL)
USB BSL
UART BSL
JTAG Operation
JTAG Standard Interface
Spy-Bi-Wire Interface
Flash Memory
RAM Memory
Peripherals
Digital I/O
Port Mapping Controller
Oscillator and System Clock
Power Management Module (PMM)
Hardware Multiplier
Real-Time Clock (RTC_A)
Watchdog Timer (WDT_A)
System Module (SYS)
DMA Controller
Universal Serial Communication Interface (USCI)
TA0
TA1
TA2
TB0
Comparator_B
ADC12_A
CRC16
REF Voltage Reference
USB Universal Serial Bus
Embedded Emulation Module (EEM)
Peripheral File Map
Absolute Maximum Ratings
Thermal Packaging Characteristics
Recommended Operating Conditions
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
Schmitt-Trigger Inputs – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
Leakage Current – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
Outputs – General Purpose I/O (Full Drive Strength)(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
Outputs – General Purpose I/O (Reduced Drive Strength)(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
Output Frequency – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
Crystal Oscillator, XT1, Low-Frequency Mode
Crystal Oscillator, XT2
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
Internal Reference, Low-Frequency Oscillator (REFO)
DCO Frequency
PMM, Brown-Out Reset (BOR)
PMM, Core Voltage
PMM, SVS High Side
PMM, SVM High Side
PMM, SVS Low Side
PMM, SVM Low Side
Wake-Up From Low-Power Modes and Reset
Timer_A
Timer_B
USCI (UART Mode), Recommended Operating Conditions
USCI (UART Mode)
USCI (SPI Master Mode), Recommended Operating Conditions
USCI (SPI Master Mode)
USCI (SPI Slave Mode)
USCI (I2C Mode)
12-Bit ADC, Power Supply and Input Range Conditions
12-Bit ADC, Timing Parameters
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
12-Bit ADC, Temperature Sensor and Built-In VMID
REF, External Reference
REF, Built-In Reference
Comparator_B
Ports PU.0 and PU.1
USB-Output Ports DP and DM
USB-Input Ports DP and DM
USB-PWR (USB Power System)
USB-PLL (USB Phase Locked Loop)
Flash Memory
JTAG and Spy-Bi-Wire Interface
Input/Output Schematics
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Port P5, P5.2, Input/Output With Schmitt Trigger
Port P5, P5.3, Input/Output With Schmitt Trigger
Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
Port P5, P5.6 to P5.7, Input/Output With Schmitt Trigger
Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
Port P8, P8.0 to P8.2, Input/Output With Schmitt Trigger
Port PU.0/DP, PU.1/DM, PUR USB Ports
Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Device Descriptors (TLV)
Revision History
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SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
MIXED SIGNAL MICROCONTROLLER
MSP430F551x
MSP430F552x
1FEATURES
• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultralow Power Consumption
– Active Mode (AM):
All System Clocks Active
290 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
150 µA/MHz at 8 MHz, 3.0 V, RAM Program
Execution (Typical)
– Standby Mode (LPM3):
Real-Time Clock With Crystal, Watchdog,
and Supply Supervisor Operational, Full
RAM Retention, Fast Wake-Up:
1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
Low-Power Oscillator (VLO),
General-Purpose Counter, Watchdog, and
Supply Supervisor Operational, Full RAM
Retention, Fast Wake-Up:
1.4 µA at 3.0 V (Typical)
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor
Operational, Fast Wake-Up:
1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.18 µA at 3.0 V (Typical)
• Wake-Up From Standby Mode in 3.5 µs
•
(Typical)
16-Bit RISC Architecture, Extended Memory,
up to 25-MHz System Clock
• Flexible Power Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
•
•
16-Bit Timer TA0, Timer_A With Five
Capture/Compare Registers
16-Bit Timer TA1, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TA2, Timer_A With Three
Capture/Compare Registers
16-Bit Timer TB0, Timer_B With Seven
Capture/Compare Shadow Registers
• Two Universal Serial Communication
•
•
Interfaces
– USCI_A0 and USCI_A1 Each Support:
– Enhanced UART Supports
Auto-Baudrate Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
– I2CTM
– Synchronous SPI
• Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V/1.8-V USB Power System
– Integrated USB-PLL
– Eight Input, Eight Output Endpoints
12-Bit Analog-to-Digital (A/D) Converter
(MSP430F552x Only) With Internal Reference,
Sample-and-Hold, and Autoscan Feature
•
• Comparator
• Hardware Multiplier Supporting 32-Bit
Operations
– Supply Voltage Supervision, Monitoring,
• Serial Onboard Programming, No External
Programming Voltage Needed
• Three Channel Internal DMA
• Basic Timer With Real-Time Clock Feature
• Family Members are Summarized in Table 1
• For Complete Module Descriptions, See the
MSP430x5xx Family User's Guide (SLAU208)
and Brownout
• Unified Clock System
– FLL Control Loop for Frequency
Stabilization
– Low Power/Low Frequency Internal Clock
Source (VLO)
– Low Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Watch Crystals (XT1)
– High-Frequency Crystals up to 32 MHz
(XT2)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this
contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per
the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
document
Copyright © 2009–2012, Texas Instruments Incorporated
MSP430F551x
MSP430F552x
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes, is optimized to achieve extended battery life in portable measurement applications. The
device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to
active mode in 3.5 µs (typical).
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 are microcontroller configurations with
integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital
converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock
module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 are microcontroller configurations with integrated USB
and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), hardware
multiplier, DMA, real
time clock module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and
MSP430FF5513 include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, etc. that require connectivity to
various USB hosts.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Channel A: Channel B:
UART/IrDA/
SPI/I2C
ADC12_A
(Ch)
Comp_B
(Ch)
I/O
Package
Type
Device
Flash
(KB)
SRAM
(KB) (1)
Timer_A (2)
Timer_B (3)
MSP430F5529
MSP430F5528
MSP430F5527
MSP430F5526
MSP430F5525
MSP430F5524
MSP430F5522
MSP430F5521
MSP430F5519
MSP430F5517
MSP430F5515
MSP430F5514
MSP430F5513
128
128
96
96
64
64
32
32
128
96
64
64
32
8 + 2
8 + 2
6 + 2
6 + 2
4 + 2
4 + 2
8 + 2
6 + 2
8 + 2
6 + 2
4 + 2
4 + 2
4 + 2
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
7
7
7
7
7
7
7
7
7
SPI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
14 ext / 2 int
10 ext / 2 int
14 ext / 2 int
10 ext / 2 int
14 ext / 2 int
10 ext / 2 int
10 ext / 2 int
14 ext/ 2 int
-
-
-
-
-
12
8
12
8
12
8
8
12
12
12
12
8
8
63
47
63
47
63
47
47
63
63
63
63
47
47
80 PN
64 RGC,
64 YFF,
80 ZQE
80 PN
64 RGC,
64 YFF,
80 ZQE
80 PN
64 RGC,
64 YFF,
80 ZQE
64 RGC,
80 ZQE
80 PN
80 PN
80 PN
80 PN
64 RGC,
80 ZQE
64 RGC,
80 ZQE
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2
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MSP430F551x
MSP430F552x
www.ti.com
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
Table 2. Ordering Information(1)
PACKAGED DEVICES(2)
TA
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN VQFN
(RGC)
PLASTIC 64-BALL DSBGA
(YFF)(3)
PLASTIC 80-BALL BGA
(ZQE)
–40°C to
85°C
MSP430F5529IPN
MSP430F5527IPN
MSP430F5525IPN
MSP430F5521IPN
MSP430F5519IPN
MSP430F5517IPN
MSP430F5515IPN
MSP430F5528IRGC
MSP430F5526IRGC
MSP430F5524IRGC
MSP430F5522IRGC
MSP430F5514IRGC
MSP430F5513IRGC
MSP430F5528IYFF
MSP430F5526IYFF
MSP430F5524IYFF
MSP430F5528IZQE
MSP430F5526IZQE
MSP430F5524IZQE
MSP430F5522IZQE
MSP430F5514IZQE
MSP430F5513IZQE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Product preview
Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,
MSP430F5521IPN
Copyright © 2009–2012, Texas Instruments Incorporated
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UnifiedClockSystem128KB96KB64KB32KBFlash8KB+2KB6KB+2KB4KB+2KBRAMMCLKACLKSMCLKI/O PortsP1/P22×8 I/OsInterrupt& WakeupPA1×16 I/OsCPUXV2andWorkingRegistersEEM(L: 8+2)XINXOUTJTAG/InterfaceSBWPAPBPCPDDMA3 ChannelXT2INXTOUT2PowerManagementLDOSVM/BrownoutSVSSYSWatchdogPort MapControl(P4)I/O PortsP3/P42×8 I/OsPB1×16 I/OsI/O PortsP5/P62×8 I/OsPC1×16 I/OsI/O PortsP7/P81×8 I/Os1PD1×11 I/Os×3 I/OsFull-speedUSBUSB-PHYUSB-LDOUSB-PLLMPY32TA0Timer_A5 CCRegistersTA1Timer_A3 CCRegistersTB0Timer_B7 CCRegistersRTC_ACRC16USCI0,1USCI_Ax:UART,IrDA, SPIUSCI_Bx:SPI, I2CADC12_A200 KSPS16 Channels(14 ext/2 int)Autoscan12 BitDVCCDVSSAVCCAVSSP1.xP2.xP3.xP4.xP5.xP6.xDP,DM,PURRST/NMITA2Timer_A3 CCRegistersREFVCOREMABMDBP7.xP8.xCOMP_B12 Channels
MSP430F551x
MSP430F552x
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN
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Copyright © 2009–2012, Texas Instruments Incorporated
PN PACKAGE(TOPVIEW)1234567891011121314151617181920616263646566676869707172737475767778798060595857565554535251504948474645444342414039383736353433323130292827262524232221P6.4/CB4/A4P6.5/CB5/A5P6.6/CB6/A6P6.7/CB7/A7P7.0/CB8/A12P7.1/CB9/A13P7.2/CB10/A14P7.3/CB11/A15P5.0/A8/VREF+/VeREF+P5.1/A9/VREF−/VeREF−AVCC1AVSS1P5.4/XINP5.5/XOUTP1.0/TA0CLK/ACLKP1.1/TA0.0P1.2/TA0.1P1.3/TA0.2DVCC2DVSS2VCOREMSP430F5529IPNMSP430F5527IPNMSP430F5525IPNMSP430F5521IPNRST/NMI/SBWTDIOPJ.3/TCKPJ.2/TMSPJ.1/TDI/TCLKPJ.0/TDOTEST/SBWTCKP5.3/XT2OUTP5.2/XT2INAVSS2V18VUSBVBUSPU.1/DMPURPU.0/DPVSSUP1.6/TA1CLK/CBOUTP1.5/TA0.4P1.7/TA1.0P2.2/TA2CLK/SMCLKP2.0/TA1.1P2.3/TA2.0P2.4/TA2.1P2.5/TA2.2P2.6/RTCCLK/DMAE0P2.7/UCB0STE/UCA0CLKP3.0/UCB0SIMO/UCB0SDAP3.1/UCB0SOMI/UCB0SCLP3.2/UCB0CLK/UCA0STEP3.3/UCA0TXD/UCA0SIMOP3.4/UCA0RXD/UCA0SOMIP7.4/TB0.2P7.5/TB0.3DVSS1DVCC1P1.4/TA0.3P2.1/TA1.2P3.6/TB0.6P3.7/TB0OUTH/SVMOUTP4.2/PM_UCB1SOMI/PM_UCB1SCLP4.1/PM_UCB1SIMO/PM_UCB1SDAP4.0/PM_UCB1STE/PM_UCA1CLKP4.5/PM_UCA1RXD/PM_UCA1SOMIP4.4/PM_UCA1TXD/PM_UCA1SIMOP4.3/PM_UCB1CLK/PM_UCA1STEP4.6/PM_NONEP4.7/PM_NONEP5.6/TB0.0P5.7/TB0.1P7.6/TB0.4P7.7/TB0CLK/MCLKP6.3/CB3/A3P6.2/CB2/A2P6.1/CB1/A1P6.0/CB0/A0P3.5/TB0.5P8.0P8.1P8.2
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Functional Block Diagram –
MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE
MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
MSP430F551x
MSP430F552x
Copyright © 2009–2012, Texas Instruments Incorporated
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UnifiedClockSystem128KB96KB64KB32KBFlash8KB+2KB6KB+2KB4KB+2KBRAMMCLKACLKSMCLKI/O PortsP1/P22×8 I/OsInterrupt& WakeupPA1×16 I/OsCPUXV2andWorkingRegistersEEM(L: 8+2)XINXOUTJTAG/InterfaceSBWPAPBPCDMA3 ChannelXT2INXTOUT2PowerManagementLDOSVM/BrownoutSVSSYSWatchdogPort MapControl(P4)I/O PortsP3/P41×5 I/Os1PB1×13 I/Os×8 I/OsI/O PortsP5/P61×6 I/OsPC1×14 I/Os1×8 I/OsFull-speedUSBUSB-PHYUSB-LDOUSB-PLLMPY32TA0Timer_A5 CCRegistersTA1Timer_A3 CCRegistersTB0Timer_B7 CCRegistersRTC_ACRC16USCI0,1USCI_Ax:UART,IrDA, SPIUSCI_Bx:SPI, I2CADC12_A200 KSPS12 Channels(10 ext/2 int)Autoscan12 BitDVCCDVSSAVCCAVSSP1.xP2.xP3.xP4.xP5.xP6.xDP,DM,PURRST/NMITA2Timer_A3 CCRegistersREFVCOREMABMDBCOMP_B8 Channels
MSP430F551x
MSP430F552x
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,
MSP430F5522IRGC
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RGC PACKAGE(TOPVIEW)MSP430F5528IRGCMSP430F5526IRGCMSP430F5524IRGCMSP430F5522IRGCP6.3/CB3/A3P6.2/CB2/A2P6.1/CB1/A1P6.0/CB0/A0P1.6/TA1CLK/CBOUTP1.7/TA1.0P2.0/TA1.1P2.1/TA1.2P2.2/TA2CLK/SMCLKP2.3/TA2.0P2.4/TA2.1P2.5/TA2.2P2.6/RTCCLK/DMAE0P2.7/UCB0STE/UCA0CLKP3.0/UCB0SIMO/UCB0SDAP3.1/UCB0SOMI/UCB0SCLP3.2/UCB0CLK/UCA0STEP6.4/CB4/A4P6.5/CB5/A5P6.6/CB6/A6P6.7/CB7/A7P5.0/A8/VREF+/VeREF+P5.1/A9/VREF−/VeREF−AVCC1AVSS1P5.4/XINP5.5/XOUTP1.0/TA0CLK/ACLKP1.1/TA0.0P1.2/TA0.1P1.3/TA0.2DVSS1DVCC1DVCC2DVSS2P4.2/PM_UCB1SOMI/PM_UCB1SCLP4.1/PM_UCB1SIMO/PM_UCB1SDAP4.0/PM_UCB1STE/PM_UCA1CLKP4.5/PM_UCA1RXD/PM_UCA1SOMIP4.4/PM_UCA1TXD/PM_UCA1SIMOP4.3/PM_UCB1CLK/PM_UCA1STEP3.3/UCA0TXD/UCA0SIMOP3.4/UCA0RXD/UCA0SOMIP4.6/PM_NONEP4.7/PM_NONE17641863196220612160225929523051315032492358245725562655275428533316341535143613371238114544634724813910409418427436445P1.4/TA0.3P1.5/TA0.4RST/NMI/SBWTDIOPJ.3/TCKPJ.2/TMSPJ.1/TDI/TCLKPJ.0/TDOTEST/SBWTCKP5.3/XT2OUTP5.2/XT2INAVSS2V18VUSBVBUSPU.1/DMPURPU.0/DPVSSUVCORENote: Power Pad connectionto Vrecommended.SS
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Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
MSP430F551x
MSP430F552x
Copyright © 2009–2012, Texas Instruments Incorporated
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UnifiedClockSystem128KB96KB64KBFlash4KB+2KBRAMMCLKACLKSMCLKI/O PortsP1/P22×8 I/OsInterrupt& WakeupPA1×16 I/OsCPUXV2andWorkingRegistersEEM(L: 8+2)XINXOUTJTAG/SBWInterfacePAPBPCPDDMA3 ChannelXT2INXT2OUTPowerManagementLDOSVM/SVSBrownoutSYSWatchdogPort MapControl(P4)I/O PortsP3/P42×8 I/OsPB1×16 I/OsI/O PortsP5/P62×8 I/OsPC1×16 I/OsI/O PortsP7/P81×8 I/Os1PD1×11 I/Os×3 I/OsFull-speedUSBUSB-PHYUSB-LDOUSB-PLLMPY32TA0Timer_A5 CCRegistersTA1Timer_A3 CCRegistersTB0Timer_B7 CCRegistersRTC_ACRC16USCI0,1USCI_Ax:UART,IrDA, SPIUSCI_Bx:SPI, I2CDVCCDVSSAVCCAVSSP1.xP2.xP3.xP4.xP5.xP6.xDP,DM,PURRST/NMITA2Timer_A3 CCRegistersCOMP_B12 ChannelsVCOREMABMDBP7.xP8.xREF
MSP430F551x
MSP430F552x
SLAS590H –MARCH 2009–REVISED FEBRUARY 2012
Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN
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