VHDLyJ
YiHwa Lai
2003/08/15
1
Wireless Access Technology Lab.
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VHDLy
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VHDLzyk
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2
National Chung Cheng University
VHDLy
3
Wireless Access Technology Lab.
VHDLvI
VHDL-Very High Speed Integrated Circuit Hardware Description Language
IBMBTexas InstrumentBIntermetricstdoiC
1983~eU
1987~wqwyA@
IEEE Std 1076-1987AS
VHDL 87C
1993~AsAs
93C
IEEE Std 1076-1993AS VHDL
1996~AIEEENqX{PWA[J
VHDLq]py
C
4
National Chung Cheng University
Wireless Access Technology Lab.
VHDL]p[
VHDLy{gAiG
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[c(Architecture)Gq\yz
ExG
5
National Chung Cheng University
Wireless Access Technology Lab.
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iykpUG
Entity W
is
port( T A G AF
T B G AF
E
E
E
E
E
E
T N G A
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E
)F
End WF
6
National Chung Cheng University
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Wireless Access Technology Lab.
q]p
ExG
ENTITY DFF is
PORT(CLK,D: IN STD_LOGIC;
Q: OUT STD_LOGIC );
END DFF;
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OutG}NeH~
InoutGieV
BufferGw
PortH
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Out
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7
National Chung Cheng University
Wireless Access Technology Lab.
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Architecture [cW of W
is
a[cib
Begin
a[cyz{b
End [cWF
8
National Chung Cheng University