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See MIPS® Run Second Edition

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See MIPS® Run Second Edition Dominic Sweetman AMSTERDAM • BOSTON • HEIDELBERG • LONDON SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO NEW YORK • OXFORD • PARIS • SAN DIEGO Morgan Kaufmann Publishers is an imprint of Elsevier

Publisher: Denise E. M. Penrose Publishing Services Manager: George Morrison Senior Project Manager: Brandy Lilly Editorial Assistant: Kimberlee Honjo Cover Design: Alisa Andreola and Hannus Design Composition: diacriTech Technical Illustration: diacriTech Copyeditor: Denise Moore Proofreader: Katherine Antonsen Indexer: Interior Printer: The Maple-Vail Book Manufacturing Group, Inc. Cover Printer: Phoenix Color Steve Rath Morgan Kaufmann Publishers is an imprint of Elsevier. 500 Sansome Street, Suite 400, San Francisco, CA 94111 This book is printed on acid-free paper. © 2007 by Elsevier Inc. All rights reserved. MIPS, MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS16, MIPS16e, MIPS-3D, MIPS32, MIPS64, 4K, 4KE, 4KEc, 4KSc, 4KSd, M4K, 5K, 20Kc, 24K, 24KE, 24Kf, 25Kf, 34K, R3000, R4000, R5000, R10000, CorExtend, MDMX, PDtrace and SmartMIPS are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries, and used herein under license from MIPS Technologies, Inc. MIPS, MIPS16, MIPS32, MIPS64, MIPS-3D and SmartMIPS, among others, are registered in the U.S. Patent and Trademark Ofﬁce. Linux® is the registered trademark of Linus Torvalds in the U.S. and other countries. Designations used by companies to distinguish their products are often claimed as trademarks or registered trade- marks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means—electronic, mechanical, photocopying, scanning, or otherwise—without prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (+44) 1865 843830, fax: (+44) 1865 853333, E-mail: permissions@elsevier.com. You may also com- plete your request on-line via the Elsevier homepage (http://elsevier.com), by selecting “Support & Contact” then “Copyright and Permission” and then “Obtaining Permissions.” Library of Congress Cataloging-in-Publication Data Application Submitted ISBN 13: 978-0-12-088421-6 ISBN 10: 0-12-088421-6 For information on all Morgan Kaufmann publications, visit our Web site at www.mkp.com or www.books.elsevier.com Printed in the United States of America 06 07 08 09 10 5 4 3 2 1

Foreword The MIPS architecture was born in the early 1980s from the work done by John Hennessy and his students at Stanford University. They were exploring the architectural concept of RISC (Reduced Instruction Set Computing), which theorized that relatively simple instructions, combined with excellent compilers and hardware that used pipelining to execute the instructions, could produce a faster processor with less die area. The concept was so successful that MIPS Computer Systems was formed in 1984 to commercialize the MIPS architecture. Over the course of the next 14 years, the MIPS architecture evolved in a number of ways and its implementations were used very successfully in work- station and server systems. Over that time, the architecture and its implementa- tions were enhanced to support 64-bit addressing and operations, support for complex memory-protected operating systems such as UNIX, and very high performance ﬂoating point. Also in that period, MIPS Computer Systems was acquired by Silicon Graphics and MIPS processors became the standard for Silicon Graphics computer systems. With 64-bit processors, high-performance ﬂoating point, and the Silicon Graphics heritage, MIPS processors became the solution of choice in high-volume gaming consoles. In 1998, MIPS Technologies emerged from Silicon Graphics as a stand- alone company focused entirely on intellectual property for embedded markets. As a result, the pace of architecture development has increased to address the unique needs of these markets: high-performance computation, code compres- sion, geometry processing for graphics, security, signal processing, and multi- threading. Each architecture development has been matched by processor core implementations of the architecture, making MIPS-based processors the standard for high-performance, low-power applications. The MIPS legacy in complex systems such as workstations and servers directly beneﬁts today’s embedded systems, which have, themselves, become very complex. A typical embedded system is composed of multiple process- ing elements, high-performance memory, and one or more operating systems. v

vi Foreword When compared with other embedded architectures, which are just now learning what is required to build a complex system, the MIPS architecture provides a proven base on which to implement such systems. In many ways, the ﬁrst edition of See MIPS Run was a ground-breaking book on the MIPS architecture and its implementations. While other books cov- ered similar material, See MIPS Run focused on what the programmer needed to understand of the architecture and the software environment in order to effectively program a MIPS chip. Increasing complexity of embedded systems has been matched by enhance- ments to the MIPS architecture to address the needs of such systems. The second edition of this book is required reading for any current developer of MIPS-based embedded systems. It adds signiﬁcant new material, including the architectural standardization of the MIPS32 and MIPS64 architectures, brand new application-speciﬁc extensions such as multithreading, and a very nice treatment of the implementation of the popular Linux operating system on the MIPS architecture. Short of the MIPS architecture speciﬁcations, the second edition of See MIPS Run is the most current description of the state of the art of the architecture and is, bar none, the most readable. I hope that you will ﬁnd this as worthwhile and as entertaining to read as I did. Michael Uhler, Chief Technology Ofﬁcer, MIPS Technologies, Inc. Mountain View, CA May 2006

Contents Foreword Preface Style and Limits Conventions Acknowledgments Chapter 1 RISCs and MIPS Architectures 1.1 Pipelines 1.1.1 What Makes a Pipeline Inefﬁcient? 1.1.2 The Pipeline and Caching 1.2 The MIPS Five-Stage Pipeline 1.3 RISC and CISC 1.4 Great MIPS Chips of the Past and Present R2000 to R3000 Processors The R6000 Processor: A Diversion The First CPU Cores The R4000 Processor: A Revolution The Rise and Fall of the ACE Consortium SGI Acquires MIPS 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 QED: Fast MIPS Processors for Embedded Systems 1.4.8 The R10000 Processor and its Successors 1.4.9 MIPS Processors in Consumer Electronics 1.4.10 MIPS in Network Routers and Laser Printers 1.4.11 MIPS Processors in Modern Times 1.4.12 The Rebirth of MIPS Technologies 1.4.13 The Present Day 1.5 MIPS Compared with CISC Architectures 1.5.1 1.5.2 1.5.3 1.5.4 Constraints on MIPS Instructions Addressing and Memory Accesses Features You Won’t Find Programmer-Visible Pipeline Effects v xv xviii xviii xix 1 2 3 4 5 7 8 8 9 11 12 12 13 13 14 15 15 17 20 21 23 23 24 25 27 vii

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