tms320f28377d数据用户手册.pdf

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1 器件概述

1.1 特性

1.2 应用

1.3 说明

1.4 功能框图

内容

2 修订历史记录

3 Device Comparison

4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.2 Signal Descriptions

4.3 Pins With Internal Pullup and Pulldown

4.4 Connections for Unused Pins

4.5 Pin Multiplexing

4.5.1 GPIO Muxed Pins

4.5.2 Input X-BAR

4.5.3 Output X-BAR

4.5.4 USB Pin Muxing

4.5.5 High-Speed SPI Pin Muxing

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Electrical Characteristics

5.5 Power Consumption Summary

5.5.1 Operational Current Consumption Graphs

5.5.2 Reducing Current Consumption

5.6 Thermal Resistance Characteristics

5.6.1 ZWT Package

5.6.2 PTP Package

5.6.3 PZP Package

5.7 System

5.7.1 Power Sequencing

5.7.2 Reset Timing

5.7.2.1 Reset Sources

5.7.2.2 Reset Electrical Data and Timing

5.7.3 Clock Specifications

5.7.3.1 Clock Sources

5.7.3.2 Clock Frequencies, Requirements, and Characteristics

5.7.3.3 Input Clocks and PLLs

5.7.3.4 Crystal Oscillator

5.7.3.5 Internal Oscillators

5.7.4 Flash Parameters

5.7.5 Emulation/JTAG

5.7.6 GPIO Electrical Data and Timing

5.7.6.1 GPIO - Output Timing

5.7.6.2 GPIO - Input Timing

5.7.6.3 Sampling Window Width for Input Signals

5.7.7 Interrupts

5.7.7.1 External Interrupt (XINT) Electrical Data and Timing

5.7.8 Low-Power Modes

5.7.8.1 Clock-Gating Low-Power Modes

5.7.8.2 Power-Gating Low-Power Modes

5.7.8.3 Low-Power Mode Wakeup Timing

5.7.9 External Memory Interface (EMIF)

5.7.9.1 Asynchronous Memory Support

5.7.9.2 Synchronous DRAM Support

5.7.9.3 EMIF Electrical Data and Timing

5.8 Analog Peripherals

5.8.1 Analog-to-Digital Converter (ADC)

5.8.1.1 ADC Electrical Data and Timing

5.8.1.2 Temperature Sensor Electrical Data and Timing

5.8.2 Comparator Subsystem (CMPSS)

5.8.2.1 CMPSS Electrical Data and Timing

5.8.3 Buffered Digital-to-Analog Converter (DAC)

5.8.3.1 Buffered DAC Electrical Data and Timing

5.9 Control Peripherals

5.9.1 Enhanced Capture (eCAP)

5.9.1.1 eCAP Electrical Data and Timing

5.9.2 Enhanced Pulse Width Modulator (ePWM)

5.9.2.1 Control Peripherals Synchronization

5.9.2.2 ePWM Electrical Data and Timing

5.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing

5.9.3 Enhanced Quadrature Encoder Pulse (eQEP)

5.9.3.1 eQEP Electrical Data and Timing

5.9.4 High-Resolution Pulse Width Modulator (HRPWM)

5.9.4.1 HRPWM Electrical Data and Timing

5.9.5 Sigma-Delta Filter Module (SDFM)

5.9.5.1 SDFM Electrical Data and Timing

5.10 Communications Peripherals

5.10.1 Controller Area Network (CAN)

5.10.2 Inter-Integrated Circuit (I2C)

5.10.2.1 I2C Electrical Data and Timing

5.10.3 Multichannel Buffered Serial Port (McBSP)

5.10.3.1 McBSP Electrical Data and Timing

5.10.4 Serial Communications Interface (SCI)

5.10.5 Serial Peripheral Interface (SPI)

5.10.5.1 SPI Electrical Data and Timing

5.10.6 Universal Serial Bus (USB) Controller

5.10.6.1 USB Electrical Data and Timing

5.10.7 Universal Parallel Port (uPP)

5.10.7.1 uPP Electrical Data and Timing

6 Detailed Description

6.1 Overview

6.2 Functional Block Diagram

6.3 Memory

6.3.1 C28x Memory Map

6.3.2 Flash Memory Map

6.3.3 EMIF Chip Select Memory Map

6.3.4 Peripheral Registers Memory Map

6.3.5 Memory Types

6.3.5.1 Dedicated RAM (Mx and Dx RAM)

6.3.5.2 Local Shared RAM (LSx RAM)

6.3.5.3 Global Shared RAM (GSx RAM)

6.3.5.4 CPU Message RAM (CPU MSGRAM)

6.3.5.5 CLA Message RAM (CLA MSGRAM)

6.4 Identification

6.5 Bus Architecture – Peripheral Connectivity

6.6 C28x Processor

6.6.1 Floating-Point Unit

6.6.2 Trigonometric Math Unit

6.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)

6.7 Control Law Accelerator

6.8 Direct Memory Access

6.9 Interprocessor Communication Module

6.10 Boot ROM and Peripheral Booting

6.10.1 EMU Boot or Emulation Boot

6.10.2 WAIT Boot Mode

6.10.3 Get Mode

6.10.4 Peripheral Pins Used by Bootloaders

6.11 Dual Code Security Module

6.12 Timers

6.13 Non-Maskable Interrupt With Watchdog Timer (NMIWD)

6.14 Watchdog

7 Applications, Implementation, and Layout

7.1 Development Tools

7.1.1 F28377D Delfino Experimenter Kit

7.1.2 F28377D Delfino controlCARD

7.2 Software Tools

7.2.1 controlSUITE

7.2.2 Code Composer Studio (CCS) Integrated Development Environment (IDE)

7.2.3 Pin Mux Utility for ARM and F2837xD Microcontrollers

7.2.4 F021 Flash Application Programming Interface (API)

7.3 Training

7.3.1 F2837xD Workshop

8 器件和文档支持

8.1 器件支持

8.1.1 开发支持

8.1.2 器件和开发支持工具命名规则

8.2 文档支持

8.2.1 相关文档

8.2.2 接收文档更新通知

8.3 相关链接

8.4 社区资源

8.5 商标

8.6 静电放电警告

8.7 Glossary

9 机械封装和可订购信息

9.1 封装信息

Important Notice

TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 TMS320F2837xD 双双核核 Delfino™ 微微控控制制器器 1 器器件件概概述述 – 两个多通道缓冲串行端口 (McBSP) – 四个串行通信接口 (SCI/UART)（引脚可引导） – 两个 I2C 接口（引脚可引导） • 模拟子系统 – 四个模数转换器 (ADC) • • 16 位模式 – 每个转换器的吞吐量为 1.1MSPS（系统吞吐量高达 4.4MSPS） – 差分输入 – 多达 12 个外部通道 12 位模式 – 每个转换器的吞吐量为 3.5MSPS（系统吞吐量高达 14MSPS） – 单端输入 – 多达 24 个外部通道 • 每个 ADC 上有单个采样与保持 (S/H) 电路 • ADC 转换的硬件集成后置处理 – 饱和偏移校准 – 定点计算误差 – 具有中断功能的高、低和过零比较 – 触发至采样延迟捕捉 – 八个具有 12 位数模转换器 (DAC) 参考的窗口化比较器 – 3 个 12 位缓冲 DAC 输出 • 增强型控制外设 – 24 条具有增强功能的脉宽调制器 (PWM) 通道 – 16 条高分辨率脉宽调制器 (HRPWM) 通道 • 8 个 PWM 模块的 A 和 B 通道均可实现高分辨率 • 死区支持（对于标准和高分辨率均支持） – 6 个增强型捕捉 (eCAP) 模块 – 3 个增强型正交编码器脉冲 (eQEP)模块 – 八条 Δ-Σ 滤波器模块 (SDFM) 输入通道，每条通道 2 个并联滤波器 • 标准 SDFM 数据滤波 • 用于快速响应超范围情况的比较器滤波器 1 1.1 特特性性 • 双核架构 – 两个 TMS320C28x 32 位 CPU – 200MHz – IEEE-754 单精度浮点单元 (FPU) – 三角法数学单元 (TMU) – Viterbi / 复杂数学单元 (VCU-II) • 两个可编程控制律加速器 (CLA) – 200MHz – IEEE 754 单精度浮点指令 – 独立于主 CPU 之外执行代码 • 片上存储器 – 512KB (256KW) 或 1MB (512KW) 闪存（ECC 保护） – 172KB (86KW) 或 204KB (102KW) RAM（ECC 保护或奇偶校验保护） – 支持第三方开发的双区安全 • 时钟和系统控制 – 两个内部零引脚 10MHz 振荡器 – 片上晶体振荡器 – 窗口化看门狗定时器模块 – 丢失时钟检测电路 • 1.2V 内核，3.3V I/O 设计 • 系统外设 – 两个支持 ASRAM 和 SDRAM 的外部存储器接口 (EMIF) – 双 6 通道直接存储器存取 (DMA) – 多达 169 个支持输入滤波的独立可编程、复用通用输入/输出 (GPIO) 引脚 – 外设中断控制器 (ePIE) – 多个支持外部唤醒的低功耗模式 (LPM) • 通信外设 – USB 2.0 (MAC + PHY) – 支持 12 引脚 3.3V 兼容通用并行端口 (uPP) 接口 – 两个控制器局域网 (CAN) 模块（引脚可引导） – 三个高速（最高 50MHz）SPI 端口（引脚可引导） 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. English Data Sheet: SPRS880 ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &Community

TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 www.ti.com.cn • 封装选项： ZWT] – 无铅，绿色环保封装 – 337 焊球全新细间距球栅阵列 (nFBGA) [后缀 – 176 引脚 PowerPAD™ 散热增强型半高四方扁平 (HLQFP) [PTP后缀] – 100 引脚 PowerPAD 耐热增强型薄型四方扁平封装 (HTQFP) [PZP 后缀] • 温度选项： – T：-40ºC 至 105ºC（结温） – S：–40ºC 到 125ºC（结温） – Q：–40ºC 到 125ºC（自然通风）（针对汽车应用的 Q100 认证） 1.2 应应用用 • 工业驱动产品 • 太阳能微型逆变器和转换器 • 雷达 • 数字电源 1.3 说说明明 • 智能计量 • 汽车运输 • 电力线通信本示例中使用的 Delfino™ TMS320F2837xD 是一款针对工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送和电力线通信等高级闭环控制应用设计的功能强大的 32 位浮点微控制器单元 (MCU)。数字电源和工业驱动器的完整开发包作为 powerSUITE 和 DesignDRIVE 方案的一部分提供。而 Delfino 产品系列并不是 TMS320C2000™ 产品组合的新成员，F2837xD 支持新型双核 C28x 架构，显著提升了系统性能；同时集成有模拟和控制外设，允许设计人员整合控制架构，消除了在高端系统中使用多处理器的需求。双实时控制子系统基于 TI 的 32 位 C28x 浮点 CPU，每个内核中可提供 200MHz 的信号处理性能。 C28x CPU 的性能通过新型 TMU 加速器和 VCU 加速器得到了进一步提升，TMU 加速器可快速执行包含变换和转矩环路计算中常见的三角运算的算法；VCU 加速器可缩短编码应用中常见的复杂数学运算的时间。 F2837xD 微控制器系列采用两个 CLA 实时控制协处理器。 CLA 是一款独立的 32 位浮点处理器，运行速度与主 CPU 相同。它会对外设触发器作出响应，并与主 C28x CPU 同时执行代码。这种并行处理功能可有效加倍实时控制系统的计算性能。通过利用 CLA 执行时间关键型功能，主 C28x CPU 可以得到释放，以便用于执行通信和诊断等其他任务。双 C28x+CLA 架构可在各种系统任务之间实现智能分区。例如，一个 C28x+CLA 内核可用于跟踪速度和位置，而另一个 C28x+CLA 内核则可用于控制转矩和电流环路。 TMS320F2837xD 支持高达 1MB (512KW) 的板载闪存（含纠错码 (ECC)）以及高达 204KB (102KW) 的 SRAM。每个 CPU 上还提供两个 128 位安全区，以实现代码保护。 F2837xD MCU 上还集成了性能模拟和控制外设，进一步实现系统整合。四个独立的 16 位 ADC 可准确、高效地管理多个模拟信号，从而最终提高系统吞吐量。新型 Σ-Δ 滤波器模块 (SDFM) 与 Σ-Δ 调制器配合使用可实现隔离分流测量。包含窗口化比较器的比较器子系统 (CMPSS) 可在超过或未满足电流限制条件的情况下保护功率级。其他模拟和控制外设包括 DAC、PWM、eCAPs、eQEP 以及其他外设。 EMIF、CAN 模块（符合 ISO11898-1/CAN 2.0B）等外设以及新型 uPP 接口扩展了 F2837xD 的连接功能。 uPP 接口是 C2000 MCU 的新功能，支持利用相似的 uPP 接口与 FPGA 或其他处理器实现高速并行连接。最后，具有 MAC 和 PHY 的 USB 2.0 端口使用户能够轻松地将通用串行总线 (USB) 连接功能添加到其应用中。产产品品型型号号 TMS320F28377DZWT TMS320F28376DZWT TMS320F28375DZWT TMS320F28374DZWT TMS320F28377DPTP 器器件件信信息息(1) 封封装装 nFBGA (337) nFBGA (337) nFBGA (337) nFBGA (337) HLQFP (176) 封封装装尺尺寸寸 16.0mm x 16.0mm 16.0mm x 16.0mm 16.0mm x 16.0mm 16.0mm x 16.0mm 24.0mm × 24.0mm (1) 有关这些器件的更多信息，请参见节 9，机械、封装和可订购信息。 2 器件概述版权 © 2013–2015, Texas Instruments Incorporated

www.ti.com.cn TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 产产品品型型号号 TMS320F28376DPTP TMS320F28375DPTP TMS320F28374DPTP TMS320F28375DPZP 器器件件信信息息(1) (continued) 封封装装 HLQFP (176) HLQFP (176) HLQFP (176) HTQFP (100) 封封装装尺尺寸寸 24.0mm x 24.0mm 24.0mm x 24.0mm 24.0mm x 24.0mm 14.0mm x 14.0mm 版权 © 2013–2015, Texas Instruments Incorporated 器件概述 3

TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 www.ti.com.cn 1.4 功功能能框框图图图 1-1 显示了 CPU 系统及相关外设。图图 1-1. 功功能能方方框框图图 4 器件概述版权 © 2013–2015, Texas Instruments Incorporated 16-/12-bitADCx4AnalogMuxADCResultRegsPeripheralFrame1Global Shared16x4Kx16GS0-GS15 RAMsCPU1toCPU21Kx16MSGRAMGPIOMUX,InputX-BAR,OutputX-BARCPU1.M0RAM1Kx16CPU1.M1 RAM 1Kx16CPU2.M0RAM1Kx16CPU2.M1 RAM 1Kx16PSWDPSWDSecureMemoriesshowninRedMEMCPU2CPU2toCPU11Kx16MSGRAMMEMCPU1CPU1BusesCPU2BusesA5:0B5:0C5:2ADCIN14ADCIN15D5:0ComparatorSubSystem(CMPSS)DACx3ConfigCPU1.CLA1BusCPU2.CLA1BusC28CPU-1FPUVCU-IITMUCPUTimer0CPUTimer1CPUTimer2ePIE(upto192interrupts)WDTimerNMI-WDTC28CPU-2FPUVCU-IITMUCPU Timer 0CPU Timer 1CPU Timer 2ePIE(upto192interrupts)WDTimerNMI-WDTCPU1.CLA1 Data ROM(4Kx16)CPU1.CLA1toCPU1128x16MSGRAMCPU1toCPU1.CLA1128x16MSGRAMCPU1.D0RAM2Kx16CPU1.D1RAM 2Kx16Boot-ROM32Kx16NonSecureSecure-ROM32Kx16SecureCPU1LocalShared6x2Kx16LS0-LS5RAMsCPU2 toCPU2.CLA1128x16MSGRAMCPU2.CLA1 toCPU2128x16MSGRAMCPU2.D0 RAM 2Kx16CPU2.D1 RAM 2Kx16CPU2.CLA1DataROM(4Kx16)Boot-ROM32Kx16NonSecureSecure-ROM32Kx16SecureCPU2LocalSharedLS0-LS5RAMsCPU1.CLA1CPU1.DMACPU2.DMACPU2.CLA1Data BusBridgeePWM-1/../12eCAP-1/../6eQEP-1/2/3SDFM-1/2EXTSYNCINEXTSYNCOUTTZ1-TZ6ECAPxEQEPxAEQEPxBEPWMxAEPWMxBEQEPxIEQEPxSSDx_DySDx_CyABCDJTAGAUXCLKINExternal Crystal orOscillatorWatchdog 1/2Main PLLAux PLLINTOSC1INTOSC2Low-PowerMode ControlGPIO MuxTRSTTCKTDITMSTDO6x2Kx16DualCodeSecurityModule+EmulationCodeSecurityLogic(ECSL)DualCodeSecurityModule+EmulationCodeSecurityLogic(ECSL)InterprocessorCommunication(IPC)ModulePUMPOTP/FlashWrapperFLASH256K x 16SecureUserConfigurableDCSMOTP1K x 16OTP/FlashWrapperFLASH256K x 16SecureUserConfigurableDCSMOTP1K x 16SCI-A/B/C/D(16LFIFO)I2C-A/B(16LFIFO)Data Bus BridgeSCITXDxSCIRXDxSDAxSCLxCAN-A/B(32-MBOX)Data BusBridgeCANRXxCANTXxGPIOData BusBridgeGPIOnData BusBridgeUSBCtrl /PHYUSBDPUSBDMUSBCtrl /PHYEMIF1Data BusBridgeEM1DxEM1AxEM1CTLxEMIF2Data BusBridgeEM2DxEM2AxEM2CTLxPeripheralFrame2SPI-A/B/C(16LFIFO)SPISIMOxSPISOMIxSPICLKxSPISTExMcBSP-A/BMDXxMRXxMCLKXxMCLKRxMFSXxMFSRxuPPRAMUPPAD[7:0]UPPAENUPPASTUPPAWTUPPACLKHRPWM-1/../8(CPU1 only)

www.ti.com.cn TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 1 器器件件概概述述.................................................... 1 1.1 特性................................................... 1 1.2 应用................................................... 2 1.3 说明................................................... 2 1.4 功能框图 ............................................. 4 2 修修订订历历史史记记录录............................................... 6 3 Device Comparison ................................... 10 Terminal Configuration and Functions ............ 12 4 Pin Diagrams........................................ 12 4.1 Signal Descriptions.................................. 18 4.2 Pins With Internal Pullup and Pulldown............. 40 4.3 Connections for Unused Pins....................... 41 4.4 Pin Multiplexing...................................... 42 4.5 Specifications........................................... 49 Absolute Maximum Ratings ........................ 49 5.1 ESD Ratings ........................................ 49 5.2 Recommended Operating Conditions............... 50 5.3 Electrical Characteristics............................ 50 5.4 Power Consumption Summary...................... 51 5.5 Thermal Resistance Characteristics ................ 54 5.6 System .............................................. 56 5.7 Analog Peripherals .................................. 91 5.8 Control Peripherals ................................ 117 5.9 5.10 Communications Peripherals ...................... 134 6 Detailed Description.................................. 174 Overview ........................................... 174 Functional Block Diagram ......................... 174 6.1 6.2 5 内内容容 6.3 Memory ............................................ 176 Identification........................................ 183 6.4 Bus Architecture – Peripheral Connectivity........ 184 6.5 C28x Processor.................................... 185 6.6 Control Law Accelerator ........................... 187 6.7 Direct Memory Access............................. 188 6.8 Interprocessor Communication Module............ 190 6.9 6.10 Boot ROM and Peripheral Booting................. 191 6.11 Dual Code Security Module ....................... 194 6.12 Timers.............................................. 194 6.13 Non-Maskable Interrupt With Watchdog Timer (NMIWD) ........................................... 194 6.14 Watchdog .......................................... 195 7 Applications, Implementation, and Layout ...... 196 Development Tools ................................ 196 Software Tools..................................... 196 Training ............................................ 196 8 器器件件和和文文档档支支持持......................................... 197 8.1 器件支持 ........................................... 197 8.2 文档支持 ........................................... 199 8.3 相关链接 ........................................... 200 8.4 社区资源 ........................................... 200 8.5 商标 ................................................ 200 8.6 静电放电警告....................................... 200 Glossary............................................ 200 8.7 9 机机械械封封装装和和可可订订购购信信息息................................. 201 9.1 封装信息 ........................................... 201 7.1 7.2 7.3 版权 © 2013–2015, Texas Instruments Incorporated 内容 5

TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 www.ti.com.cn 2 修修订订历历史史记记录录注：之前版本的页码可能与当前版本有所不同。 Changes from June 19, 2015 to September 25, 2015 (from D Revision (June 2015) to E Revision) ................................................................................................................................... 1 Page • 全全局局：：TMS320F2837xD 器件现已成为完全合格的生产器件 (TMS)。 ........................................................ 1 • 全全局局：：文档结构已经过重新编排。 • 全全局局：：将 UPP-STRT 改为 UPP-START。 ....................................................................................... 1 • 节 1.1 （特性）：更新了章节。 .................................................................................................... 1 • 节 1.2 （应用）：更新了章节。 .................................................................................................... 2 • 节 1.3 （说明）：更新了章节。 .................................................................................................... 2 • 图 1-1 （功能框图）：更新了图片。 .............................................................................................. 4 Table 3-1 (Device Comparison): Updated table and footnotes. .............................................................. 10 • • Table 4-1 (Signal Descriptions): Updated DESCRIPTION of ADCSOCAO, ADCSOCBO, EPWM[1:8]A, EPWM[1:8]B, GPIO72, GPIO84, XRS, TRST, VDDIO, and ERRORSTS. .................................................... 18 Table 4-1: Removed "The maximum toggling frequency of the GPIOs is 50 MHz" footnote. ............................ 18 • Table 4-2 (Pins With Internal Pullup and Pulldown): Removed "POWER UP" column and associated footnote. ..... 40 • Table 4-2: APPLICATION SOFTWARE column: Changed "Application-defined" to "Pullup enable is application- • defined". ............................................................................................................................. 40 • Section 4.4 (Connections for Unused Pins): Added section. ................................................................. 41 • Section 4.5.3 (Output X-BAR): Removed "Output X-BAR Mux Configuration Table" (this was Table 4-5 in SPRS880D). ......................................................................................................................... 47 Figure 4-8 (Output X-BAR): Changed "ADCSOCA" to "ADCSOCAO". Changed "ADCSOCB" to "ADCSOCBO". ... 47 • • Section 5.1 (Absolute Maximum Ratings): Moved "Supply ramp rate" to Table 5-3. ...................................... 49 • Section 5.3 (Recommended Operating Conditions): Updated "VDDIO, VDD3VFL, VDDOSC ..." footnote. .................... 50 • Section 5.4 (Electrical Characteristics): Updated section. ..................................................................... 50 • Section 5.4: Added footnote about MAX input leakage. ....................................................................... 50 Table 5-1 (Device Current Consumption at 200-MHz SYSCLK): Updated table. .......................................... 51 • • Section 5.5.2 (Reducing Current Consumption): Updated "Any one of the four low-power modes ..." method. ...... 53 • Table 5-2 (Current on VDD Supply by Various Peripherals (at 200 MHz)): Changed table title from "Typical Current Consumption by Various Peripherals (at 200 MHz)" to "Current on VDD Supply by Various Peripherals (at 200 MHz)". ....................................................................................................................... 53 Table 5-2: Added footnote reference to CMPSS and DAC. .................................................................. 53 • Table 5-2: Updated "This number represents the current drawn by ..." footnote. ......................................... 53 • Table 5-2: Changed "USB" to "USB and AUXPLL at 60 MHz". .............................................................. 53 • • Section 5.7.1 (Power Sequencing): Updated "An external power supply must be used to supply ..." paragraph. .... 56 Table 5-3 (Supply Ramp Rate): Added table. .................................................................................. 56 • • Section 5.7.2 (Reset Timing): Updated section. ................................................................................ 56 Figure 5-3 (Reset Circuit): Added figure. ........................................................................................ 56 • • Section 5.7.2.1 (Reset Sources): Added section. .............................................................................. 57 Figure 5-4 (Power-on Reset): Updated "After reset ..." footnote. ............................................................ 58 • Figure 5-5 (Warm Reset): Changed "Boot-ROM Execution Starts" to "Boot-ROM execution starts (initiated by • any reset source)". ................................................................................................................. 58 Figure 5-5: Updated footnote. ..................................................................................................... 58 • • 表 5-6 (Possible Reference Clock Sources): Changed GPIO_AUXCLKIN to AUXCLKIN. ............................... 59 • 表 5-6: XTAL: Updated COMMENTS. ........................................................................................... 59 • 表 5-6: Removed "For power savings ..." footnote. ............................................................................ 59 • 图 5-6 (Device Clocking): Updated figure. ...................................................................................... 60 • 表 5-7 (Input Clock Frequency): Changed f(OSC) to f(XTAL). ..................................................................... 61 • 表 5-7: Changed f(OCI) to f(X1). ..................................................................................................... 61 • 表 5-7: Changed f(XCI) to f(AUXI). .................................................................................................... 61 • 表 5-9 (X1 Timing Requirements): Changed tf(OCI) to tf(X1). .................................................................... 61 • 表 5-9: Changed tr(OCI) to tr(X1). .................................................................................................... 61 • 表 5-9: Changed tw(OCL) to tw(X1L). ................................................................................................. 61 • 表 5-9: Changed tw(OCH) to tw(X1H). ................................................................................................. 61 • 表 5-9: Changed tc(OCI) to tc(X1). .................................................................................................... 61 • 表 5-10 (AUXCLKIN Timing Requirements): Changed tf(XCI) to tf(AUXI). ...................................................... 61 • 表 5-10: Changed tr(XCI) to tr(AUXI). ................................................................................................. 61 6 修订历史记录版权 © 2013–2015, Texas Instruments Incorporated

www.ti.com.cn TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 • 表 5-10: Changed tw(XCL) to tw(AUXL). .............................................................................................. 61 • 表 5-10: Changed tw(XCH) to tw(AUXH). .............................................................................................. 61 • 表 5-11 (PLL Lock Times): Updated footnote. .................................................................................. 61 • 表 5-12 (Internal Clock Frequencies): Changed "f(AUX)" to "f(AUXPLL)". Added MIN and MAX values. Removed NOM value. .......................................................................................................................... 62 • 表 5-12: Changed "f(INT)" to "f(INTOSC)". Updated description. .................................................................. 62 • 表 5-12: Added f(OSCCLK). ........................................................................................................... 62 • 表 5-13 (Output Clock Frequency): f(XCO): Removed MIN value. ............................................................. 62 • 节 5.7.3.3 (Input Clocks and PLLs): Added "(also referred to as XTAL)" to paragraph. .................................. 63 • 表 5-16 (Crystal Equivalent Series Resistance (ESR) Requirements): Added footnote about ESR. .................... 64 • 表 5-17 (Crystal Oscillator Electrical Characteristics): Added Crystal drive level (DL). ................................... 64 • 节 5.7.3.5 (Internal Oscillators): Added paragraph about INTOSC1 and INTOSC2. ...................................... 65 Table 5-18 (Internal Oscillator Electrical Characteristics): Updated table. .................................................. 65 • • 节 5.7.4 (Flash Parameters): Added paragraphs. .............................................................................. 66 • 表 5-19 (Minimum Required Flash Wait States at Different Frequencies): Added footnote about using INTOSC as PLL clock source. ............................................................................................................... 66 • 表 5-21 (Flash/OTP Endurance): Removed NOTP. ............................................................................. 66 • 节 5.7.6 (GPIO Electrical Data and Timing): Updated section. ............................................................... 69 Table 5-23 (General-Purpose Output Switching Characteristics): Added footnote. ....................................... 69 • Table 5-25 (External Interrupt Timing Requirements): Removed footnote about ADCSOC functionality. .............. 73 • Figure 5-14 (External Interrupt Timing): Updated signal names. ............................................................. 73 • • 表 5-27 (Effect of Clock-Gating Low-Power Modes on the Device): Changed "WD1CLK" to "CPU1.WDCLK". Updated "CPU2 IDLE" and "CPU2 STANDBY" columns. ..................................................................... 74 • 表 5-27: Changed "WD2CLK" to "CPU2.WDCLK". Updated "CPU1 IDLE" and "CPU1 STANDBY" columns. ......... 74 • 表 5-27: Updated HALT column of PLL. ......................................................................................... 74 • 表 5-27: Changed "X1,X2 OSC" to "X1/X2 Crystal Oscillator". ............................................................... 74 • 表 5-29 (IDLE Mode Timing Requirements): tw(WAKE) with input qualifier: Changed MIN value from "1tc(SYSCLK) + tw(IQSW)" to "2tc(SYSCLK) + tw(IQSW)". .................................................................................................. 75 • 表 5-30 (IDLE Mode Switching Characteristics): Changed "Wakeup from SARAM" to "Wakeup from RAM". ......... 75 • 表 5-30: Added footnote about FPAC1[PSLEEP] setting. ..................................................................... 75 • 表 5-31 (STANDBY Mode Timing Requirements): Changed "Without input qualification" to "QUALSTDBY = 0 | 2tc(OSCCLK)". .......................................................................................................................... 76 • 表 5-31: Changed "With input qualification" to "QUALSTDBY > 0 | (2 + QUALSTDBY)tc(OSCCLK)". ...................... 76 • 表 5-32 (STANDBY Mode Switching Characteristics): td(WAKE-STBY): Removed MAX values for "Without input qualifier" condition. ................................................................................................................. 76 • 表 5-32: td(WAKE-STBY): Changed "Wakeup from SARAM" to "Wakeup from RAM". ......................................... 76 • 表 5-32: Added footnote about FPAC1[PSLEEP] setting. ..................................................................... 76 • 图 5-16 (STANDBY Entry and Exit Timing Diagram): Changed "X1/X2 or XCLKIN" to OSCCLK. ...................... 77 • 表 5-33 (HALT Mode Timing Requirements): Added footnote about OSCCLK. ........................................... 78 • 表 5-34 (HALT Mode Switching Characteristics): Changed "Wakeup from SARAM" to "Wakeup from RAM". ........ 78 • 表 5-34: Added footnote. .......................................................................................................... 78 • 图 5-17 (HALT Entry and Exit Timing Diagram): Changed "X1/X2 or XCLKIN" to OSCCLK. ............................ 79 • 表 5-36 (HIBERNATE Mode Switching Characteristics): td(WAKE-HIB): Removed "Wakeup from flash" from parameter description. ............................................................................................................. 80 footnote. ............................................................................................................................. 81 Table 5-37 (EMIF Asynchronous Memory Timing Requirements): Updated MIN value of EMIF clock period. ........ 84 • • 节 5.8 (Analog Peripherals): Updated section. ................................................................................. 91 • 节 5.8.1.1 (ADC Electrical Data and Timing): Added NOTE about ADC inputs. ........................................... 97 Table 5-41 (ADC Operating Conditions (16-Bit Differential Mode)): Updated table. ...................................... 97 • Table 5-42 (ADC Characteristics (16-Bit Differential Mode)): Updated table and footnotes. ............................. 98 • Table 5-43 (ADC Operating Conditions (12-Bit Single-Ended Mode)): Updated table. ................................... 99 • Table 5-44 (ADC Characteristics (12-Bit Single-Ended Mode)): Updated table. ......................................... 100 • Table 5-45 (ADCEXTSOC Timing Requirements): Added table. ........................................................... 101 • • 节 5.8.1.1.1 (ADC Input Models): Updated NOTE about ADC channels having a 50-kΩ pulldown resistor to VSSA.. 101 • 节 5.8.1.1.1: Updated "The user should analyze the ADC input setting ..." paragraph. ................................. 101 • 节 5.8.1.2 (Temperature Sensor Electrical Data and Timing): Added paragraph. ........................................ 107 Table 5-51 (Temperature Sensor Electrical Characteristics): Updated description of Start-up time. .................. 107 • • 节 5.8.2 (Comparator Subsystem (CMPSS)): Updated paragraph. ........................................................ 108 • 图 5-35 (CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)): Updated figure. ..................................... 108 7 • 图 5-18 (HIBERNATE Entry and Exit Timing Diagram): Updated "The BootROM will then begin to execute ..." 版权 © 2013–2015, Texas Instruments Incorporated 修订历史记录

TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D ZHCSC63E –DECEMBER 2013–REVISED SEPTEMBER 2015 www.ti.com.cn • 图 5-36 (CMPSS Connectivity (100-Pin PZP)): Updated figure. ............................................................ 109 • 节 5.8.2.1 (CMPSS Electrical Data and Timing): Added NOTE about CMPSS inputs. .................................. 110 Table 5-52 (Comparator Electrical Characteristics): Updated table. ....................................................... 110 • Figure 5-37 (CMPSS Comparator Input Referred Offset): Added figure. .................................................. 110 • Figure 5-38 (CMPSS Comparator Hysteresis): Added figure. .............................................................. 110 • • Table 5-53 (CMPSS DAC Static Electrical Characteristics): Changed table title from "Reference DAC Static Electrical Characteristics" to "CMPSS DAC Static Electrical Characteristics". ........................................... 111 Table 5-53: Changed "DAC" and "reference DAC" to "CMPSS DAC". .................................................... 111 • Figure 5-39 (CMPSS DAC Static Offset): Added figure. ..................................................................... 111 • Figure 5-40 (CMPSS DAC Static Gain): Added figure. ...................................................................... 112 • Figure 5-41 (CMPSS DAC Static Linearity): Added figure. .................................................................. 112 • • 节 5.8.3.1 (Buffered DAC Electrical Data and Timing): Added NOTE about VDAC pin. ................................ 114 Table 5-54 (Buffered DAC Electrical Characteristics): Changed table title from "Reference DAC Electrical • Characteristics" to "Buffered DAC Electrical Characteristics". .............................................................. 114 Table 5-54: Updated table and footnotes. ..................................................................................... 114 • Figure 5-43 (Buffered DAC Offset): Added figure. ............................................................................ 115 • Figure 5-44 (Buffered DAC Gain): Added figure. ............................................................................. 115 • Figure 5-45 (Buffered DAC Linearity): Added figure. ......................................................................... 116 • • 节 5.9.1 (Enhanced Capture (eCAP)): Updated section. .................................................................... 117 • 图 5-47 (ePWM Submodules and Critical Internal Signal Interconnects): Updated figure and footnotes. ............ 121 • 图 5-48 (ePWM Trip Input Connectivity): Changed figure caption from "ePWM" to "ePWM Trip Input Connectivity". ...................................................................................................................... 122 • 图 5-48: Updated figure. ......................................................................................................... 122 Table 5-58 (ePWM Switching Characteristics): Changed td(PWM)tza to td(TZ-PWM). ........................................... 124 • Figure 5-50 (PWM Hi-Z Characteristics): Changed td(TZ-PWM)HZ to td(TZ-PWM)................................................. 124 • • 节 5.9.2.3 (External ADC Start-of-Conversion Electrical Data and Timing): Added section. ............................ 125 • 节 5.9.3 (Enhanced Quadrature Encoder Pulse (eQEP)): Updated section. .............................................. 126 • 节 5.9.4 (High-Resolution Pulse Width Modulator (HRPWM)): Updated section. ........................................ 129 • 节 5.9.5 (Sigma-Delta Filter Module (SDFM)): Updated SDFM features list. ............................................. 130 • 图 5-53 (SDFM): Updated figure. ............................................................................................... 131 Table 5-64 (SDFM Timing Requirements): Updated tc(SDC)M0, tc(SDC)M1, tw(SDCH)M1, tc(SDD)M2, and tc(SDC)M3. ............. 132 • • 节 5.10.1 (Controller Area Network (CAN)): Updated NOTE about accuracy of the on-chip zero-pin oscillator. .... 134 • 节 5.10.2 (Inter-Integrated Circuit (I2C)): Changed " One 16-word receive FIFO and one 16-word transmit FIFO" to " One 16-byte receive FIFO and one 16-byte transmit FIFO". ........................................................... 135 • 节 5.10.3 (Multichannel Buffered Serial Port (McBSP)): Updated McBSP featues list. .................................. 138 Table 5-67 (McBSP Timing Requirements): Updated footnotes. ........................................................... 140 • • Section 5.10.3.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs with "For all SPI slave modes ..." table footnotes. ............................................................................ 143 Table 5-69 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all SPI slave modes ..." footnote. ................................................................................................... 143 Table 5-71 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all SPI slave modes ..." footnote. ................................................................................................... 144 Table 5-73 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all SPI slave modes ..." footnote. ................................................................................................... 145 Table 5-75 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all SPI slave modes ..." footnote. ................................................................................................... 146 communication" to "Changed "High-speed mode for up to 50-MHz full-duplex communication". ...................... 150 Table 5-79 (SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2): Parameter 6 [td(SIMO-SPCH)M]: Moved MAX value to MIN column. ............................................................................ 156 Table 5-79: Parameter 6 [td(SIMO-SPCL)M]: Moved MAX value to MIN column. .............................................. 156 Table 5-80 (SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3): Parameter 6 [td(SIMO-SPCH)M]: Moved MAX value to MIN column. ............................................................................ 157 Table 5-80: Parameter 6 [td(SIMO-SPCL)M]: Moved MAX value to MIN column. .............................................. 157 Table 5-84 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3): Parameter 8 [tsu(SOMI-SPCL)M]: Changed MIN value from 6 ns to 1 ns. ....................................................... 161 Table 5-84: Parameter 8 [tsu(SOMI-SPCH)M]: Changed MIN value from 6 ns to 1 ns. ........................................ 161 Table 5-84: Parameter 9 [th(SPCL-SOMI)M]: Changed MIN value from 7 ns to 5 ns. ......................................... 161 Table 5-84: Parameter 9 [th(SPCH-SOMI)M]: Changed MIN value from 7 ns to 5 ns. ......................................... 161 Table 5-85 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2): • 节 5.10.5 (Serial Peripheral Interface (SPI)): Changed "High-speed mode for up to 40-MHz full-duplex • • • • • • • • • • • • • 8 修订历史记录版权 © 2013–2015, Texas Instruments Incorporated

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