DAQ M Series User Manual
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Contents
About This Manual
Conventions
Related Documentation
NI-DAQmx for Windows
NI-DAQmx for Linux
NI-DAQmx Base (Linux/Mac OS X )
LabVIEW
LabWindows/CVI
Measurement Studio
ANSI C without NI Application Software
.NET Languages without NI Application Software
Device Documentation and Specifications
Training Courses
Technical Support on the Web
Chapter 1 Getting Started
Installing NI-DAQmx
Installing Other Software
Installing the Hardware
Device Self-Calibration
Device Pinouts
Device Specifications
Device Accessories and Cables
Applying the Signal Label to USB-62xx Screw Terminal Devices
Figure 1-1. Applying the USB-62xx Screw Terminal Signal Label
USB Cable Strain Relief
Figure 1-2. USB Cable Strain Relief on USB-62xx Screw Terminal and USB-62xx Mass Termination Devices
Figure 1-3. USB Cable Strain Relief on USB-62xx BNC Devices
USB Device Panel/Wall Mounting
USB Device Security Cable Slot
Chapter 2 DAQ System Overview
Figure 2-1. Components of a Typical DAQ System
DAQ Hardware
Figure 2-2. General M Series Block Diagram
DAQ-STC2 and DAQ-6202
Calibration Circuitry
Signal Conditioning
Sensors and Transducers
Signal Conditioning Options
SCXI
SCC
5B Series
Cables and Accessories
Custom Cabling
Programming Devices in Software
Chapter 3 Connector and LED Information
I/O Connector Signal Descriptions
Table 3-1. I/O Connector Signals
M Series and E Series Pinout Comparison
Table 3-2. M Series and E Series Device Pinout Comparison
+5 V Power Source
USB Chassis Ground
Figure 3-1. Grounding a USB-62xx Device through the Ground Lug Screw
Figure 3-2. Grounding a USB-62xx Screw Terminal Device through the Chassis Ground Lug
Figure 3-3. Grounding a USB-62xx BNC Device through the CHS GND Screw Terminal
PCI Express Device Disk Drive Power Connector
When to Use the Disk Drive Power Connector
Disk Drive Power Connector Installation
Figure 3-4. Connecting to the Disk Drive Power Connector
USB Device Fuse Replacement
Figure 3-5. USB-62xx Screw Terminal Fuse Locations
Figure 3-6. USB-62xx BNC Fuse Location
Figure 3-7. USB-62xx Mass Termination Fuse Locations
RTSI Connector Pinout
LED Patterns
Table 3-3. LED Patterns
Chapter 4 Analog Input
Figure 4-1. M Series Analog Input Circuitry
Analog Input Range
Table 4-1. M Series Input Range and Nominal Resolution
Analog Input Lowpass Filter
Analog Input Ground-Reference Settings
Figure 4-2. NI-PGIA
Table 4-2. Signals Routed to the NI-PGIA
Configuring AI Ground-Reference Settings in Software
Figure 4-3. Enabling Multimode Scanning in LabVIEW
Multichannel Scanning Considerations
Analog Input Data Acquisition Methods
Analog Input Triggering
Connecting Analog Input Signals
Table 4-3. Analog Input Configuration
Connecting Floating Signal Sources
What Are Floating Signal Sources?
When to Use Differential Connections with Floating Signal Sources
When to Use Non-Referenced Single-Ended (NRSE) Connections with Floating Signal Sources
When to Use Referenced Single-Ended (RSE) Connections with Floating Signal Sources
Using Differential Connections for Floating Signal Sources
Figure 4-4. Differential Connections for Floating Signal Sources without Bias Resistors
Figure 4-5. Differential Connections for Floating Signal Sources with Single Bias Resistor
Figure 4-6. Differential Connections for Floating Signal Sources with Balanced Bias Resistors
Figure 4-7. Differential Connections for AC Coupled Floating Sources with Balanced Bias Resistors
Using Non-Referenced Single-Ended (NRSE) Connections for Floating Signal Sources
Figure 4-8. NRSE Connections for Floating Signal Sources
Using Referenced Single-Ended (RSE) Connections for Floating Signal Sources
Figure 4-9. RSE Connections for Floating Signal Sources
Connecting Ground-Referenced Signal Sources
What Are Ground-Referenced Signal Sources?
When to Use Differential Connections with Ground-Referenced Signal Sources
When to Use Non-Referenced Single-Ended (NRSE) Connections with Ground-Referenced Signal Sources
When to Use Referenced Single-Ended (RSE) Connections with Ground-Referenced Signal Sources
Using Differential Connections for Ground-Referenced Signal Sources
Figure 4-10. Differential Connections for Ground-Referenced Signal Sources
Using Non-Referenced Single-Ended (NRSE) Connections for Ground-Referenced Signal Sources
Figure 4-11. Single-Ended Connections for Ground-Referenced Signal Sources (NRSE Configuration)
Field Wiring Considerations
Analog Input Timing Signals
Figure 4-12. Analog Input Timing Options
Figure 4-13. Interval Sampling
Figure 4-14. Posttriggered Data Acquisition Example
Figure 4-15. Pretriggered Data Acquisition Example
AI Sample Clock Signal
Using an Internal Source
Using an External Source
Routing AI Sample Clock Signal to an Output Terminal
Other Timing Requirements
Figure 4-16. AI Sample Clock and AI Start Trigger
AI Sample Clock Timebase Signal
AI Convert Clock Signal
Using an Internal Source
Using an External Source
Routing AI Convert Clock Signal to an Output Terminal
Using a Delay from Sample Clock to Convert Clock
Figure 4-17. AI Sample Clock and AI Convert Clock
Other Timing Requirements
Figure 4-18. AI Sample Clock Pulses Are Gated Off; AI Sample Clock Too Fast For Convert Clock
Figure 4-19. AI Convert Clock Too Fast For AI Sample Clock; AI Convert Clock Pulses Are Gated Off
Figure 4-20. AI Sample Clock and AI Convert Clock Improperly Matched; Leads to Aperiodic Sampling
Figure 4-21. AI Sample Clock and AI Convert Clock Properly Matched
Figure 4-22. One External Signal Driving Both Clocks Simultaneously
AI Convert Clock Timebase Signal
AI Hold Complete Event Signal
AI Start Trigger Signal
Using a Digital Source
Using an Analog Source
Routing AI Start Trigger to an Output Terminal
AI Reference Trigger Signal
Figure 4-23. Reference Trigger Final Buffer
Using a Digital Source
Using an Analog Source
Routing AI Reference Trigger Signal to an Output Terminal
AI Pause Trigger Signal
Using a Digital Source
Using an Analog Source
Routing AI Pause Trigger Signal to an Output Terminal
Getting Started with AI Applications in Software
Chapter 5 Analog Output
Figure 5-1. M Series Analog Output Circuitry
AO Offset and AO Reference Selection
Minimizing Glitches on the Output Signal
Analog Output Data Generation Methods
Analog Output Triggering
Connecting Analog Output Signals
Figure 5-2. Analog Output Connections
Analog Output Timing Signals
Figure 5-3. Analog Output Timing Options
AO Start Trigger Signal
Using a Digital Source
Using an Analog Source
Routing AO Start Trigger Signal to an Output Terminal
AO Pause Trigger Signal
Figure 5-4. AO Pause Trigger with the Onboard Clock Source
Figure 5-5. AO PauseTrigger with Other Signal Source
Using a Digital Source
Using an Analog Source
Routing AO Pause Trigger Signal to an Output Terminal
AO Sample Clock Signal
Using an Internal Source
Using an External Source
Routing AO Sample Clock Signal to an Output Terminal
Other Timing Requirements
Figure 5-6. AO Sample Clock and AO Start Trigger
AO Sample Clock Timebase Signal
Getting Started with AO Applications in Software
Chapter 6 Digital I/O
Figure 6-1. M Series Digital I/O Circuitry
Static DIO
Digital Waveform Triggering
Figure 6-2. Digital Waveform Triggering
Digital Waveform Acquisition
DI Sample Clock Signal
Using an Internal Source
Using an External Source
Routing DI Sample Clock to an Output Terminal
Digital Waveform Generation
DO Sample Clock Signal
Using an Internal Source
Using an External Source
Routing DO Sample Clock to an Output Terminal
I/O Protection
Programmable Power-Up States
DI Change Detection
Figure 6-3. DI Change Detection
DI Change Detection Applications
Connecting Digital I/O Signals
Figure 6-4. Digital I/O Connections
Getting Started with DIO Applications in Software
Chapter 7 Counters
Figure 7-1. M Series Counters
Counter Input Applications
Counting Edges
Single Point (On-Demand) Edge Counting
Figure 7-2. Single Point (On-Demand) Edge Counting
Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger
Buffered (Sample Clock) Edge Counting
Figure 7-4. Buffered (Sample Clock) Edge Counting
Controlling the Direction of Counting
Pulse-Width Measurement
Single Pulse-Width Measurement
Figure 7-5. Single Pulse-Width Measurement
Buffered Pulse-Width Measurement
Figure 7-6. Buffered Pulse-Width Measurement
Period Measurement
Single Period Measurement
Figure 7-7. Single Period Measurement
Buffered Period Measurement
Figure 7-8. Buffered Period Measurement
Semi-Period Measurement
Single Semi-Period Measurement
Buffered Semi-Period Measurement
Figure 7-9. Buffered Semi-Period Measurement
Frequency Measurement
Figure 7-10. Method 1
Figure 7-11. Method 1b
Figure 7-12. Method 2
Figure 7-13. Method 3
Choosing a Method for Measuring Frequency
Table 7-1. Frequency Measurement Method 1
Table 7-2. Frequency Measurement Method Comparison
Position Measurement
Measurements Using Quadrature Encoders
Figure 7-14. X1 Encoding
Figure 7-15. X2 Encoding
Figure 7-16. X4 Encoding
Figure 7-17. Channel Z Reload with X4 Decoding
Measurements Using Two Pulse Encoders
Figure 7-18. Measurements Using Two Pulse Encoders
Buffered (Sample Clock) Position Measurement
Figure 7-19. Buffered Position Measurement
Two-Signal Edge-Separation Measurement
Single Two-Signal Edge-Separation Measurement
Figure 7-20. Single Two-Signal Edge-Separation Measurement
Buffered Two-Signal Edge-Separation Measurement
Figure 7-21. Buffered Two-Signal Edge-Separation Measurement
Counter Output Applications
Simple Pulse Generation
Single Pulse Generation
Figure 7-22. Single Pulse Generation
Single Pulse Generation with Start Trigger
Figure 7-23. Single Pulse Generation with Start Trigger
Retriggerable Single Pulse Generation
Figure 7-24. Retriggerable Single Pulse Generation
Pulse Train Generation
Continuous Pulse Train Generation
Figure 7-25. Continuous Pulse Train Generation
Finite Pulse Train Generation
Figure 7-26. Finite Pulse Train Timing Diagram
Frequency Generation
Using the Frequency Generator
Figure 7-27. Frequency Generator Block Diagram
Figure 7-28. Frequency Generator Output Waveform
Frequency Division
Pulse Generation for ETS
Figure 7-29. Pulse Generation for ETS
Counter Timing Signals
Counter n Source Signal
Table 7-3. Counter Applications and Counter n Source
Routing a Signal to Counter n Source
Routing Counter n Source to an Output Terminal
Counter n Gate Signal
Routing a Signal to Counter n Gate
Routing Counter n Gate to an Output Terminal
Counter n Aux Signal
Routing a Signal to Counter n Aux
Counter n A, Counter n B, and Counter n Z Signals
Routing Signals to A, B, and Z Counter Inputs
Routing Counter n Z Signal to an Output Terminal
Counter n Up_Down Signal
Counter n HW Arm Signal
Routing Signals to Counter n HW Arm Input
Counter n Internal Output and Counter n TC Signals
Routing Counter n Internal Output to an Output Terminal
Frequency Output Signal
Routing Frequency Output to a Terminal
Default Counter/Timer Pinouts
Table 7-4. 68-Pin Device Default NI-DAQmx Counter/Timer Pins
Counter Triggering
Other Counter Features
Cascading Counters
Counter Filters
Table 7-5. Filters
Figure 7-30. Filter Example
Prescaling
Figure 7-31. Prescaling
Duplicate Count Prevention
Example Application That Works Correctly (No Duplicate Counting)
Figure 7-32. Duplicate Count Prevention Example
Example Application That Works Incorrectly (Duplicate Counting)
Figure 7-33. Duplicate Count Example
Example Application That Prevents Duplicate Count
Figure 7-34. Duplicate Count Prevention Example
When To Use Duplicate Count Prevention
Enabling Duplicate Count Prevention in NI-DAQmx
Synchronization Modes
Table 7-6. Synchronization Mode Conditions
80 MHz Source Mode
Figure 7-35. 80 MHz Source Mode
Other Internal Source Mode
Figure 7-36. Other Internal Source Mode
External Source Mode
Figure 7-37. External Source Mode
Chapter 8 PFI
Figure 8-1. M Series PFI Circuitry
Using PFI Terminals as Timing Input Signals
Exporting Timing Output Signals Using PFI Terminals
Using PFI Terminals as Static Digital I/Os
Connecting PFI Input Signals
Figure 8-2. PFI Input Signals Connections
PFI Filters
Table 8-1. Filters
Figure 8-3. Filter Example
I/O Protection
Programmable Power-Up States
Chapter 9 Digital Routing and Clock Generation
Clock Routing
Figure 9-1. M Series Clock Routing Circuitry
80 MHz Timebase
20 MHz Timebase
100 kHz Timebase
External Reference Clock
10 MHz Reference Clock
Synchronizing Multiple Devices
Real-Time System Integration (RTSI)
RTSI Connector Pinout
Figure 9-2. M Series PCI/PCI Express Device RTSI Pinout
Table 9-1. RTSI Signals
Using RTSI as Outputs
Using RTSI Terminals as Timing Input Signals
RTSI Filters
Table 9-2. Filters
Figure 9-3. Filter Example
PXI Clock and Trigger Signals
PXI_CLK10
PXI Triggers
PXI_STAR Trigger
PXI_STAR Filters
Table 9-3. Filters
Figure 9-4. Filter Example
Chapter 10 Bus Interface
DMA Controllers and USB Signal Stream
PXI Considerations
PXI Clock and Trigger Signals
PXI and PXI Express
Using PXI with CompactPCI
Data Transfer Methods
Changing Data Transfer Methods
Chapter 11 Triggering
Triggering with a Digital Source
Figure 11-1. Falling-Edge Trigger
Triggering with an Analog Source
Figure 11-2. Analog Trigger Circuit
APFI <0..1> Terminals
Analog Input Channels
Analog Trigger Actions
Routing Analog Comparison Event to an Output Terminal
Analog Trigger Types
Figure 11-3. Below-Level Analog Triggering Mode
Figure 11-4. Above-Level Analog Triggering Mode
Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example
Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example
Figure 11-7. Analog Window Triggering Mode (Entering Window)
Analog Trigger Accuracy
Appendix A Device-Specific Information
Table A-1. Default NI-DAQmx Counter/Timer Pins
Table A-2. Default NI-DAQmx Counter/Timer Pins
Table A-3. Default NI-DAQmx Counter/Timer Pins
Table A-4. Default NI-DAQmx Counter/Timer Pins
Table A-5. Default NI-DAQmx Counter/Timer Pins
Figure A-6. FS/GS Switch
Figure A-7. Analog Input Circuitry
Figure A-8. Single-Ended Channels
Figure A-9. Analog Output Circuitry
Figure A-10. Digital I/O and Timing I/O Circuitry
Figure A-11. USER 1 and USER 2 BNC Connections
Figure A-12. Connecting PFI 8 to USER 1 BNC
Table A-6. Default NI-DAQmx Counter/Timer Pins
Table A-7. Default NI-DAQmx Counter/Timer Pins
Table A-8. Default NI-DAQmx Counter/Timer Pins
Table A-9. Default NI-DAQmx Counter/Timer Pins
Table A-10. Default NI-DAQmx Counter/Timer Pins
Table A-11. Default NI-DAQmx Counter/Timer Pins
Table A-12. Default NI-DAQmx Counter/Timer Pins
Figure A-20. FS/GS Switch
Figure A-21. Analog Input Circuitry
Figure A-22. Single-Ended Channels
Figure A-23. Analog Output Circuitry
Figure A-24. Digital I/O and Timing I/O Circuitry
Figure A-25. USER 1 and USER 2 BNC Connections
Figure A-26. Connecting PFI 8 to USER 1 BNC
Table A-13. Default NI-DAQmx Counter/Timer Pins
Table A-14. Default NI-DAQmx Counter/Timer Pins
Table A-15. Default NI-DAQmx Counter/Timer Pins
Table A-16. Default NI-DAQmx Counter/Timer Pins
Figure A-31. FS/GS Switch
Figure A-32. Analog Input Circuitry
Figure A-33. Single-Ended Channels
Figure A-34. Analog Output Circuitry
Figure A-35. Digital I/O and Timing I/O Circuitry
Figure A-36. Analog Programmable Function Interface Circuitry
Figure A-37. USER 1 and USER 2 BNC Connections
Figure A-38. Connecting PFI 8 to USER 1 BNC
Table A-17. Default NI-DAQmx Counter/Timer Pins
Table A-18. Default NI-DAQmx Counter/Timer Pins
Table A-19. Default NI-DAQmx Counter/Timer Pins
Table A-20. Default NI-DAQmx Counter/Timer Pins
Table A-21. Default NI-DAQmx Counter/Timer Pins
Table A-22. Default NI-DAQmx Counter/Timer Pins
Table A-23. Default NI-DAQmx Counter/Timer Pins
Table A-24. Default NI-DAQmx Counter/Timer Pins
Figure A-47. FS/GS Switch
Figure A-48. Analog Input Circuitry
Figure A-49. Single-Ended Channels
Figure A-50. Analog Output Circuitry
Figure A-51. Digital I/O and Timing I/O Circuitry
Figure A-52. Analog Programmable Function Interface Circuitry
Figure A-53. USER 1 and USER 2 BNC Connections
Figure A-54. Connecting PFI 8 to USER 1 BNC
Table A-25. Default NI-DAQmx Counter/Timer Pins
Table A-26. Default NI-DAQmx Counter/Timer Pins
Table A-27. Default NI-DAQmx Counter/Timer Pins
Table A-28. Default NI-DAQmx Counter/Timer Pins
Table A-29. Default NI-DAQmx Counter/Timer Pins
Table A-30. Default NI-DAQmx Counter/Timer Pins
Table A-31. Default NI-DAQmx Counter/Timer Pins
Table A-32. Default NI-DAQmx Counter/Timer Pins
Table A-33. Default NI-DAQmx Counter/Timer Pins
Appendix B Timing Diagrams
Figure B-1. M Series Analog Input Timing Engine
Figure B-2. Input Timing and the Analog Input Timing Engine
Figure B-3. Input Timing Diagram
Table B-1. Input Timing
Figure B-4. AI Timing Clocks and the Analog Input Timing Engine
Figure B-5. AI Timing Clocks Timing Diagram
Table B-2. AI Timing Clocks Timing
Figure B-6. Convert Clock and the Analog Input Timing Engine
Figure B-7. Convert Clock Timing Diagram
Table B-3. Convert Clock Timing
Figure B-8. Convert Clock and Any Internal Signal Timing Diagram
Table B-4. Convert Clock and Any Internal Signal Timing
Figure B-9. Convert Clock Timebase Timing and the Analog Input Timing Engine
Figure B-10. Convert Clock Timebase Timing Diagram
Table B-5. Convert Clock Timebase Timing
Figure B-11. Sample Clock Timebase Timing and the Analog Input Timing Engine
Figure B-12. Sample Clock Timebase Timing Diagram
Table B-6. Sample Clock Timebase Timing
Figure B-13. Reference Trigger and the Analog Input Timing Engine
Figure B-14. Reference Trigger Timing Diagram
Table B-7. Reference Trigger Timing
Figure B-15. Sample Clock and the Analog Input Timing Engine
Figure B-16. Sample Clock Timing Diagram
Table B-8. Sample Clock Timing
Figure B-17. AI_Sample_In_Progress Timing Diagram
Table B-9. AI_Sample_In_Progress Timing
Figure B-18. Pause Trigger and the Analog Input Timing Engine
Figure B-19. Pause Trigger Timing Diagram
Table B-10. Pause Trigger Timing
Figure B-20. Output Timing and the Analog Input Timing Engine
Figure B-21. Output Timing Diagram
Table B-11. Output Timing
Figure B-22. M Series Analog Output Timing
Figure B-23. Input Timing Diagram
Table B-12. Input Timing
Figure B-24. External Update Source Clock Insertions Timing Diagram
Table B-13. External Update Source Clock Insertions Timing
Figure B-25. Sample Clock Timebase and the Sync Sample Clock Timebase Timing Diagram
Table B-14. Sample Clock Timebase and the Sync Sample Clock Timebase Timing
Figure B-26. Start Trigger Input Delay Path
Figure B-27. Start Trigger Timing Diagram
Table B-15. Start Trigger Timing from Signal_i to Selected Start Trigger
Table B-16. Start Trigger Setup and Hold Timing
Figure B-28. Pause Trigger Input Delay Path
Figure B-29. Pause Trigger Timing Diagram
Table B-17. Pause Trigger Timing from Signal_i to Selected Pause Trigger
Table B-18. Pause Trigger Setup and Hold Timing
Figure B-30. External Trigger and External Clock Application
Figure B-31. Start Trigger Path
Figure B-32. Start Trigger Output Delay Timing Diagram
Table B-19. Start Trigger Output Delay Timing
Figure B-33. Pause Trigger Path
Figure B-34. Pause Trigger Output Routing Delay Timing Diagram
Table B-20. Pause Trigger Output Routing Delay Timing
Figure B-35. Sample Clock Path
Figure B-36. Sample Clock Delay Timing Diagram
Table B-21. Sample Clock Delay Timing
Figure B-37. Digital Waveform Acquisition Timing Circuitry
Figure B-38. Digital Waveform Acquisition Timing Delays
Table B-22. DI Timing Delays
Table B-23. DI Timing Requirements
Figure B-39. Digital Waveform Generation Timing Circuitry
Figure B-40. Digital Waveform Acquisition Timing Delays
Table B-24. DO Timing Delays
Table B-25. DO Timing Requirements
Figure B-41. Counter/Timer Circuitry
Figure B-42. Pin to Internal Signal Delays Timing Diagram
Table B-26. Pin to Internal Signal Delays Timing
Figure B-43. Selected Gate Delays Timing Diagram
Table B-27. Selected Gate Delays Timing
Figure B-44. Selected Source Delays Timing Diagram
Table B-28. Selected Source Delays Timing
Figure B-45. Count Enable Delays
Table B-29. Selected Gate to Count Enable Delays
Figure B-46. Counter n Source Timing Requirements
Table B-30. Counter n Source Timing
Figure B-47. Counter n Gate Pulse Width Timing Diagram
Table B-31. Counter n Gate Pulse Width Timing
Figure B-48. Gate to Source Setup and Hold Timing Diagram
Table B-32. Gate to Source Setup and Hold Timing
Figure B-49. DAQ-STC2 Internal Block Setup and Hold Requirements Timing Diagram
Table B-33. DAQ-STC2 Internal Block Setup and Hold Requirements Timing
Figure B-50. Output Delays
Table B-34. Output Delays Timing
Figure B-51. Quadrature and Two Pulse Encoder Timing Diagrams
Table B-35. Quadrature and Two Pulse Encoder Timing
Figure B-52. Generating Different Clocks from the Onboard 80 MHz Oscillator
Table B-36. Generating Different Clocks from the Onboard 80 MHz Oscillator
Figure B-53. Generating Different Clocks Using an External Reference Clock and the PLL
Table B-37. Generating Different Clocks Using an External Reference Clock and the PLL
Appendix C Troubleshooting
Figure C-1. AI Sample Clock and AI Convert Clock
Appendix D Upgrading from E Series to M Series
Appendix E Technical Support and Professional Services
Glossary
Symbols
A-B
C
D
E
F
G-H
I
K-M
N
O-P
Q-R
T
U-W
Index
Symbols
Numerics
A
B-C
D
E
F-G
H-I
K-M
N-O
P
Q-S
T
U
W-X