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PCIe机械及电气规范.pdf
Contents
1. Introduction
1.1. Terms and Definitions
1.2. Reference Documents
1.3. Specification Contents
1.4. Objectives
1.5. Electrical Overview
1.6. Mechanical Overview
2. Auxiliary Signals
2.1. Reference Clock
2.1.1. Low Voltage Swing, Differential Clocks
2.1.2. Spread Spectrum Clocking (SSC)
2.1.3. REFCLK AC Specifications
2.1.4. REFCLK Phase Jitter Specification
2.2. PERST# Signal
2.2.1. Initial Power-Up (G3 to L0)
2.2.2. Power Management States (S0 to S3/S4 to S0)
2.2.3. Power Down
2.3. WAKE# Signal
2.4. SMBus (Optional)
2.4.1. Capacitive Load of High-power SMBus Lines
2.4.2. Minimum Current Sinking Requirements for SMBus Devices
2.4.3. SMBus “Back Powering” Considerations
2.4.4. Power-on Reset
2.5. JTAG Pins (Optional)
2.6. Auxiliary Signal Parametric Specifications
2.6.1. DC Specifications
2.6.2. AC Specifications
3. Hot Insertion and Removal
3.1. Scope
3.2. Presence Detect
4. Electrical Requirements
4.1. Power Supply Requirements
4.2. Power Consumption
4.3. Power Supply Sequencing
4.4. Power Supply Decoupling
4.5. Electrical Topologies and Link Definitions
4.5.1. Topologies
4.5.2. Link Definition
4.6. Electrical Budgets
4.6.1. AC Coupling Capacitors
4.6.2. Insertion Loss Values (Voltage Transfer Function)
4.6.3. Jitter Values
4.6.4. Crosstalk
4.6.5. Lane-to-Lane Skew
4.6.6. Equalization
4.6.7. Skew within the Differential Pair
4.7. Eye Diagrams at the Add-in Card Interface
4.7.1. Add-in Card Transmitter Path Compliance Eye-Diagram
4.7.2. Add-in Card Minimum Receiver Path Sensitivity Requirements
4.7.3. System Board Transmitter Path Compliance Eye Diagram
4.7.4. System Board Minimum Receiver Path Sensitivity Requirements
5. Connector Specification
5.1. Connector Pinout
5.2. Connector Interface Definitions
5.3. Signal Integrity Requirements and Test Procedures
5.4. Connector Environmental and Other Requirements
5.4.1. Environmental Requirements
5.4.2. Mechanical Requirements
5.4.3. Current Rating Requirement
5.4.4. Additional Considerations
6. Add-in Card Form Factors and Implementation
6.1. Add-in Card Form Factors
6.2. Connector and Add-in Card Locations
6.3. Card Interoperability
Acknowledgements
PCI Express™
Card Electromechanical
Specification
Revision 1.1
March 28, 2005
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
Revision
1.0
1.0a
1.1
Revision History
Initial release.
Incorporated WG Errata C1-C7 and E1.
Date
7/22/02
4/15/03
Incorporated approved Errata and ECNs.
03/28/05
PCI-SIG disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 503-291-2569
Fax: 503-297-1090
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Express Card Electromechanical Specification is provided “as is” with no
warranties whatsoever, including any warranty of merchantability, noninfringement,
fitness for any particular purpose, or any warranty otherwise arising out of any proposal,
specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary
rights, relating to use of information in this specification. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI Express is a trademark of PCI-SIG.
All other product names are trademarks, registered trademarks, or service marks of their
respective owners.
Copyright © 2002-2005 PCI-SIG
2
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
Contents
1. INTRODUCTION....................................................................................................................7
1.1. TERMS AND DEFINITIONS ..................................................................................................... 7
1.2. REFERENCE DOCUMENTS ..................................................................................................... 9
1.3. SPECIFICATION CONTENTS................................................................................................... 9
1.4. OBJECTIVES............................................................................................................................. 10
1.5. ELECTRICAL OVERVIEW ..................................................................................................... 10
1.6. MECHANICAL OVERVIEW ................................................................................................... 11
2. AUXILIARY SIGNALS........................................................................................................13
2.1. REFERENCE CLOCK............................................................................................................... 14
Low Voltage Swing, Differential Clocks .................................................................... 14
Spread Spectrum Clocking (SSC)............................................................................... 15
REFCLK AC Specifications........................................................................................ 16
REFCLK Phase Jitter Specification........................................................................... 19
2.2. PERST# SIGNAL ...................................................................................................................... 20
Initial Power-Up (G3 to L0)....................................................................................... 20
Power Management States (S0 to S3/S4 to S0) .......................................................... 21
Power Down............................................................................................................... 22
2.3. WAKE# SIGNAL ...................................................................................................................... 24
2.4. SMBUS (OPTIONAL)............................................................................................................... 27
2.4.1.
Capacitive Load of High-power SMBus Lines ........................................................... 27
2.4.2. Minimum Current Sinking Requirements for SMBus Devices.................................... 28
SMBus “Back Powering” Considerations ................................................................. 28
2.4.3.
2.4.4.
Power-on Reset .......................................................................................................... 28
2.5. JTAG PINS (OPTIONAL) ......................................................................................................... 29
2.6. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS................................................... 30
DC Specifications....................................................................................................... 30
AC Specifications ....................................................................................................... 31
3. HOT INSERTION AND REMOVAL..................................................................................33
3.1. SCOPE
.................................................................................................................................... 33
3.2. PRESENCE DETECT................................................................................................................ 33
4. ELECTRICAL REQUIREMENTS .....................................................................................35
4.1. POWER SUPPLY REQUIREMENTS ...................................................................................... 35
4.2. POWER CONSUMPTION ........................................................................................................ 36
4.3. POWER SUPPLY SEQUENCING............................................................................................ 37
4.4. POWER SUPPLY DECOUPLING............................................................................................ 38
4.5. ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS .................................................... 38
Topologies .................................................................................................................. 38
Link Definition............................................................................................................ 40
4.6. ELECTRICAL BUDGETS ........................................................................................................ 41
AC Coupling Capacitors ............................................................................................ 42
Insertion Loss Values (Voltage Transfer Function) ................................................... 42
Jitter Values................................................................................................................ 44
Crosstalk..................................................................................................................... 46
Lane-to-Lane Skew..................................................................................................... 46
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.5.
2.6.1.
2.6.2.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.2.1.
2.2.2.
2.2.3.
4.5.1.
4.5.2.
3
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
4.6.6.
4.6.7.
4.7.1.
4.7.2.
4.7.3.
4.7.4.
Equalization ............................................................................................................... 47
Skew within the Differential Pair ............................................................................... 47
4.7. EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE..................................................... 47
Add-in Card Transmitter Path Compliance Eye-Diagram ........................................ 48
Add-in Card Minimum Receiver Path Sensitivity Requirements................................ 49
System Board Transmitter Path Compliance Eye Diagram....................................... 50
System Board Minimum Receiver Path Sensitivity Requirements.............................. 52
5. CONNECTOR SPECIFICATION.......................................................................................53
5.1. CONNECTOR PINOUT ............................................................................................................ 53
5.2. CONNECTOR INTERFACE DEFINITIONS........................................................................... 58
5.3. SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES ................................ 62
5.4. CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS ................................ 65
5.4.1.
Environmental Requirements ..................................................................................... 65
5.4.2. Mechanical Requirements .......................................................................................... 67
Current Rating Requirement ...................................................................................... 68
5.4.3.
5.4.4.
Additional Considerations.......................................................................................... 69
6. ADD-IN CARD FORM FACTORS AND IMPLEMENTATION ....................................71
6.1. ADD-IN CARD FORM FACTORS........................................................................................... 71
6.2. CONNECTOR AND ADD-IN CARD LOCATIONS ............................................................... 81
6.3. CARD INTEROPERABILITY .................................................................................................. 87
ACKNOWLEDGEMENTS ........................................................................................................89
4
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
Figures
FIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR................................................................. 11
FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER..... 12
FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM ................................................................. 14
FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION................................ 15
FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT
AND SWING ............................................................................................................................. 17
FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT.......... 17
FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME
MATCHING............................................................................................................................... 18
FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD 18
FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME.......... 18
FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK ............................. 18
FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING ....... 19
FIGURE 2-10: POWER UP ................................................................................................................ 21
FIGURE 2-11: POWER MANAGEMENT STATES......................................................................... 22
FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS ............................................... 23
FIGURE 2-13: POWER DOWN......................................................................................................... 23
FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS............................... 31
FIGURE 3-1: PRESENCE DETECT IN A HOT-PLUG ENVIRONMENT...................................... 34
FIGURE 4-1: PCI EXPRESS ON THE SYSTEM BOARD............................................................... 39
FIGURE 4-2: PCI EXPRESS CONNECTOR ON SYSTEM BOARD WITH AN ADD-IN CARD. 39
FIGURE 4-3: PCI EXPRESS CONNECTOR ON A RISER CARD WITH AN ADD-IN CARD .... 40
FIGURE 4-4: LINK DEFINITION FOR TWO COMPONENTS ...................................................... 41
FIGURE 4-5: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR
INTERFACE .............................................................................................................................. 42
FIGURE 4-6: INSERTION LOSS BUDGETS................................................................................... 43
FIGURE 4-7: JITTER BUDGET ........................................................................................................ 44
FIGURE 4-8: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM............ 48
FIGURE 4-9: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD
RECEIVER PATH COMPLIANCE .......................................................................................... 49
FIGURE 4-10: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE
DIAGRAM................................................................................................................................. 50
FIGURE 4-11: TWO-PORT MEASUREMENT MODEL ................................................................. 51
FIGURE 4-12: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD
RECEIVER PATH COMPLIANCE .......................................................................................... 52
FIGURE 5-1: CONNECTOR FORM FACTOR................................................................................. 58
FIGURE 5-2: RECOMMENDED FOOTPRINT................................................................................ 59
FIGURE 5-3: ADD-IN CARD EDGE-FINGER DIMENSIONS....................................................... 60
FIGURE 5-4: ILLUSTRATION OF ADJACENT PAIRS ................................................................. 65
FIGURE 5-5: CONTACT RESISTANCE MEASUREMENT POINTS............................................ 66
FIGURE 6-1: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITHOUT THE I/O
BRACKET ................................................................................................................................. 72
FIGURE 6-2: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET
AND CARD RETAINER........................................................................................................... 73
FIGURE 6-3: ADDITIONAL FEATURE AND KEEPOUTS ON THE X16 GRAPHICS CARD ... 74
FIGURE 6-4: STANDARD ADD-IN CARD I/O BRACKET ........................................................... 75
FIGURE 6-5: BRACKET DESIGN WITH THE MOUNTING TABS MOUNTED ON THE
PRIMARY SIDE OF THE ADD-IN CARD.............................................................................. 76
5
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
FIGURE 6-6: ADD-IN CARD RETAINER ....................................................................................... 77
FIGURE 6-7: LOW PROFILE PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET . 78
FIGURE 6-8: LOW PROFILE PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET ......... 79
FIGURE 6-9: LOW PROFILE I/O BRACKET.................................................................................. 80
FIGURE 6-10: EXAMPLE OF A PC SYSTEM IN MICROATX FORM FACTOR ........................ 81
FIGURE 6-11: INTRODUCTION OF A PCI EXPRESS CONNECTOR IN A MICROATX
SYSTEM .................................................................................................................................... 82
FIGURE 6-12: MORE PCI EXPRESS CONNECTORS ARE INTRODUCED ON A MICROATX
SYSTEM BOARD ..................................................................................................................... 83
FIGURE 6-13: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH
ONE PCI EXPRESS CONNECTOR ......................................................................................... 84
FIGURE 6-14: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH
TWO PCI EXPRESS CONNECTORS ...................................................................................... 85
FIGURE 6-15: CARD ASSEMBLED IN CONNECTOR.................................................................. 86
Tables
TABLE 2-1: REFCLCK DC SPECIFICATIONS AND AC TIMING REQUIREMENTS ............... 16
TABLE 2-2: MAXIMUM ALLOWED PHASE JITTER WHEN APPLIED TO FIXED FILTER
CHARACTERISTIC.................................................................................................................. 20
TABLE 2-3: AUXILIARY SIGNAL DC SPECIFICATIONS - PERST#, WAKE#, AND SMBUS 30
TABLE 2-4: POWER SEQUENCING AND RESET SIGNAL TIMINGS ....................................... 31
TABLE 4-1: POWER SUPPLY RAIL REQUIREMENTS................................................................ 35
TABLE 4-2: ADD-IN CARD POWER DISSIPATION..................................................................... 36
TABLE 4-3: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET ........... 43
TABLE 4-4: TOTAL SYSTEM JITTER BUDGET........................................................................... 45
TABLE 4-5: ALLOCATION OF INTERCONNECT JITTER BUDGET ......................................... 45
TABLE 4-6: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW..................................... 47
TABLE 4-7: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS.. 48
TABLE 4-8: ADD-IN CARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS 49
TABLE 5-1: PCI EXPRESS CONNECTORS PINOUT .................................................................... 53
TABLE 5-2: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES.................... 63
TABLE 5-3: TEST DURATIONS ...................................................................................................... 66
TABLE 5-4: MECHANICAL TEST PROCEDURES AND REQUIREMENTS .............................. 67
TABLE 5-5: END OF LIFE CURRENT RATING TEST SEQUENCE............................................ 68
TABLE 5-6: ADDITIONAL REQUIREMENTS ............................................................................... 69
TABLE 6-1: ADD-IN CARD SIZES.................................................................................................. 71
TABLE 6-2: CARD INTEROPERABILITY...................................................................................... 87
6
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
1
Introduction
1.
This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus
is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical
and electrical specifications. The discussions are confined to ATX or ATX-based form factors.
Other form factors, such as PCI Express Mini Card are covered in other separate specifications.
Terms and Definitions
A card that is plugged into a connector and mounted in a chassis
slot.
A system board form factor. Refer to the ATX Specification,
Revision. 2.2.
1.1.
Add-in card
ATX
ATX-based form factor Refers to the form factor that does not exactly conform to the
Auxiliary signals
Basic bandwidth
x1, x4, x8, x16
Down-plugging
Down-shifting
Evolutionary strategy A strategy to develop the PCI Express connector and card form
High bandwidth
ATX specification, but uses the key features of the ATX, such as
the slot spacing, I/O panel definition, etc.
Signals not required by the PCI Express architecture but necessary
for certain desired functions or system implementation, for
example, the SMBus signals.
Contains one PCI Express Lane
x1 refers to one PCI Express Lane of basic bandwidth; x4 refers to a
collection of four PCI Express Lanes; etc.
Plugging a larger Link card into a smaller Link connector; for example,
plugging a x4 card into a x1 connector
Plugging a PCI Express card into a connector that is not fully
routed for all of the PCI Express Lanes; for example, plugging
a x4 card into a x8 capable connector with only four Lanes
being routed
factors within today’s chassis and system board form factor
infrastructure constraints.
Supports larger number of PCI Express Lanes, such as a x16 card
or connector.
5
10
15
20
25
30
7
PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1
5
10
15
20
25
Insertion and/or removal of a card into an active backplane or
system board as defined in PCI Standard Hot-Plug Controller and
Subsystem Specification, Revision. 1.0. No special card support is required.
Insertion and/or removal of a card into a passive backplane. The
card must satisfy specific requirements to support Hot swap.
Ability to plug a PCI Express card into different Link connectors
and the system works, for example, plugging a x1 PCI Express
I/O card into a x16 graphics slot.
A collection of one or more PCI Express Lanes
An add-in card whose height is no more than 68.90 mm
(2.731 inches)
An ATX-based system board form factor. Refer to the microATX
Motherboard Interface Specification, Revision 1.2.
Hot-Plug
Hot swap
Interoperability
Link
Low profile card
microATX
PCI Express Mini Card PCI Express for mobile form factor, similar to Mini PCI
One PCI Express Lane contains two differential lines for
PCI Express Lane
Transmitter and two differential lines for Receiver. A by-N Link
is composed of N Lanes.
A method for signaling events and conditions using physical
sideband signaling
signals separate from signals forming the Link between two
components.
An add-in card whose height is no more than 111.15 mm
Standard height card
(4.376 inches)
Plug a smaller Link card into a larger Link connector; for
Up-plugging
example, plugging a x1 card into a x4 connector
A mechanism used by a component to request the reapplication of
wakeup
main power when in the L2 Link state. Two such mechanisms are
defined in the PCI Express Base Specification, Revision 1.1: Beacon and
WAKE#. This specification requires the use of WAKE# on any add-in
card or system board that supports wakeup functionality.
8
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