library ieee; use ieee.std_logic_1164.all; entity mul is port(a,b:in std_logic_vector(0 to 4); p:out std_logic_vector(0 to 9)); end mul; architecture s_mul of mul is component fa is port(a,b,ci:in std_logic; s,co:out std_logic); end component; signal s1:std_logic_vector(1 to 12); signal c1:std_logic_vector(1 to 19); begin p(0)<=a(0) and b(0); f11:fa port map((a(1) and b(0)),(a(0) and b(1)),'0',p(1),c1(1)); f12:fa port map((a(2) and b(0)),(a(1) and b(1)),'0',s1(1),c1(2)); f13:fa port map((a(3) and b(0)),(a(2) and b(1)),'0',s1(2),c1(3)); f14:fa port map((a(4) and b(0)),(a(3) and b(1)),'0',s1(3),c1(4)); f21:fa port map(s1(1),(a(0) and b(2)),c1(1),p(2),c1(5)); f22:fa port map(s1(2),(a(1) and b(2)),c1(2),s1(4),c1(6)); f23:fa port map(s1(3),(a(2) and b(2)),c1(3),s1(5),c1(7)); f24:fa port map((a(4) and b(1)),(a(3) and b(2)),c1(4),s1(6),c1(8)); f31:fa port map(s1(4),(a(0) and b(3)),c1(5),p(3),c1(9)); f32:fa port map(s1(5),(a(1) and b(3)),c1(6),s1(7),c1(10)); f33:fa port map(s1(6),(a(2) and b(3)),c1(7),s1(8),c1(11)); f34:fa port map((a(4) and b(2)),(a(3) and b(3)),c1(8),s1(9),c1(12)); f41:fa port map(s1(7),(a(0) and b(4)),c1(9),p(4),c1(13)); f42:fa port map(s1(8),(a(1) and b(4)),c1(10),s1(10),c1(14)); f43:fa port map(s1(9),(a(2) and b(4)),c1(11),s1(11),c1(15)); f44:fa port map((a(4) and b(3)),(a(3) and b(4)),c1(12),s1(12),c1(16)); f51:fa port map(s1(10), c1(13),p(5),c1(17)); f52:fa port map(s1(11),c1(17),c1(14),p(6),c1(18)); f53:fa port map(s1(12),c1(18),c1(15),p(7),c1(19)); f54:fa port map((a(4) and b(4)),c1(19),c1(16),p(8),p(9)); end s_mul;