Protected Mode Software Architecture（理解保护模式）.pdf

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Protected Mode Software Architecture MINDSHARE, INC. Tom Shanley ▲ ▼▼ Addison-Wesley Publishing Company Reading, Massachusetts • Menlo Park, California New York Don Mills, Ontario Harlow, England Amsterdam Bonn Sydney Singapore Tokyo Madrid San Juan Paris Seoul Milan Mexico City Taipei

Many of the designations used by manufacturers and sellers to distinguish their prod- ucts are claimed as trademarks. Where those designators appear in this book, and Addi- son-Wesley was aware of the trademark claim, the designations have been printed in initial capital letters or all capital letters. The authors and publishers have taken care in preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connec- tion with or arising out of the use of the information or programs contained herein. Library of Congress Cataloging-in-Publication Data ISBN: 0-201-55447-X Copyright ©1996 by MindShare, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopy- ing, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States of America. Published simultaneously in Canada. Sponsoring Editor: Kathleen Tibbetts Project Manager: Deborah McKenna Cover Design: Barbara T. Atkinson Set in 10 point Palatino by MindShare, Inc. 1 2 3 4 5 6 7 8 9-MA-9998979696 First Printing, February 1996 Addison-Wesley books available for bulk purchases by corporations, institutions, and other organizations. For more information please contact the Corporate, Government, and Special Sales Department at (800) 238-9682. Find A-W Developers Press on the World-Wide Web at: http://www/aw.com/devpress/

To my pal Nancy.

Contents About This Book The MindShare Architecture Series ...................................................................................... 1 Cautionary Note ........................................................................................................................ 2 What This Book Covers ........................................................................................................... 2 What this Book Does not Cover ............................................................................................. 2 Organization of This Book ...................................................................................................... 2 Who this Book is For ................................................................................................................ 3 Prerequisite Knowledge .......................................................................................................... 3 Documentation Conventions .................................................................................................. 3 Hexadecimal Notation ....................................................................................................... 4 Binary Notation ................................................................................................................... 4 Decimal Notation ................................................................................................................ 4 Signal Name Representation .................................................................................................. 4 Identification of Bit Fields (logical groups of bits or signals) ......................................... 5 Register Field References ........................................................................................................ 5 Visit Our Web Page .................................................................................................................. 5 We Want Your Feedback .......................................................................................................... 5 Part One Background Chapter 1: Single-Task OS and Application ............................9 Operating System Overview ................................................................................................... 9 Command Line Interpreter (CLI) ..................................................................................... 9 Program Loader ................................................................................................................ 10 OS Services ......................................................................................................................... 10 Direct IO Access ...................................................................................................................... 11 Applications Program Memory Usage ................................................................................ 11 Task Initiation, Execution and Termination ...................................................................... 11 Chapter 2: Definition of Multitasking ....................................13 Concept ...................................................................................................................................... 13 An Example—Timeslicing ..................................................................................................... 14 Another Example—Awaiting an Event ............................................................................... 14 Task Issues Call to OS for Disk Read ............................................................................. 14 OS Suspends Task ............................................................................................................. 15 OS Initiates Disk Read ...................................................................................................... 15 OS Makes Entry in Event Queue .................................................................................... 15 v

Contents OS Starts or Resumes Another Task ............................................................................... 15 Disk-Generated IRQ Causes Jump to OS ...................................................................... 15 Task Queue Checked ........................................................................................................ 16 OS Resumes Task .............................................................................................................. 16 Chapter 3: Multitasking Problems ...........................................17 OS Protects Territorial Integrity ........................................................................................... 17 Stay in Your Own Memory Area .......................................................................................... 18 IO Port Anarchy ....................................................................................................................... 18 Unauthorized Use of OS’s Tools .......................................................................................... 19 No Interrupts, Please! ............................................................................................................. 20 BIOS Calls ................................................................................................................................ 21 Part Two: Register Set & Real Mode Chapter 4: The Control Registers .............................................25 Control Register 0 (CR0) ........................................................................................................ 25 CR0 Description ................................................................................................................ 25 CR0 State after Reset ......................................................................................................... 27 Control Register 1 (CR1) ........................................................................................................ 28 CR1 Description ................................................................................................................ 28 CR1 State after Reset ......................................................................................................... 28 Control Register 2 (CR2) ........................................................................................................ 29 CR2 Description ................................................................................................................ 29 CR2 State after Reset ......................................................................................................... 29 Control Register 3 (CR3) ........................................................................................................ 29 CR3 Description ................................................................................................................ 29 CR3 State after Reset ......................................................................................................... 30 Control Register 4 (CR4) ........................................................................................................ 30 CR4 Description ................................................................................................................ 30 CR4 State after Reset ......................................................................................................... 34 EFlags Register ......................................................................................................................... 35 EFlags Description ............................................................................................................ 35 EFlags State after Reset .................................................................................................... 38 Interrupt Descriptor Table Register (IDTR) ...................................................................... 40 Background ........................................................................................................................ 40 IDTR Description .............................................................................................................. 41 IDTR State after Reset ....................................................................................................... 41 Debug Registers ...................................................................................................................... 42 Debug Registers Description ........................................................................................... 42 Debug Registers State after Reset ................................................................................... 42 vi

Contents Chapter 5: Real Mode Operation ..............................................45 Special Note ............................................................................................................................. 45 286/386/486/Pentium Power-Up State .................................................................................. 45 Initial Memory Reads ............................................................................................................. 48 IO Port Addressing ................................................................................................................. 49 Memory Addressing ............................................................................................................... 49 General ................................................................................................................................ 49 Accessing the Code Segment ........................................................................................... 51 Accessing the Stack Segment ........................................................................................... 53 Accessing DS Data Segment ............................................................................................ 56 Accessing ES/FS/GS Data Segments ............................................................................. 56 An Example ........................................................................................................................ 57 Accessing Extended Memory in Real Mode ................................................................. 58 Big Real Mode .................................................................................................................... 61 Real Mode Instructions and Registers ................................................................................ 61 Registers Accessible in Real Mode ................................................................................. 61 Registers Inaccessible in Real Mode ............................................................................... 62 Instructions Usable in Real Mode ................................................................................... 62 Instructions Unusable in Real Mode .............................................................................. 62 Real Mode Interrupt/Exception Handling ......................................................................... 63 Protection in Real Mode ........................................................................................................ 67 Part Three: Protected Mode Chapter 6: x86 Protected Mode Intro .......................................71 General ...................................................................................................................................... 71 Memory Protection ................................................................................................................. 72 Segmentation ..................................................................................................................... 72 Virtual Memory Paging ................................................................................................... 72 IO Protection ............................................................................................................................ 73 Privilege Levels ....................................................................................................................... 74 Virtual 8086 Mode ................................................................................................................... 74 Task Switching ........................................................................................................................ 74 Interrupt Handling ................................................................................................................. 75 Chapter 7: Intro to Segmentation .............................................77 Special Note ............................................................................................................................. 77 Real Mode Limitations ........................................................................................................... 77 Introduction to Segment Descriptor .................................................................................... 78 vii

Contents Segment Register—Selects Descriptor Table and Entry ................................................. 79 Introduction to Descriptor Tables ....................................................................................... 81 Segment Descriptors Reside in Memory ....................................................................... 81 Global Descriptor Table (GDT) ....................................................................................... 82 Description .................................................................................................................. 82 Setting GDT Base Address and Size ....................................................................... 83 Local Descriptor Tables (LDTs) ...................................................................................... 85 General Segment Descriptor Format ................................................................................... 90 Granularity Bit ................................................................................................................... 90 Segment Base Address Field ........................................................................................... 90 Segment Size Field ............................................................................................................ 90 Default/Big Bit .................................................................................................................. 90 Code Segment Descriptor’s Default Bit .................................................................. 90 Stack Segment Descriptor’s Big Bit ......................................................................... 92 Segment Type Field .......................................................................................................... 92 Introduction to Type Field ........................................................................................ 92 Non-System Segment Types .................................................................................... 92 Segment Present Bit .......................................................................................................... 96 Descriptor Privilege Level (DPL) Field .......................................................................... 96 System Bit ........................................................................................................................... 96 Available Bit ....................................................................................................................... 97 Chapter 8: Code Segments .........................................................99 Selecting Code Segment to Execute ..................................................................................... 99 Code Segment Descriptor Format ...................................................................................... 101 Accessing Code Segment ..................................................................................................... 104 Privilege Checking ................................................................................................................ 107 General .............................................................................................................................. 107 Some Definitions ............................................................................................................. 107 Definition of a Task ................................................................................................. 107 Definition of a Procedure ........................................................................................ 108 CPL Definition .......................................................................................................... 108 DPL Definition ......................................................................................................... 108 Conforming and Non-Conforming Code Segments ........................................... 108 RPL Definition .......................................................................................................... 109 Calling a Procedure in Current Task ................................................................................. 110 Call Gate ................................................................................................................................. 110 The Problem ..................................................................................................................... 110 The Solution—Different Gateways .............................................................................. 111 Call Gate Example ........................................................................................................... 114 Execution Begins ...................................................................................................... 114 Call Gate Descriptor Read ...................................................................................... 114 viii

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