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FZ3B-2019-11-15.pdf

发布时间：2022-05-29 发布人：admin 分类：说明书 资料大小：0.38M 资料格式：pdf 举报 版权申诉
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    5 4 3 2 1 D C B A D C B A ALINX Confidential 5 4 3 Title Title Title Size Size Size PAGE01 Block diagram PAGE01 Block diagram PAGE01 Block diagram Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 1 1 1 o f o f o f 23 23 23
    D C B A 5 4 3 2 1 VCCAUX BLM18SG121TN1 L1 C1 470nF AGND VCCADC AGND VCCAUX R1 1K U1-1 BANK0 U7 PUDC_B W7 POR_OVERRIDE VCCADC VREFP VREFN VP VN DXP DXN GNDADC P12 T13 R12 R13 T12 U13 U12 P13 XAZU3EG-SFVC784-1-I AGND L2 BLM18SG121TN1 MODE[3:0] 0000 0001 0010 0011 0101 0110 0111 1110 BOOT MODE PS JTAG Quad_SPI(24b) Quad_SPI(32b) SD0(2.0) SD1(2.0) eMMC(1.8V) USB0(2.0) SD1 LS(3.0) Descritpion PS JTAG Interface 24-Bit addresssing(QSPI24) 32-Bit addresssing(QSPI32) SD2.0 SD2.0 eMMC version 4.5 at 1.8V USB 2.0 only SD 3.0 VCCAUX D1 BAS16XV2T1G AGND R2 4.7K BT1 VBAT_IN C5 4.7uF C6 100uF VCC_3V3 BATTERY_4 R4 4.7K PS_SRST_B 13,22 PS_POR_B PS_REF_CLK_503 20 PS_REF_CLK VCC_3V3 C4 47uF PS_POR_B M17 P18 Y18 P16 N19 R16 VCC_3V3 FPGA_DONE M21 R10 4.7K PS_PROG_B FPGA_TCK FPGA_TDI FPGA_TDO FPGA_TMS P21 R17 R19 R18 T21 N21 U1-5 BANK503 VCCO_PSIO3_503 VCCO_PSIO3_503 VCC_PSBATT PS_POR_B_503 PS_SRST_B_503 PS_REF_CLK_503 PS_DONE_503 PS_INIT_B_503 PS_PROG_B_503 PS_JTAG_TCK_503 PS_JTAG_TDI_503 PS_JTAG_TDO_503 PS_JTAG_TMS_503 VCC_PSAUX C2 0.1uF L3 C3 470nF L4 BLM18SG121TN1 BLM18SG121TN1 Y20 W20 N17 N18 22pF C7 1 Y1 32.768KHZ R5 4.7M VCC_PSADC GND_PSADC PS_PADI_503 PS_PADO_503 PS_ERROR_OUT_503 PS_ERROR_STATUS_503 P17 M20 PS_ERROR_OUT PS_ERROR_STATUS PS_MODE0_503 PS_MODE1_503 PS_MODE2_503 PS_MODE3_503 P19 P20 R20 T20 PS_MODE0 PS_MODE1 PS_MODE2 PS_MODE3 XAZU3EG-SFVC784-1-I 2 R8 R9 R11 R12 22pF C8 VCC_3V3 4.7K 4.7K 4.7K 4.7K SW1 SW DIP-4 R13 R14 R15 R16 220R 220R 220R 220R 1 2 KEY2 P1 P2 Button 3 4 P3 P4 VCC_3V3 R18 4.7K PS_PROG_B C10 0.1uF TP16 TP18 TP17 TP19 VCC_3V3 R20 R21 R22 R23 4.7K 4.7K 4.7K 4.7K TP20 1 2 3 4 5 6 1 2 3 4 5 6 H6 J1 FPGA_TDI FPGA_TDO FPGA_TCK FPGA_TMS PS_ERROR_OUT R6 1K PS_ERROR_STATUS R19 1K D2 LED D3 LED FPGA DONE LED VCC_3V3 D4 LED R25 499R FPGA_DONE ALINX Confidential 5 4 3 www.alinx.com Title Title Title Size Size Size Page02 Z7 Bank0 & BANK503 Page02 Z7 Bank0 & BANK503 Page02 Z7 Bank0 & BANK503 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 2 2 2 o f o f o f 23 23 23 D C B A
    5 4 3 2 1 VCC_PSAUX R26 4.7K C12 0.1uF U2 VCC C S_B VSS 8 6 1 4 MIO0_QSPI0_SCLK MIO5_QSPI0_SS_B VCC_PSAUX R27 4.7K R28 4.7K DQ0 DQ1 WP#/DQ2 HOLD#/DQ3 5 2 3 7 D A P 9 MT25QU256ABA1EW9-0SIT MIO4_QSPI0_IO0 MIO1_QSPI0_IO1 MIO2_QSPI0_IO2 MIO3_QSPI0_IO3 D C B A VCC_PSAUX C13 4.7uF C14 47uF U1-2 VCC1V8 BANK500 MIO0_QSPI0_SCLK MIO1_QSPI0_IO1 MIO2_QSPI0_IO2 MIO3_QSPI0_IO3 MIO4_QSPI0_IO0 MIO5_QSPI0_SS_B 17 17 21 CAN_TX CAN_RX PS_UART0_RX CAN_TX CAN_RX PS_UART0_RX AB17 AE16 AG17 AG15 AG16 AF15 AH15 AH16 AD16 AF16 AH17 AF17 AC16 AD17 VCCO_PSIO0_500 VCCO_PSIO0_500 VCCO_PSIO0_500 PS_MIO0_500 PS_MIO1_500 PS_MIO2_500 PS_MIO3_500 PS_MIO4_500 PS_MIO5_500 PS_MIO6_500 PS_MIO7_500 PS_MIO8_500 PS_MIO9_500 PS_MIO10_500 PS_MIO11_500 PS_MIO12_500 PS_MIO13_500 PS_MIO14_500 PS_MIO15_500 PS_MIO16_500 PS_MIO17_500 PS_MIO18_500 PS_MIO19_500 PS_MIO20_500 PS_MIO21_500 PS_MIO22_500 PS_MIO23_500 PS_MIO24_500 PS_MIO25_500 AE17 AC17 AH18 AG18 AE18 AF18 AC18 AC19 AE19 AD19 AC21 AB20 AB18 AB19 AB21 R29 PS_UART0_TX MMC_DAT0 MMC_DAT1 MMC_DAT2 MMC_DAT3 MMC_DAT4 MMC_DAT5 MMC_DAT6 MMC_DAT7 MMC_CMD 49.9R MMC_RSTN PS_UART1_TX PS_UART1_RX MMC_CCLK PS_UART0_TX 21 12 MMC_DAT0 12 MMC_DAT1 12 MMC_DAT2 12 MMC_DAT3 12 MMC_DAT4 12 MMC_DAT5 12 MMC_DAT6 12 MMC_DAT7 12 MMC_CMD 12 MMC_CCLK 12 MMC_RSTN PS_UART1_TX 18 PS_UART1_RX 18 SD0 XAZU3EG-SFVC784-1-I VCC_PSAUX C15 4.7uF C16 47uF U1-3 VCC1V8 BANK501 16 16 16 16 15 19 19 21,22 21,22 DP_AUX_OUT DP_HPD DP_OE DP_AUX_IN HUB_RESET_IO PS_IIC1_SCL PS_IIC1_SDA PS_IIC0_SCL PS_IIC0_SDA DP_AUX_OUT DP_HPD DP_OE DP_AUX_IN HUB_RESET_IO PS_IIC1_SCL PS_IIC1_SDA PS_IIC0_SCL PS_IIC0_SDA H20 L19 L15 J15 K15 G16 F16 H16 J16 L16 L17 H17 K17 VCCO_PSIO1_501 VCCO_PSIO1_501 PS_MIO26_501 PS_MIO27_501 PS_MIO28_501 PS_MIO29_501 PS_MIO30_501 PS_MIO31_501 PS_MIO32_501 PS_MIO33_501 PS_MIO34_501 PS_MIO35_501 PS_MIO36_501 PS_MIO37_501 PS_MIO38_501 PS_MIO39_501 PS_MIO40_501 PS_MIO41_501 PS_MIO42_501 PS_MIO43_501 PS_MIO44_501 PS_MIO45_501 PS_MIO46_501 PS_MIO47_501 PS_MIO48_501 PS_MIO49_501 PS_MIO50_501 PS_MIO51_501 J17 H18 H19 K18 J19 L18 K19 J20 K20 L20 H21 J21 M18 M19 L21 PCIE_RESET_N SPI1_SCLK PMIC_IRQB SPI1_SS SPI1_MISO SPI1_MOSI USB_RESET_N SD_CD SD_D0 SD_D1 SD_D2 SD_D3 SD_CMD R30 49.9R PCIE_RESET_N 17 21 SPI1_SCLK PMIC_IRQB 22 21 SPI1_SS 21 SPI1_MISO 21 SPI1_MOSI USB_RESET_N 14 19 SD_CD 19 SD_D0 19 SD_D1 19 SD_D2 19 SD_D3 19 SD_CMD 19 SD_CLK SD1 XAZU3EG-SFVC784-1-I VCC_PSAUX C17 4.7uF C18 47uF U1-4 VCC1V8 BANK502 G17 D18 VCCO_PSIO2_502 VCCO_PSIO2_502 14 14 14 14 14 14 14 14 14 14 14 USB_CLK USB_DIR USB_DATA2 USB_NXT USB_DATA0 USB_DATA1 USB_STP USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_CLK USB_DIR USB_DATA2 USB_NXT USB_DATA0 USB_DATA1 USB_STP USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 G18 D16 F17 B16 C16 A16 F18 E17 C17 D17 A17 PS_MIO52_502 PS_MIO53_502 PS_MIO54_502 PS_MIO55_502 PS_MIO56_502 PS_MIO57_502 PS_MIO58_502 PS_MIO59_502 PS_MIO60_502 PS_MIO61_502 PS_MIO62_502 PS_MIO63_502 PS_MIO64_502 PS_MIO65_502 PS_MIO66_502 PS_MIO67_502 PS_MIO68_502 PS_MIO69_502 PS_MIO70_502 PS_MIO71_502 PS_MIO72_502 PS_MIO73_502 PS_MIO74_502 PS_MIO75_502 PS_MIO76_502 PS_MIO77_502 E18 E19 A18 G19 B18 C18 D19 C19 B19 G20 G21 D20 A19 B20 F20 XAZU3EG-SFVC784-1-I USB_DATA7 PHY1_TXCK PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 PHY1_TXCTL PHY1_RXCK PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 PHY1_RXCTL PHY1_MDC PHY1_MDIO USB_DATA7 PHY1_TXCK PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 PHY1_TXCTL PHY1_RXCK PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 PHY1_RXCTL PHY1_MDC PHY1_MDIO 14 13 13 13 13 13 13 13 13 13 13 13 13 13 13 D C B A ALINX Confidential 5 4 3 Title Title Title Size Size Size PAGE03 Z7 MIO-Config PAGE03 Z7 MIO-Config PAGE03 Z7 MIO-Config Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 3 3 3 o f o f o f 23 23 23
    3 2 1 U1-8 VCCO_44 VCCO_44 BANK44 IO_L1P_AD11P_44 IO_L1N_AD11N_44 IO_L2P_AD10P_44 IO_L2N_AD10N_44 IO_L3P_AD9P_44 IO_L3N_AD9N_44 IO_L4P_AD8P_44 IO_L4N_AD8N_44 IO_L5P_HDGC_AD7P_44 IO_L5N_HDGC_AD7N_44 IO_L6P_HDGC_AD6P_44 IO_L6N_HDGC_AD6N_44 IO_L7P_HDGC_AD5P_44 IO_L7N_HDGC_AD5N_44 IO_L8P_HDGC_AD4P_44 IO_L8N_HDGC_AD4N_44 IO_L9P_AD3P_44 IO_L9N_AD3N_44 IO_L10P_AD2P_44 IO_L10N_AD2N_44 IO_L11P_AD1P_44 IO_L11N_AD1N_44 IO_L12P_AD0P_44 IO_L12N_AD0N_44 AD11 AD10 AB11 AC11 AA11 AA10 W10 Y10 Y9 AA8 AB10 AB9 XAZU3EG-SFVC784-1-I U1-9 VCCO_24 VCCO_24 BANK24 IO_L1P_AD15P_24 IO_L1N_AD15N_24 IO_L2P_AD14P_24 IO_L2N_AD14N_24 IO_L3P_AD13P_24 IO_L3N_AD13N_24 IO_L4P_AD12P_24 IO_L4N_AD12N_24 IO_L5P_HDGC_24 IO_L5N_HDGC_24 IO_L6P_HDGC_24 IO_L6N_HDGC_24 IO_L7P_HDGC_24 IO_L7N_HDGC_24 IO_L8P_HDGC_24 IO_L8N_HDGC_24 IO_L9P_AD11P_24 IO_L9N_AD11N_24 IO_L10P_AD10P_24 IO_L10N_AD10N_24 IO_L11P_AD9P_24 IO_L11N_AD9N_24 IO_L12P_AD8P_24 IO_L12N_AD8N_24 AA13 AB13 AB15 AB14 W14 W13 Y14 Y13 W12 W11 Y12 AA12 XAZU3EG-SFVC784-1-I U1-10 VCCO_25 VCCO_25 BANK25 IO_L1P_AD15P_25 IO_L1N_AD15N_25 IO_L2P_AD14P_25 IO_L2N_AD14N_25 IO_L3P_AD13P_25 IO_L3N_AD13N_25 IO_L4P_AD12P_25 IO_L4N_AD12N_25 IO_L5P_HDGC_25 IO_L5N_HDGC_25 IO_L6P_HDGC_25 IO_L6N_HDGC_25 IO_L7P_HDGC_25 IO_L7N_HDGC_25 IO_L8P_HDGC_25 IO_L8N_HDGC_25 IO_L9P_AD11P_25 IO_L9N_AD11N_25 IO_L10P_AD10P_25 IO_L10N_AD10N_25 IO_L11P_AD9P_25 IO_L11N_AD9N_25 IO_L12P_AD8P_25 IO_L12N_AD8N_25 E10 D10 E12 D11 C11 B10 B11 A10 A12 A11 D12 C12 XAZU3EG-SFVC784-1-I IO_AD11_15P IO_AD10_15N IO_AB11_14P IO_AC11_14N IO_W10_12P IO_Y10_12N IO_Y9_13P IO_AA8_13N IO_AD11_15P IO_AD10_15N IO_AB11_14P IO_AC11_14N IO_W10_12P IO_Y10_12N IO_Y9_13P IO_AA8_13N 21 21 21 21 21 21 21 21 BT1120_DATA5 BT1120_DATA4 BT1120_DATA3 BT1120_DATA2 BT1120_DATA1 BT1120_DATA0 BT1120_DATA5 BT1120_DATA4 BT1120_DATA3 BT1120_DATA2 BT1120_DATA1 BT1120_DATA0 21 21 21 21 21 21 PL_485_RXD FAN_PWM PL_LED PL_485_DE PL_485_RXD FAN_PWM PL_LED PL_485_DE 17 23 23 17 5 D C B A 4 VCC_3V3 C19 47uF IO_AH12_18P IO_AH11_18N IO_AF11_17P IO_AG11_17N IO_AE10_16P IO_AF10_16N IO_AH12_18P IO_AH11_18N IO_AF11_17P IO_AG11_17N 21 21 21 21 IO_AE10_16P IO_AF10_16N 21 21 21 21 21 21 21 21 21 21 21 21 21 21 GPIO_Z BT1120_DATA15 BT1120_DATA14 BT1120_DATA13 BT1120_DATA12 BT1120_DATA11 BT1120_DATA10 BT1120_DATA9 BT1120_CLK BT1120_DATA8 BT1120_DATA7 BT1120_DATA6 VCC_3V3 C20 47uF GPIO_Z BT1120_DATA15 BT1120_DATA14 BT1120_DATA13 BT1120_DATA12 BT1120_DATA11 BT1120_DATA10 BT1120_DATA9 BT1120_CLK BT1120_DATA8 BT1120_DATA7 BT1120_DATA6 VCC_3V3 C22 47uF 19 19 SECURE_PIOA SECURE_PIOB SECURE_PIOA SECURE_PIOB 17 PCIE_PRSNT PCIE_PRSNT PL_485_TXD PL_485_TXD 17 VCC_3V3 C23 47uF IO_B15_2P IO_A15_2N IO_B14_1P IO_A14_1N IO_B13_7P IO_A13_7N IO_C14_3P IO_C13_3N IO_D15_8P IO_D14_8N IO_E14_9P IO_E13_9N 21 21 21 21 21 21 21 21 21 21 21 21 IO_B15_2P IO_A15_2N IO_B14_1P IO_A14_1N IO_B13_7P IO_A13_7N IO_C14_3P IO_C13_3N IO_D15_8P IO_D14_8N IO_E14_9P IO_E13_9N AC10 AG12 AG10 AH10 AF11 AG11 AH12 AH11 AE10 AF10 AE12 AF12 AC12 AD12 AA14 AD13 AE15 AE14 AG14 AH14 AG13 AH13 AE13 AF13 AD15 AD14 AC14 AC13 B12 E11 J11 J10 K13 K12 H11 G10 J12 H12 G11 F10 F12 F11 C15 F14 B15 A15 B14 A14 B13 A13 C14 C13 D15 D14 E14 E13 U1-11 VCCO_26 VCCO_26 BANK26 IO_L1P_AD11P_26 IO_L1N_AD11N_26 IO_L2P_AD10P_26 IO_L2N_AD10N_26 IO_L3P_AD9P_26 IO_L3N_AD9N_26 IO_L4P_AD8P_26 IO_L4N_AD8N_26 IO_L5P_HDGC_AD7P_26 IO_L5N_HDGC_AD7N_26 IO_L6P_HDGC_AD6P_26 IO_L6N_HDGC_AD6N_26 IO_L7P_HDGC_AD5P_26 IO_L7N_HDGC_AD5N_26 IO_L8P_HDGC_AD4P_26 IO_L8N_HDGC_AD4N_26 IO_L9P_AD3P_26 IO_L9N_AD3N_26 IO_L10P_AD2P_26 IO_L10N_AD2N_26 IO_L11P_AD1P_26 IO_L11N_AD1N_26 IO_L12P_AD0P_26 IO_L12N_AD0N_26 G13 F13 F15 E15 G15 G14 H14 H13 K14 J14 L14 L13 IO_G13_4P IO_F13_4N IO_F15_10P IO_E15_10N IO_H14_5P IO_H13_5N IO_K14_11P IO_J14_11N IO_L14_6P IO_L13_6N XAZU3EG-SFVC784-1-I IO_G13_4P IO_F13_4N IO_F15_10P IO_E15_10N IO_H14_5P IO_H13_5N IO_K14_11P IO_J14_11N IO_L14_6P IO_L13_6N 21 21 21 21 21 21 21 21 21 21 www.alinx.com Title Title Title Size Size Size PAGE04 Z7 Bank44_24_25_26 PAGE04 Z7 Bank44_24_25_26 PAGE04 Z7 Bank44_24_25_26 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 4 4 4 o f o f o f 23 23 23 ALINX Confidential 5 4 3 D C B A
    5 4 3 2 1 +1.2V VCCO_HP C24 47uF R36 240 1% VRP_64 AC5 AD8 AG7 AC9 AD9 AE9 AE8 AB8 AC8 AD7 AE7 AB7 AC7 AB6 AC6 AD6 AG9 AH9 AF8 AG8 AH8 AH7 AG6 AG5 AF7 AF6 AE5 AF5 AH6 U1-12 VCCO_64 VCCO_64 VCCO_64 BANK64 VREF_64 AA7 R35 1K IO_L1P_T0L_N0_DBC_64 IO_L1N_T0L_N1_DBC_64 IO_L2P_T0L_N2_64 IO_L2N_T0L_N3_64 IO_L3P_T0L_N4_AD15P_64 IO_L3N_T0L_N5_AD15N_64 IO_L4P_T0U_N6_DBC_AD7P_64 IO_L4N_T0U_N7_DBC_AD7N_64 IO_L5P_T0U_N8_AD14P_64 IO_L5N_T0U_N9_AD14N_64 IO_L6P_T0U_N10_AD6P_64 IO_L6N_T0U_N11_AD6N_64 IO_T0U_N12_VRP_64 IO_L7P_T1L_N0_QBC_AD13P_64 IO_L7N_T1L_N1_QBC_AD13N_64 IO_L8P_T1L_N2_AD5P_64 IO_L8N_T1L_N3_AD5N_64 IO_L9P_T1L_N4_AD12P_64 IO_L9N_T1L_N5_AD12N_64 IO_L10P_T1U_N6_QBC_AD4P_64 IO_L10N_T1U_N7_QBC_AD4N_64 IO_L11P_T1U_N8_GC_64 IO_L11N_T1U_N9_GC_64 IO_L12P_T1U_N10_GC_64 IO_L12N_T1U_N11_GC_64 IO_T1U_N12_64 IO_L13P_T2L_N0_GC_QBC_64 IO_L13N_T2L_N1_GC_QBC_64 IO_L14P_T2L_N2_GC_64 IO_L14N_T2L_N3_GC_64 IO_L15P_T2L_N4_AD11P_64 IO_L15N_T2L_N5_AD11N_64 IO_L16P_T2U_N6_QBC_AD3P_64 IO_L16N_T2U_N7_QBC_AD3N_64 IO_L17P_T2U_N8_AD10P_64 IO_L17N_T2U_N9_AD10N_64 IO_L18P_T2U_N10_AD2P_64 IO_L18N_T2U_N11_AD2N_64 IO_T2U_N12_64 IO_L19P_T3L_N0_DBC_AD9P_64 IO_L19N_T3L_N1_DBC_AD9N_64 IO_L20P_T3L_N2_AD1P_64 IO_L20N_T3L_N3_AD1N_64 IO_L21P_T3L_N4_AD8P_64 IO_L21N_T3L_N5_AD8N_64 IO_L22P_T3U_N6_DBC_AD0P_64 IO_L22N_T3U_N7_DBC_AD0N_64 IO_L23P_T3U_N8_64 IO_L23N_T3U_N9_64 IO_L24P_T3U_N10_64 IO_L24N_T3U_N11_64 IO_T3U_N12_64 XAZU3EG-SFVC784-1-I AD5 AD4 AC4 AC3 AB4 AB3 AD2 AD1 AB2 AC2 AB1 AC1 AB5 AG4 AH4 AG3 AH3 AE3 AF3 AE2 AF2 AH2 AH1 AF1 AG1 AE4 MIPI_CSI_CLKP MIPI_CSI_CLKN MIPI_CSI_DATA0P MIPI_CSI_DATA0N MIPI_CSI_DATA1P MIPI_CSI_DATA1N MIPI_CSI_DATA2P MIPI_CSI_DATA2N MIPI_CSI_DATA3P MIPI_CSI_DATA3N 21 MIPI_CSI_CLKP 21 MIPI_CSI_CLKN MIPI_CSI_DATA0P 21 MIPI_CSI_DATA0N 21 MIPI_CSI_DATA1P 21 MIPI_CSI_DATA1N 21 MIPI_CSI_DATA2P 21 MIPI_CSI_DATA2N 21 MIPI_CSI_DATA3P 21 MIPI_CSI_DATA3N 21 D C B A D C B A ALINX Confidential 5 4 3 Title Title Title Size Size Size PAGE05 Z7 Bank64 PAGE05 Z7 Bank64 PAGE05 Z7 Bank64 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 5 5 5 o f o f o f 23 23 23
    5 4 3 2 1 VCCAUX C25 47uF 21 21 CAM_PWDN# CAM_RST# CAM_PWDN# CAM_RST# R38 240 1% VRP_65 H5 J3 L4 W8 Y8 U9 V9 U8 V8 R8 T8 R7 T7 R6 T6 W9 L1 K1 J1 H1 K2 J2 H4 H3 K4 K3 L3 L2 H2 U1-13 VCCO_65 VCCO_65 VCCO_65 BANK65 VREF_65 R9 R37 1K IO_L1P_T0L_N0_DBC_65 IO_L1N_T0L_N1_DBC_65 IO_L2P_T0L_N2_65 IO_L2N_T0L_N3_65 IO_L3P_T0L_N4_AD15P_65 IO_L3N_T0L_N5_AD15N_65 IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 IO_L4N_T0U_N7_DBC_AD7N_65 IO_L5P_T0U_N8_AD14P_65 IO_L5N_T0U_N9_AD14N_65 IO_L6P_T0U_N10_AD6P_65 IO_L6N_T0U_N11_AD6N_65 IO_T0U_N12_VRP_65 IO_L7P_T1L_N0_QBC_AD13P_65 IO_L7N_T1L_N1_QBC_AD13N_65 IO_L8P_T1L_N2_AD5P_65 IO_L8N_T1L_N3_AD5N_65 IO_L9P_T1L_N4_AD12P_65 IO_L9N_T1L_N5_AD12N_65 IO_L10P_T1U_N6_QBC_AD4P_65 IO_L10N_T1U_N7_QBC_AD4N_65 IO_L11P_T1U_N8_GC_65 IO_L11N_T1U_N9_GC_65 IO_L12P_T1U_N10_GC_65 IO_L12N_T1U_N11_GC_65 IO_T1U_N12_65 IO_L13P_T2L_N0_GC_QBC_65 IO_L13N_T2L_N1_GC_QBC_65 IO_L14P_T2L_N2_GC_65 IO_L14N_T2L_N3_GC_65 IO_L15P_T2L_N4_AD11P_65 IO_L15N_T2L_N5_AD11N_65 IO_L16P_T2U_N6_QBC_AD3P_65 IO_L16N_T2U_N7_QBC_AD3N_65 IO_L17P_T2U_N8_AD10P_65 IO_L17N_T2U_N9_AD10N_65 IO_L18P_T2U_N10_AD2P_65 IO_L18N_T2U_N11_AD2N_65 IO_T2U_N12_65 IO_L19P_T3L_N0_DBC_AD9P_65 IO_L19N_T3L_N1_DBC_AD9N_65 IO_L20P_T3L_N2_AD1P_65 IO_L20N_T3L_N3_AD1N_65 IO_L21P_T3L_N4_AD8P_65 IO_L21N_T3L_N5_AD8N_65 IO_L22P_T3U_N6_DBC_AD0P_65 IO_L22N_T3U_N7_DBC_AD0N_65 IO_L23P_T3U_N8_I2C_SCLK_65 IO_L23N_T3U_N9_65 IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 IO_L24N_T3U_N11_PERSTN0_65 IO_T3U_N12_65 L7 L6 M6 L5 N7 N6 P7 P6 N9 N8 M8 L8 P9 J5 J4 J6 H6 J7 H7 K8 K7 K9 J9 H9 H8 K5 XAZU3EG-SFVC784-1-I CAM_MCLK CAM_MCLK 21 VCCAUX C26 47uF U1-14 E6 D3 VCCO_66 B7 VCCO_66 VCCO_66 BANK66 VREF_66 G9 R39 1K R40 240 1% VRP_66 PL_REF_CLK 20 PL_REF_CLK G1 F1 E1 D1 F2 E2 G3 F3 E4 E3 G5 F5 G4 C1 B1 A2 A1 B3 A3 B4 A4 D4 C4 C3 C2 D2 IO_L1P_T0L_N0_DBC_66 IO_L1N_T0L_N1_DBC_66 IO_L2P_T0L_N2_66 IO_L2N_T0L_N3_66 IO_L3P_T0L_N4_AD15P_66 IO_L3N_T0L_N5_AD15N_66 IO_L4P_T0U_N6_DBC_AD7P_66 IO_L4N_T0U_N7_DBC_AD7N_66 IO_L5P_T0U_N8_AD14P_66 IO_L5N_T0U_N9_AD14N_66 IO_L6P_T0U_N10_AD6P_66 IO_L6N_T0U_N11_AD6N_66 IO_T0U_N12_VRP_66 IO_L7P_T1L_N0_QBC_AD13P_66 IO_L7N_T1L_N1_QBC_AD13N_66 IO_L8P_T1L_N2_AD5P_66 IO_L8N_T1L_N3_AD5N_66 IO_L9P_T1L_N4_AD12P_66 IO_L9N_T1L_N5_AD12N_66 IO_L10P_T1U_N6_QBC_AD4P_66 IO_L10N_T1U_N7_QBC_AD4N_66 IO_L11P_T1U_N8_GC_66 IO_L11N_T1U_N9_GC_66 IO_L12P_T1U_N10_GC_66 IO_L12N_T1U_N11_GC_66 IO_T1U_N12_66 IO_L13P_T2L_N0_GC_QBC_66 IO_L13N_T2L_N1_GC_QBC_66 IO_L14P_T2L_N2_GC_66 IO_L14N_T2L_N3_GC_66 IO_L15P_T2L_N4_AD11P_66 IO_L15N_T2L_N5_AD11N_66 IO_L16P_T2U_N6_QBC_AD3P_66 IO_L16N_T2U_N7_QBC_AD3N_66 IO_L17P_T2U_N8_AD10P_66 IO_L17N_T2U_N9_AD10N_66 IO_L18P_T2U_N10_AD2P_66 IO_L18N_T2U_N11_AD2N_66 IO_T2U_N12_66 IO_L19P_T3L_N0_DBC_AD9P_66 IO_L19N_T3L_N1_DBC_AD9N_66 IO_L20P_T3L_N2_AD1P_66 IO_L20N_T3L_N3_AD1N_66 IO_L21P_T3L_N4_AD8P_66 IO_L21N_T3L_N5_AD8N_66 IO_L22P_T3U_N6_DBC_AD0P_66 IO_L22N_T3U_N7_DBC_AD0N_66 IO_L23P_T3U_N8_66 IO_L23N_T3U_N9_66 IO_L24P_T3U_N10_66 IO_L24N_T3U_N11_66 IO_T3U_N12_66 D7 D6 E5 D5 G6 F6 G8 F7 F8 E8 E9 D9 E7 B5 A5 C6 B6 A7 A6 C8 B8 A9 A8 C9 B9 C7 XAZU3EG-SFVC784-1-I D C B A D C B A ALINX Confidential 5 4 3 Title Title Title Size Size Size PAGE06 Z7 Bank65_66 PAGE06 Z7 Bank65_66 PAGE06 Z7 Bank65_66 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 6 6 6 o f o f o f 23 23 23
    5 4 3 2 1 505_PCIE_REFCLK_P 505_PCIE_REFCLK_N 505_USB_CLKP 505_USB_CLKN 505_DP_CLKP 505_DP_CLKN 505_PCIE_REFCLK_P 20 505_PCIE_REFCLK_N 20 505_USB_CLKP 20 505_USB_CLKN 20 505_DP_CLKP 20 505_DP_CLKN 20 PCIE_RXP PCIE_RXN USB_SSRXP USB_SSRXN PCIE_RXP 17 PCIE_RXN 17 USB_SSRXP 15 USB_SSRXN 15 D C B A U1-16 BANK505 PS MGT F23 F24 PS_MGTREFCLK0P_505 PS_MGTREFCLK0N_505 E21 E22 PS_MGTREFCLK1P_505 PS_MGTREFCLK1N_505 C21 C22 PS_MGTREFCLK2P_505 PS_MGTREFCLK2N_505 A21 A22 PS_MGTREFCLK3P_505 PS_MGTREFCLK3N_505 PS_MGTRREF_505 F22 R41 500 0.1% F27 F28 PS_MGTRRXP0_505 PS_MGTRRXN0_505 D27 D28 PS_MGTRRXP1_505 PS_MGTRRXN1_505 B27 B28 PS_MGTRRXP2_505 PS_MGTRRXN2_505 A25 A26 PS_MGTRRXP3_505 PS_MGTRRXN3_505 PS_MGTRTXP0_505 PS_MGTRTXN0_505 PS_MGTRTXP1_505 PS_MGTRTXN1_505 PS_MGTRTXP2_505 PS_MGTRTXN2_505 PS_MGTRTXP3_505 PS_MGTRTXN3_505 E25 E26 D23 D24 C25 C26 B23 B24 XAZU3EG-SFVC784-1-I PCIE_TXP PCIE_TXN USB_SSTXP USB_SSTXN GT1_DP_TX_P GT1_DP_TX_N GT0_DP_TX_P GT0_DP_TX_N PCIE_TXP PCIE_TXN USB_SSTXP USB_SSTXN GT1_DP_TX_P GT1_DP_TX_N GT0_DP_TX_P GT0_DP_TX_N 17 17 15 15 16 16 16 16 U1-15 NC1 NC2 NC3 NC4 V4 Y4 U5 W5 Y6 Y5 NC5 NC6 V6 V5 NC7 NC8 Y2 Y1 NC9 NC10 V2 V1 NC11 NC12 T2 NC13 T1 NC14 P2 P1 NC15 NC16 BANK224 MGT T4 P4 N1 N2 W4 W3 U4 U3 R4 R3 N4 N3 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 XAZU3EG-SFVC784-1-I D C B A ALINX Confidential 5 4 3 Title Title Title Size Size Size PAGE07 Z7 Bank505 PAGE07 Z7 Bank505 PAGE07 Z7 Bank505 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 7 7 7 o f o f o f 23 23 23
    5 DDR_1V2 1.2V C27 100uF C29 4.7uF C30 4.7uF C31 470nF C36 470nF C32 470nF C33 470nF 1.8V VCC_PSAUX VCC_PS_DDR_PLL 0.85V VCC_PSINTFP L5 BLM18SG121TN1 C34 10uF C35 470nF C37 100uF C38 4.7uF C40 470nF 4 1.2V DDR_1V2 U1-6 AB22 AD23 AF24 P23 T24 V25 Y26 U16 U18 AA20 AA21 Y19 VCCO_PSDDR_504 VCCO_PSDDR_504 VCCO_PSDDR_504 VCCO_PSDDR_504 VCCO_PSDDR_504 VCCO_PSDDR_504 VCCO_PSDDR_504 VCC_PSDDR_PLL VCC_PSDDR_PLL VCC_PSINTFP_DDR VCC_PSINTFP_DDR VCC_PSINTFP_DDR 3 BANK504 PS_DDR_CK0_504 PS_DDR_CK_N0_504 PS_DDR_CKE0_504 PS_DDR_CK1_504 PS_DDR_CK_N1_504 PS_DDR_CKE1_504 PS_DDR_A0_504 PS_DDR_A1_504 PS_DDR_A2_504 PS_DDR_A3_504 PS_DDR_A4_504 PS_DDR_A5_504 PS_DDR_A6_504 PS_DDR_A7_504 PS_DDR_A8_504 PS_DDR_A9_504 PS_DDR_A10_504 PS_DDR_A11_504 PS_DDR_A12_504 PS_DDR_A13_504 PS_DDR_A14_504 PS_DDR_A15_504 PS_DDR_A16_504 PS_DDR_A17_504 PS_DDR_CS_N0_504 PS_DDR_CS_N1_504 PS_DDR_BA0_504 PS_DDR_BA1_504 PS_DDR_BG0_504 PS_DDR_BG1_504 PS_DDR_PARITY_504 PS_DDR_RAM_RST_N_504 PS_DDR_ACT_N_504 PS_DDR_ALERT_N_504 PS_DDR_ZQ_504 PS_DDR_ODT0_504 PS_DDR_ODT1_504 2 1 W25 W26 V28 Y24 Y25 V27 W28 Y28 AB28 AA28 Y27 AA27 Y22 AA23 AA22 AB23 AA25 AA26 AB25 AB26 AB24 AC24 AC23 AC22 W27 V26 V23 W22 W24 V22 V24 U23 Y23 U25 U24 U28 U26 PS_DDR4_CLK0_P PS_DDR4_CLK0_N PS_DDR4_CKE0 PS_DDR4_CLK0_P10,11,12,13 PS_DDR4_CLK0_N10,11,12,13 PS_DDR4_CKE0 10,11,12,13 PS_DDR4_A0 PS_DDR4_A1 PS_DDR4_A2 PS_DDR4_A3 PS_DDR4_A4 PS_DDR4_A5 PS_DDR4_A6 PS_DDR4_A7 PS_DDR4_A8 PS_DDR4_A9 PS_DDR4_A10 PS_DDR4_A11 PS_DDR4_A12 PS_DDR4_A13 PS_DDR4_WE_B PS_DDR4_CAS_B PS_DDR4_RAS_B PS_DDR4_CS0_B PS_DDR4_BA0 PS_DDR4_BA1 PS_DDR4_BG0 PS_DDR4_PARITY PS_DDR4_RESET_B PS_DDR4_ACT_B PS_DDR4_ALERT_B 10,11,12,13 PS_DDR4_A0 10,11,12,13 PS_DDR4_A1 10,11,12,13 PS_DDR4_A2 10,11,12,13 PS_DDR4_A3 10,11,12,13 PS_DDR4_A4 10,11,12,13 PS_DDR4_A5 10,11,12,13 PS_DDR4_A6 10,11,12,13 PS_DDR4_A7 10,11,12,13 PS_DDR4_A8 10,11,12,13 PS_DDR4_A9 10,11,12,13 PS_DDR4_A10 10,11,12,13 PS_DDR4_A11 10,11,12,13 PS_DDR4_A12 10,11,12,13 PS_DDR4_A13 PS_DDR4_WE_B 10,11,12,13 PS_DDR4_CAS_B 10,11,12,13 PS_DDR4_RAS_B 10,11,12,13 PS_DDR4_CS0_B 10,11,12,13 PS_DDR4_BA0 PS_DDR4_BA1 PS_DDR4_BG0 10,11,12,13 10,11,12,13 10,11,12,13 PS_DDR4_PARITY10,11,12,13 PS_DDR4_RESET_B10,11,12,13 PS_DDR4_ACT_B 10,11,12,13 PS_DDR4_ALERT_B10,11,12,13 PS_DDR4_ZQ R42 240 1% PS_DDR4_ODT0 PS_DDR4_ODT0 10,11,12,13 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 PS_DDR4_DQ0 PS_DDR4_DQ1 PS_DDR4_DQ2 PS_DDR4_DQ3 PS_DDR4_DQ4 PS_DDR4_DQ5 PS_DDR4_DQ6 PS_DDR4_DQ7 PS_DDR4_DQ8 PS_DDR4_DQ9 PS_DDR4_DQ10 PS_DDR4_DQ11 PS_DDR4_DQ12 PS_DDR4_DQ13 PS_DDR4_DQ14 PS_DDR4_DQ15 PS_DDR4_DQ16 PS_DDR4_DQ17 PS_DDR4_DQ18 PS_DDR4_DQ19 PS_DDR4_DQ20 PS_DDR4_DQ21 PS_DDR4_DQ22 PS_DDR4_DQ23 PS_DDR4_DQ24 PS_DDR4_DQ25 PS_DDR4_DQ26 PS_DDR4_DQ27 PS_DDR4_DQ28 PS_DDR4_DQ29 PS_DDR4_DQ30 PS_DDR4_DQ31 10 PS_DDR4_DQS0_P 10 PS_DDR4_DQS0_N 10 PS_DDR4_DQS1_P 10 PS_DDR4_DQS1_N 11 PS_DDR4_DQS2_P 11 PS_DDR4_DQS2_N 11 PS_DDR4_DQS3_P 11 PS_DDR4_DQS3_N 12 PS_DDR4_DQS4_P 12 PS_DDR4_DQS4_N 12 PS_DDR4_DQS5_P 12 PS_DDR4_DQS5_N 13 PS_DDR4_DQS6_P 13 PS_DDR4_DQS6_N 13 PS_DDR4_DQS7_P 13 PS_DDR4_DQS7_N PS_DDR4_DQ0 PS_DDR4_DQ1 PS_DDR4_DQ2 PS_DDR4_DQ3 PS_DDR4_DQ4 PS_DDR4_DQ5 PS_DDR4_DQ6 PS_DDR4_DQ7 PS_DDR4_DQ8 PS_DDR4_DQ9 PS_DDR4_DQ10 PS_DDR4_DQ11 PS_DDR4_DQ12 PS_DDR4_DQ13 PS_DDR4_DQ14 PS_DDR4_DQ15 PS_DDR4_DQ16 PS_DDR4_DQ17 PS_DDR4_DQ18 PS_DDR4_DQ19 PS_DDR4_DQ20 PS_DDR4_DQ21 PS_DDR4_DQ22 PS_DDR4_DQ23 PS_DDR4_DQ24 PS_DDR4_DQ25 PS_DDR4_DQ26 PS_DDR4_DQ27 PS_DDR4_DQ28 PS_DDR4_DQ29 PS_DDR4_DQ30 PS_DDR4_DQ31 PS_DDR4_DQS0_P PS_DDR4_DQS0_N PS_DDR4_DQS1_P PS_DDR4_DQS1_N PS_DDR4_DQS2_P PS_DDR4_DQS2_N PS_DDR4_DQS3_P PS_DDR4_DQS3_N PS_DDR4_DQS4_P PS_DDR4_DQS4_N PS_DDR4_DQS5_P PS_DDR4_DQS5_N PS_DDR4_DQS6_P PS_DDR4_DQS6_N PS_DDR4_DQS7_P PS_DDR4_DQS7_N U1-7 PS_DDR_DQ0_504 PS_DDR_DQ1_504 PS_DDR_DQ2_504 PS_DDR_DQ3_504 PS_DDR_DQ4_504 PS_DDR_DQ5_504 PS_DDR_DQ6_504 PS_DDR_DQ7_504 PS_DDR_DQ8_504 PS_DDR_DQ9_504 PS_DDR_DQ10_504 PS_DDR_DQ11_504 PS_DDR_DQ12_504 PS_DDR_DQ13_504 PS_DDR_DQ14_504 PS_DDR_DQ15_504 PS_DDR_DQ16_504 PS_DDR_DQ17_504 PS_DDR_DQ18_504 PS_DDR_DQ19_504 PS_DDR_DQ20_504 PS_DDR_DQ21_504 PS_DDR_DQ22_504 PS_DDR_DQ23_504 PS_DDR_DQ24_504 PS_DDR_DQ25_504 PS_DDR_DQ26_504 PS_DDR_DQ27_504 PS_DDR_DQ28_504 PS_DDR_DQ29_504 PS_DDR_DQ30_504 PS_DDR_DQ31_504 PS_DDR_DQS_P0_504 PS_DDR_DQS_N0_504 PS_DDR_DQS_P1_504 PS_DDR_DQS_N1_504 PS_DDR_DQS_P2_504 PS_DDR_DQS_N2_504 PS_DDR_DQS_P3_504 PS_DDR_DQS_N3_504 PS_DDR_DQS_P4_504 PS_DDR_DQS_N4_504 PS_DDR_DQS_P5_504 PS_DDR_DQS_N5_504 PS_DDR_DQS_P6_504 PS_DDR_DQS_N6_504 PS_DDR_DQS_P7_504 PS_DDR_DQS_N7_504 PS_DDR_DQS_P8_504 PS_DDR_DQS_N8_504 AD21 AE20 AD20 AF20 AH21 AH20 AH19 AG19 AF22 AH22 AE22 AD22 AH23 AH24 AE24 AG24 AC26 AD26 AD25 AD24 AG26 AH25 AH26 AG25 AH27 AH28 AF28 AG28 AC27 AD27 AD28 AC28 AF21 AG21 AF23 AG23 AF25 AF26 AE27 AF27 N23 M23 L23 K23 N26 N27 J26 J27 R27 T27 XAZU3EG-SFVC784-1-I BANK504 PS_DDR_DQ32_504 PS_DDR_DQ33_504 PS_DDR_DQ34_504 PS_DDR_DQ35_504 PS_DDR_DQ36_504 PS_DDR_DQ37_504 PS_DDR_DQ38_504 PS_DDR_DQ39_504 PS_DDR_DQ40_504 PS_DDR_DQ41_504 PS_DDR_DQ42_504 PS_DDR_DQ43_504 PS_DDR_DQ44_504 PS_DDR_DQ45_504 PS_DDR_DQ46_504 PS_DDR_DQ47_504 PS_DDR_DQ48_504 PS_DDR_DQ49_504 PS_DDR_DQ50_504 PS_DDR_DQ51_504 PS_DDR_DQ52_504 PS_DDR_DQ53_504 PS_DDR_DQ54_504 PS_DDR_DQ55_504 PS_DDR_DQ56_504 PS_DDR_DQ57_504 PS_DDR_DQ58_504 PS_DDR_DQ59_504 PS_DDR_DQ60_504 PS_DDR_DQ61_504 PS_DDR_DQ62_504 PS_DDR_DQ63_504 PS_DDR_DQ64_504 PS_DDR_DQ65_504 PS_DDR_DQ66_504 PS_DDR_DQ67_504 PS_DDR_DQ68_504 PS_DDR_DQ69_504 PS_DDR_DQ70_504 PS_DDR_DQ71_504 PS_DDR_DM0_504 PS_DDR_DM1_504 PS_DDR_DM2_504 PS_DDR_DM3_504 PS_DDR_DM4_504 PS_DDR_DM5_504 PS_DDR_DM6_504 PS_DDR_DM7_504 PS_DDR_DM8_504 PS_DDR4_DQ32 PS_DDR4_DQ33 PS_DDR4_DQ34 PS_DDR4_DQ35 PS_DDR4_DQ36 PS_DDR4_DQ37 PS_DDR4_DQ38 PS_DDR4_DQ39 PS_DDR4_DQ40 PS_DDR4_DQ41 PS_DDR4_DQ42 PS_DDR4_DQ43 PS_DDR4_DQ44 PS_DDR4_DQ45 PS_DDR4_DQ46 PS_DDR4_DQ47 PS_DDR4_DQ48 PS_DDR4_DQ49 PS_DDR4_DQ50 PS_DDR4_DQ51 PS_DDR4_DQ52 PS_DDR4_DQ53 PS_DDR4_DQ54 PS_DDR4_DQ55 PS_DDR4_DQ56 PS_DDR4_DQ57 PS_DDR4_DQ58 PS_DDR4_DQ59 PS_DDR4_DQ60 PS_DDR4_DQ61 PS_DDR4_DQ62 PS_DDR4_DQ63 PS_DDR4_DQ32 12 PS_DDR4_DQ33 12 PS_DDR4_DQ34 12 PS_DDR4_DQ35 12 PS_DDR4_DQ36 12 PS_DDR4_DQ37 12 PS_DDR4_DQ38 12 PS_DDR4_DQ39 12 PS_DDR4_DQ40 12 PS_DDR4_DQ41 12 PS_DDR4_DQ42 12 PS_DDR4_DQ43 12 PS_DDR4_DQ44 12 PS_DDR4_DQ45 12 PS_DDR4_DQ46 12 PS_DDR4_DQ47 12 PS_DDR4_DQ48 13 PS_DDR4_DQ49 13 PS_DDR4_DQ50 13 PS_DDR4_DQ51 13 PS_DDR4_DQ52 13 PS_DDR4_DQ53 13 PS_DDR4_DQ54 13 PS_DDR4_DQ55 13 PS_DDR4_DQ56 13 PS_DDR4_DQ57 13 PS_DDR4_DQ58 13 PS_DDR4_DQ59 13 PS_DDR4_DQ60 13 PS_DDR4_DQ61 13 PS_DDR4_DQ62 13 PS_DDR4_DQ63 13 T22 R22 P22 N22 T23 P24 R24 N24 H24 J24 M24 K24 J22 H22 K22 L22 M25 M26 L25 L26 K28 L28 M28 N28 J28 K27 H28 H27 G26 G25 K25 J25 T28 R28 P28 P27 P26 R25 P25 T25 PS_DDR4_DM0 PS_DDR4_DM1 PS_DDR4_DM2 PS_DDR4_DM3 PS_DDR4_DM4 PS_DDR4_DM5 PS_DDR4_DM6 PS_DDR4_DM7 AG20 AE23 AE25 AE28 R23 H23 L27 H26 T26 PS_DDR4_DM0 PS_DDR4_DM1 PS_DDR4_DM2 PS_DDR4_DM3 PS_DDR4_DM4 PS_DDR4_DM5 PS_DDR4_DM6 PS_DDR4_DM7 10 10 11 11 12 12 13 13 ALINX Confidential XAZU3EG-SFVC784-1-I 5 4 3 Title Title Title Size Size Size PAGE08 Z7 Bank504 PAGE08 Z7 Bank504 PAGE08 Z7 Bank504 Document Number Document Number Document Number FZ3B开发板 Schematics FZ3B开发板 Schematics FZ3B开发板 Schematics www.alinx.com Rev Rev Rev 1.0 1.0 1.0 2 Date: Date: Date: Wednesday, April 08, 2020 Wednesday, April 08, 2020 Wednesday, April 08, 2020 Sheet Sheet Sheet 1 8 8 8 o f o f o f 25 25 25 D C B A D C B A
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