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STM32G0x0单片机参考手册.pdf
1 Documentation conventions
1.1 General information
1.2 List of abbreviations for registers
1.3 Glossary
1.4 Availability of peripherals
Table 1. Peripherals versus products
2 Memory and bus architecture
2.1 System architecture
Figure 1. System architecture
2.2 Memory organization
2.2.1 Introduction
2.2.2 Memory map and register boundary addresses
Figure 2. Memory map
Table 2. STM32G070xx memory boundary addresses
Table 3. STM32G030xx memory boundary addresses
Table 4. STM32G0x0 peripheral register boundary addresses
2.3 Embedded SRAM
2.4 Flash memory overview
2.5 Boot configuration
Table 5. Boot modes
3 Embedded Flash memory (FLASH)
3.1 FLASH Introduction
3.2 FLASH main features
3.3 FLASH functional description
3.3.1 FLASH memory organization
Table 6. Flash memory organization
3.3.2 FLASH empty check
3.3.3 FLASH error code correction (ECC)
3.3.4 FLASH read access latency
Table 7. Number of wait states according to Flash memory clock (HCLK) frequency
3.3.5 FLASH memory acceleration
3.3.6 FLASH program and erase operations
3.3.7 FLASH Main memory erase sequences
3.3.8 FLASH Main memory programming sequences
3.4 FLASH option bytes
3.4.1 FLASH option byte description
Table 8. Option byte format
Table 9. Organization of option bytes
3.4.2 FLASH option byte programming
3.5 FLASH memory protection
3.5.1 FLASH read protection (RDP)
Table 10. Flash memory read protection status
Figure 3. Changing read protection (RDP) level
Table 11. Access status versus protection level and execution modes
3.5.2 FLASH write protection (WRP)
3.6 FLASH interrupts
Table 13. FLASH interrupt requests
3.7 FLASH registers
3.7.1 FLASH access control register (FLASH_ACR)
3.7.2 FLASH key register (FLASH_KEYR)
3.7.3 FLASH option key register (FLASH_OPTKEYR)
3.7.4 FLASH status register (FLASH_SR)
3.7.5 FLASH control register (FLASH_CR)
3.7.6 FLASH ECC register (FLASH_ECCR)
3.7.7 FLASH option register (FLASH_OPTR)
3.7.8 FLASH WRP area A address register (FLASH_WRP1AR)
3.7.9 FLASH WRP area B address register (FLASH_WRP1BR)
3.7.10 FLASH register map
Table 14. FLASH register map and reset values
4 Power control (PWR)
4.1 Power supplies
Figure 4. Power supply overview
4.1.1 ADC reference voltage
4.1.2 Battery backup of RTC domain
4.1.3 Voltage regulator
4.1.4 Dynamic voltage scaling management
4.2 Power supply supervisor
4.2.1 Power-on reset (POR) / power-down reset (PDR)
Figure 5. POR, PDR thresholds
4.3 Low-power modes
Figure 6. Low-power modes state diagram
Table 15. Low-power mode summary
Table 16. Functionalities depending on the working mode
4.3.1 Run mode
4.3.2 Low-power run mode (LP run)
Table 17. Low-power run
4.3.3 Low-power modes
4.3.4 Sleep mode
Table 18. Sleep mode summary
4.3.5 Low-power sleep mode (LP sleep)
Table 19. Low-power sleep mode summary
4.3.6 Stop 0 mode
Table 20. Stop 0 mode summary
4.3.7 Stop 1 mode
Table 21. Stop 1 mode summary
4.3.8 Standby mode
Table 22. Standby mode summary
4.3.9 Auto-wakeup from low-power mode
4.4 PWR registers
4.4.1 Power control register 1 (PWR_CR1)
4.4.2 Power control register 3 (PWR_CR3)
4.4.3 Power control register 4 (PWR_CR4)
4.4.4 Power status register 1 (PWR_SR1)
4.4.5 Power status register 2 (PWR_SR2)
4.4.6 Power status clear register (PWR_SCR)
4.4.7 Power Port A pull-up control register (PWR_PUCRA)
4.4.8 Power Port A pull-down control register (PWR_PDCRA)
4.4.9 Power Port B pull-up control register (PWR_PUCRB)
4.4.10 Power Port B pull-down control register (PWR_PDCRB)
4.4.11 Power Port C pull-up control register (PWR_PUCRC)
4.4.12 Power Port C pull-down control register (PWR_PDCRC)
4.4.13 Power Port D pull-up control register (PWR_PUCRD)
4.4.14 Power Port D pull-down control register (PWR_PDCRD)
4.4.15 Power Port F pull-up control register (PWR_PUCRF)
4.4.16 Power Port F pull-down control register (PWR_PDCRF)
4.4.17 PWR register map and reset value table
Table 23. PWR register map and reset values
5 Reset and clock control (RCC)
5.1 Reset
5.1.1 Power reset
5.1.2 System reset
Figure 7. Simplified diagram of the reset circuit
5.1.3 RTC domain reset
5.2 Clocks
Figure 8. Clock tree
5.2.1 HSE clock
Figure 9. HSE/ LSE clock sources
5.2.2 HSI16 clock
5.2.3 PLL
5.2.4 LSE clock
5.2.5 LSI clock
5.2.6 System clock (SYSCLK) selection
5.2.7 Clock source frequency versus voltage scaling
Table 24. Clock source frequency
5.2.8 Clock security system (CSS)
5.2.9 Clock security system for LSE clock (LSECSS)
5.2.10 ADC clock
5.2.11 RTC clock
5.2.12 Timer clock
5.2.13 Watchdog clock
5.2.14 Clock-out capability
5.2.15 Internal/external clock measurement with TIM14/TIM16/TIM17
Figure 10. Frequency measurement with TIM14 in capture mode
Figure 11. Frequency measurement with TIM16 in capture mode
Figure 12. Frequency measurement with TIM17 in capture mode
5.2.16 Peripheral clock enable registers
5.3 Low-power modes
5.4 RCC registers
5.4.1 Clock control register (RCC_CR)
5.4.2 Internal clock sources calibration register (RCC_ICSCR)
5.4.3 Clock configuration register (RCC_CFGR)
5.4.4 PLL configuration register (RCC_PLLCFGR)
5.4.5 Clock interrupt enable register (RCC_CIER)
5.4.6 Clock interrupt flag register (RCC_CIFR)
5.4.7 Clock interrupt clear register (RCC_CICR)
5.4.8 I/O port reset register (RCC_IOPRSTR)
5.4.9 AHB peripheral reset register (RCC_AHBRSTR)
5.4.10 APB peripheral reset register 1 (RCC_APBRSTR1)
5.4.11 APB peripheral reset register 2 (RCC_APBRSTR2)
5.4.12 I/O port clock enable register (RCC_IOPENR)
5.4.13 AHB peripheral clock enable register (RCC_AHBENR)
5.4.14 APB peripheral clock enable register 1 (RCC_APBENR1)
5.4.15 APB peripheral clock enable register 2(RCC_APBENR2)
5.4.16 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)
5.4.17 AHB peripheral clock enable in Sleep/Stop mode register (RCC_AHBSMENR)
5.4.18 APB peripheral clock enable in Sleep/Stop mode register 1 (RCC_APBSMENR1)
5.4.19 APB peripheral clock enable in Sleep/Stop mode register 2 (RCC_APBSMENR2)
5.4.20 Peripherals independent clock configuration register (RCC_CCIPR)
5.4.21 RTC domain control register (RCC_BDCR)
5.4.22 Control/status register (RCC_CSR)
5.4.23 RCC register map
Table 25. RCC register map and reset values
6 General-purpose I/Os (GPIO)
6.1 Introduction
6.2 GPIO main features
6.3 GPIO functional description
Table 26. Port bit configuration table
6.3.1 General-purpose I/O (GPIO)
6.3.2 I/O pin alternate function multiplexer and mapping
6.3.3 I/O port control registers
6.3.4 I/O port data registers
6.3.5 I/O data bitwise handling
6.3.6 GPIO locking mechanism
6.3.7 I/O alternate function input/output
6.3.8 External interrupt/wakeup lines
6.3.9 Input configuration
6.3.10 Output configuration
6.3.11 Alternate function configuration
6.3.12 Analog configuration
6.3.13 Using the HSE or LSE oscillator pins as GPIOs
6.3.14 Using the GPIO pins in the RTC domain
6.3.15 USB PD / Dead battery support
6.4 GPIO registers
6.4.1 GPIO port mode register (GPIOx_MODER) (x =A to D, F)
6.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to D, F)
6.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to D, F)
6.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to D, F)
6.4.5 GPIO port input data register (GPIOx_IDR) (x = A to D, F)
6.4.6 GPIO port output data register (GPIOx_ODR) (x = A to D, F)
6.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to D, F)
6.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to D, F)
6.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to D, F)
6.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to D, F)
6.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D, F)
6.4.12 GPIO register map
Table 27. GPIO register map and reset values
7 System configuration controller (SYSCFG)
7.1 SYSCFG registers
7.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)
7.1.2 SYSCFG configuration register 2 (SYSCFG_CFGR2)
7.1.3 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)
7.1.4 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)
7.1.5 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)
7.1.6 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)
7.1.7 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)
7.1.8 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)
7.1.9 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)
7.1.10 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)
7.1.11 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)
7.1.12 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)
7.1.13 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)
7.1.14 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)
7.1.15 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)
7.1.16 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)
7.1.17 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)
7.1.18 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)
7.1.19 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)
7.1.20 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)
7.1.21 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)
7.1.22 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)
7.1.23 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)
7.1.24 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)
7.1.25 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
7.1.26 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
7.1.27 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
7.1.28 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)
7.1.29 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)
7.1.30 SYSCFG register map
Table 28. SYSCFG register map and reset values
8 Interconnect matrix
8.1 Introduction
8.2 Connection summary
Table 29. Interconnect matrix
8.3 Interconnection details
8.3.1 From TIM1, TIM3, TIM15, TIM16, and TIM17, to TIM1, TIM3, and TIM15
8.3.2 From TIM1, TIM3, TIM6, TIM15, and EXTI, to ADC
8.3.3 From ADC to TIM1
8.3.4 From HSE, LSE, LSI, MCO, RTC and TAMP, to TIM14, TIM16, and TIM17
8.3.5 From internal analog sources to ADC
8.3.6 From system errors to TIM1, TIM3, TIM15, TIM16, and TIM17
8.3.7 From TIM16, TIM17, USART1, and USART4, to IRTIM
8.3.8 From TIM14 to DMAMUX
9 Direct memory access controller (DMA)
9.1 Introduction
9.2 DMA main features
9.3 DMA implementation
9.3.1 DMA
Table 30. DMA implementation
9.3.2 DMA request mapping
9.4 DMA functional description
9.4.1 DMA block diagram
9.4.2 DMA pins and internal signals
Table 31. DMA internal input/output signals
9.4.3 DMA transfers
9.4.4 DMA arbitration
9.4.5 DMA channels
Programmable data sizes
Pointer incrementation
Channel configuration procedure
Channel state and disabling a channel
Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)
Memory-to-memory mode
Peripheral-to-peripheral mode
Programming transfer direction, assigning source/destination
9.4.6 DMA data width, alignment and endianness
Table 32. Programmable data width and endian behavior (when PINC = MINC = 1)
Addressing AHB peripherals not supporting byte/half-word write transfers
9.4.7 DMA error management
9.5 DMA interrupts
Table 33. DMA interrupt requests
9.6 DMA registers
9.6.1 DMA interrupt status register (DMA_ISR)
9.6.2 DMA interrupt flag clear register (DMA_IFCR)
9.6.3 DMA channel x configuration register (DMA_CCRx)
9.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
9.6.5 DMA channel x peripheral address register (DMA_CPARx)
9.6.6 DMA channel x memory address register (DMA_CMARx)
9.6.7 DMA register map and reset values
Table 34. DMA register map and reset values
10 DMA request multiplexer (DMAMUX)
10.1 Introduction
10.2 DMAMUX main features
10.3 DMAMUX implementation
10.3.1 DMAMUX instantiation
Table 35. DMAMUX instantiation
10.3.2 DMAMUX mapping
Table 36. DMAMUX: assignment of multiplexer inputs to resources
Table 37. DMAMUX: assignment of trigger inputs to resources
Table 38. DMAMUX: assignment of synchronization inputs to resources
10.4 DMAMUX functional description
10.4.1 DMAMUX block diagram
10.4.2 DMAMUX signals
Table 39. DMAMUX signals
10.4.3 DMAMUX channels
Channel configuration procedure
10.4.4 DMAMUX request line multiplexer
Synchronization mode and channel event generation
Synchronization overrun and interrupt
10.4.5 DMAMUX request generator
Trigger overrun and interrupt
10.5 DMAMUX interrupts
Table 40. DMAMUX interrupts
10.6 DMAMUX registers
10.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
10.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR)
10.6.3 DMAMUX request line multiplexer interrupt clear flag register (DMAMUX_CFR)
10.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR)
10.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR)
10.6.6 DMAMUX request generator interrupt clear flag register (DMAMUX_RGCFR)
10.6.7 DMAMUX register map
Table 41. DMAMUX register map and reset values
11 Nested vectored interrupt controller (NVIC)
11.1 Main features
11.2 SysTick calibration value register
11.3 Interrupt and exception vectors
12 Extended interrupt and event controller (EXTI)
12.1 EXTI main features
12.2 EXTI block diagram
Figure 22. EXTI block diagram
Table 43. EXTI signal overview
Table 44. EVG pin overview
12.2.1 EXTI connections between peripherals and CPU
12.3 EXTI functional description
Table 45. EXTI event input configurations and register control
12.3.1 EXTI configurable event input wakeup
Figure 23. Configurable event trigger logic CPU wakeup
12.3.2 EXTI direct event input wakeup
Figure 24. Direct event trigger logic CPU wakeup
12.3.3 EXTI mux
Figure 25. EXTI GPIO mux
Table 46. EXTI line connections
12.4 EXTI functional behavior
Table 47. Masking functionality
12.5 EXTI registers
Table 48. EXTI register map sections
12.5.1 EXTI rising trigger selection register (EXTI_RTSR1)
12.5.2 EXTI falling trigger selection register (EXTI_FTSR1)
12.5.3 EXTI software interrupt event register (EXTI_SWIER1)
12.5.4 EXTI rising edge pending register (EXTI_RPR1)
12.5.5 EXTI falling edge pending register (EXTI_FPR1)
12.5.6 EXTI external interrupt selection register (EXTI_EXTICRx)
12.5.7 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)
12.5.8 EXTI CPU wakeup with event mask register (EXTI_EMR1)
12.5.9 EXTI register map
Table 49. EXTI controller register map and reset values
13 Cyclic redundancy check calculation unit (CRC)
13.1 Introduction
13.2 CRC main features
13.3 CRC functional description
13.3.1 CRC block diagram
13.3.2 CRC internal signals
Table 50. CRC internal input/output signals
13.3.3 CRC operation
Polynomial programmability
13.4 CRC registers
13.4.1 CRC data register (CRC_DR)
13.4.2 CRC independent data register (CRC_IDR)
13.4.3 CRC control register (CRC_CR)
13.4.4 CRC initial value (CRC_INIT)
13.4.5 CRC polynomial (CRC_POL)
13.4.6 CRC register map
Table 51. CRC register map and reset values
14 Analog-to-digital converter (ADC)
14.1 Introduction
14.2 ADC main features
14.3 ADC functional description
14.3.1 ADC pins and internal signals
14.3.2 ADC voltage regulator (ADVREGEN)
14.3.3 Calibration (ADCAL)
14.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)
14.3.5 ADC clock (CKMODE, PRESC[3:0])
14.3.6 ADC connectivity
14.3.7 Configuring the ADC
14.3.8 Channel selection (CHSEL, SCANDIR, CHSELRMOD)
14.3.9 Programmable sampling time (SMPx[2:0])
14.3.10 Single conversion mode (CONT=0)
14.3.11 Continuous conversion mode (CONT=1)
14.3.12 Starting conversions (ADSTART)
14.3.13 Timings
14.3.14 Stopping an ongoing conversion (ADSTP)
14.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)
14.4.1 Discontinuous mode (DISCEN)
14.4.2 Programmable resolution (RES) - fast conversion mode
14.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)
14.4.4 End of conversion sequence (EOS flag)
14.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)
14.4.6 Low frequency trigger mode
14.5 Data management
14.5.1 Data register and data alignment (ADC_DR, ALIGN)
14.5.2 ADC overrun (OVR, OVRMOD)
14.5.3 Managing a sequence of data converted without using the DMA
14.5.4 Managing converted data without using the DMA without overrun
14.5.5 Managing converted data using the DMA
14.6 Low-power features
14.6.1 Wait mode conversion
14.6.2 Auto-off mode (AUTOFF)
14.7 Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR, ADC_AWDxTR)
14.7.1 Description of analog watchdog 1
14.7.2 Description of analog watchdog 2 and 3
14.7.3 ADC_AWDx_OUT signal output generation
14.7.4 Analog Watchdog threshold control
14.8 Oversampler
14.8.1 ADC operating modes supported when oversampling
14.8.2 Analog watchdog
14.8.3 Triggered mode
14.9 Temperature sensor and internal reference voltage
14.10 Battery voltage monitoring
14.11 ADC interrupts
14.12 ADC registers
14.12.1 ADC interrupt and status register (ADC_ISR)
14.12.2 ADC interrupt enable register (ADC_IER)
14.12.3 ADC control register (ADC_CR)
14.12.4 ADC configuration register 1 (ADC_CFGR1)
14.12.5 ADC configuration register 2 (ADC_CFGR2)
14.12.6 ADC sampling time register (ADC_SMPR)
14.12.7 ADC watchdog threshold register (ADC_AWD1TR)
14.12.8 ADC watchdog threshold register (ADC_AWD2TR)
14.12.9 ADC channel selection register [alternate] (ADC_CHSELR)
14.12.10 ADC channel selection register [alternate] (ADC_CHSELR)
14.12.11 ADC watchdog threshold register (ADC_AWD3TR)
14.12.12 ADC data register (ADC_DR)
14.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)
14.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)
14.12.15 ADC Calibration factor (ADC_CALFACT)
14.12.16 ADC common configuration register (ADC_CCR)
14.12.17 ADC register map
15 Advanced-control timers (TIM1)
15.1 TIM1 introduction
15.2 TIM1 main features
Figure 55. Advanced-control timer block diagram
15.3 TIM1 functional description
15.3.1 Time-base unit
Figure 56. Counter timing diagram with prescaler division change from 1 to 2
Figure 57. Counter timing diagram with prescaler division change from 1 to 4
15.3.2 Counter modes
Figure 58. Counter timing diagram, internal clock divided by 1
Figure 59. Counter timing diagram, internal clock divided by 2
Figure 60. Counter timing diagram, internal clock divided by 4
Figure 61. Counter timing diagram, internal clock divided by N
Figure 62. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
Figure 63. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
Figure 64. Counter timing diagram, internal clock divided by 1
Figure 65. Counter timing diagram, internal clock divided by 2
Figure 66. Counter timing diagram, internal clock divided by 4
Figure 67. Counter timing diagram, internal clock divided by N
Figure 68. Counter timing diagram, update event when repetition counter is not used
Figure 69. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6
Figure 70. Counter timing diagram, internal clock divided by 2
Figure 71. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
Figure 72. Counter timing diagram, internal clock divided by N
Figure 73. Counter timing diagram, update event with ARPE=1 (counter underflow)
Figure 74. Counter timing diagram, Update event with ARPE=1 (counter overflow)
15.3.3 Repetition counter
Figure 75. Update rate examples depending on mode and TIMx_RCR register settings
15.3.4 External trigger input
Figure 76. External trigger input block
Figure 77. TIM1 ETR input circuitry
15.3.5 Clock selection
Figure 78. Control circuit in normal mode, internal clock divided by 1
Figure 79. TI2 external clock connection example
Figure 80. Control circuit in external clock mode 1
Figure 81. External trigger input block
Figure 82. Control circuit in external clock mode 2
15.3.6 Capture/compare channels
Figure 83. Capture/compare channel (example: channel 1 input stage)
Figure 84. Capture/compare channel 1 main circuit
Figure 85. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)
Figure 86. Output stage of capture/compare channel (channel 4)
Figure 87. Output stage of capture/compare channel (channel 5, idem ch. 6)
15.3.7 Input capture mode
15.3.8 PWM input mode
Figure 88. PWM input mode timing
15.3.9 Forced output mode
15.3.10 Output compare mode
Figure 89. Output compare mode, toggle on OC1
15.3.11 PWM mode
Figure 90. Edge-aligned PWM waveforms (ARR=8)
Figure 91. Center-aligned PWM waveforms (ARR=8)
15.3.12 Asymmetric PWM mode
Figure 92. Generation of 2 phase-shifted PWM signals with 50% duty cycle
15.3.13 Combined PWM mode
Figure 93. Combined PWM mode on channel 1 and 3
15.3.14 Combined 3-phase PWM mode
Figure 94. 3-phase combined PWM signals with multiple trigger pulses per period
15.3.15 Complementary outputs and dead-time insertion
Figure 95. Complementary output with dead-time insertion
Figure 96. Dead-time waveforms with delay greater than the negative pulse
Figure 97. Dead-time waveforms with delay greater than the positive pulse
15.3.16 Using the break function
Figure 98. Break and Break2 circuitry overview
Figure 99. Various output behavior in response to a break event on BRK (OSSI = 1)
Table 63. Behavior of timer outputs versus BRK/BRK2 inputs
Figure 100. PWM output state following BRK and BRK2 pins assertion (OSSI=1)
Figure 101. PWM output state following BRK assertion (OSSI=0)
15.3.17 Bidirectional break inputs
Table 64. Break protection disarming conditions
Figure 102. Output redirection (BRK2 request not represented)
15.3.18 Clearing the OCxREF signal on an external event
Figure 103. Clearing TIMx OCxREF
15.3.19 6-step PWM generation
Figure 104. 6-step generation, COM example (OSSR=1)
15.3.20 One-pulse mode
Figure 105. Example of one pulse mode.
15.3.21 Retriggerable one pulse mode (OPM)
Figure 106. Retriggerable one pulse mode
15.3.22 Encoder interface mode
Table 65. Counting direction versus encoder signals
Figure 107. Example of counter operation in encoder interface mode.
Figure 108. Example of encoder interface mode with TI1FP1 polarity inverted.
15.3.23 UIF bit remapping
15.3.24 Timer input XOR function
Figure 109. Measuring time interval between edges on 3 signals
15.3.25 Interfacing with Hall sensors
Figure 110. Example of Hall sensor interface
15.3.26 Timer synchronization
Figure 111. Control circuit in reset mode
Figure 112. Control circuit in Gated mode
Figure 113. Control circuit in trigger mode
Figure 114. Control circuit in external clock mode 2 + trigger mode
15.3.27 ADC synchronization
15.3.28 DMA burst mode
15.3.29 Debug mode
15.4 TIM1 registers
15.4.1 TIM1 control register 1 (TIM1_CR1)
15.4.2 TIM1 control register 2 (TIM1_CR2)
15.4.3 TIM1 slave mode control register (TIM1_SMCR)
Table 66. TIM1 internal trigger connection
15.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER)
15.4.5 TIM1 status register (TIM1_SR)
15.4.6 TIM1 event generation register (TIM1_EGR)
15.4.7 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1)
15.4.8 TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1)
15.4.9 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2)
15.4.10 TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2)
15.4.11 TIM1 capture/compare enable register (TIM1_CCER)
Table 67. Output control bits for complementary OCx and OCxN channels with break feature
15.4.12 TIM1 counter (TIM1_CNT)
15.4.13 TIM1 prescaler (TIM1_PSC)
15.4.14 TIM1 auto-reload register (TIM1_ARR)
15.4.15 TIM1 repetition counter register (TIM1_RCR)
15.4.16 TIM1 capture/compare register 1 (TIM1_CCR1)
15.4.17 TIM1 capture/compare register 2 (TIM1_CCR2)
15.4.18 TIM1 capture/compare register 3 (TIM1_CCR3)
15.4.19 TIM1 capture/compare register 4 (TIM1_CCR4)
15.4.20 TIM1 break and dead-time register (TIM1_BDTR)
15.4.21 TIM1 DMA control register (TIM1_DCR)
15.4.22 TIM1 DMA address for full transfer (TIM1_DMAR)
15.4.23 TIM1 capture/compare mode register 3 (TIM1_CCMR3)
15.4.24 TIM1 capture/compare register 5 (TIM1_CCR5)
15.4.25 TIM1 capture/compare register 6 (TIM1_CCR6)
15.4.26 TIM1 alternate function option register 1 (TIM1_AF1)
15.4.27 TIM1 Alternate function register 2 (TIM1_AF2)
15.4.28 TIM1 timer input selection register (TIM1_TISEL)
15.4.29 TIM1 register map
Table 68. TIM1 register map and reset values
16 General-purpose timer (TIM3)
16.1 TIM3 introduction
16.2 TIM3 main features
Figure 115. General-purpose timer block diagram
16.3 TIM3 functional description
16.3.1 Time-base unit
Figure 116. Counter timing diagram with prescaler division change from 1 to 2
Figure 117. Counter timing diagram with prescaler division change from 1 to 4
16.3.2 Counter modes
Figure 118. Counter timing diagram, internal clock divided by 1
Figure 119. Counter timing diagram, internal clock divided by 2
Figure 120. Counter timing diagram, internal clock divided by 4
Figure 121. Counter timing diagram, internal clock divided by N
Figure 122. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)
Figure 123. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)
Figure 124. Counter timing diagram, internal clock divided by 1
Figure 125. Counter timing diagram, internal clock divided by 2
Figure 126. Counter timing diagram, internal clock divided by 4
Figure 127. Counter timing diagram, internal clock divided by N
Figure 128. Counter timing diagram, Update event when repetition counter is not used
Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
Figure 130. Counter timing diagram, internal clock divided by 2
Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
Figure 132. Counter timing diagram, internal clock divided by N
Figure 133. Counter timing diagram, Update event with ARPE=1 (counter underflow)
Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow)
16.3.3 Clock selection
Figure 135. Control circuit in normal mode, internal clock divided by 1
Figure 136. TI2 external clock connection example
Figure 137. Control circuit in external clock mode 1
Figure 138. External trigger input block
Figure 139. Control circuit in external clock mode 2
16.3.4 Capture/Compare channels
Figure 140. Capture/Compare channel (example: channel 1 input stage)
Figure 141. Capture/Compare channel 1 main circuit
Figure 142. Output stage of Capture/Compare channel (channel 1)
16.3.5 Input capture mode
16.3.6 PWM input mode
Figure 143. PWM input mode timing
16.3.7 Forced output mode
16.3.8 Output compare mode
Figure 144. Output compare mode, toggle on OC1
16.3.9 PWM mode
Figure 145. Edge-aligned PWM waveforms (ARR=8)
Figure 146. Center-aligned PWM waveforms (ARR=8)
16.3.10 Asymmetric PWM mode
Figure 147. Generation of 2 phase-shifted PWM signals with 50% duty cycle
16.3.11 Combined PWM mode
Figure 148. Combined PWM mode on channels 1 and 3
16.3.12 Clearing the OCxREF signal on an external event
Figure 149. Clearing TIMx OCxREF
16.3.13 One-pulse mode
Figure 150. Example of one-pulse mode.
16.3.14 Retriggerable one pulse mode (OPM)
Figure 151. Retriggerable one-pulse mode.
16.3.15 Encoder interface mode
Table 69. Counting direction versus encoder signals
Figure 152. Example of counter operation in encoder interface mode
Figure 153. Example of encoder interface mode with TI1FP1 polarity inverted
16.3.16 UIF bit remapping
16.3.17 Timer input XOR function
16.3.18 Timers and external trigger synchronization
Figure 154. Control circuit in reset mode
Figure 155. Control circuit in gated mode
Figure 156. Control circuit in trigger mode
Figure 157. Control circuit in external clock mode 2 + trigger mode
16.3.19 Timer synchronization
Figure 158. Master/Slave timer example
Figure 159. Gating TIMz with OC1REF of TIMy
Figure 160. Gating TIMz with Enable of TIMy
Figure 161. Triggering TIMz with update of TIMy
Figure 162. Triggering TIMz with Enable of TIMy
Figure 163. Triggering TIMy and TIMz with TIMy TI1 input
16.3.20 DMA burst mode
16.3.21 Debug mode
16.4 TIM3 registers
16.4.1 TIM3 control register 1 (TIM3_CR1)
16.4.2 TIM3 control register 2 (TIM3_CR2)
16.4.3 TIM3 slave mode control register (TIM3_SMCR)
Table 70. TIM3 internal trigger connection
16.4.4 TIM3 DMA/Interrupt enable register (TIM3_DIER)
16.4.5 TIM3 status register (TIM3_SR)
16.4.6 TIM3 event generation register (TIM3_EGR)
16.4.7 TIM3 capture/compare mode register 1 [alternate] (TIM3_CCMR1)
16.4.8 TIM3 capture/compare mode register 1 [alternate] (TIM3_CCMR1)
16.4.9 TIM3 capture/compare mode register 2 [alternate] (TIM3_CCMR2)
16.4.10 TIM3 capture/compare mode register 2 [alternate] (TIM3_CCMR2)
16.4.11 TIM3 capture/compare enable register (TIM3_CCER)
Table 71. Output control bit for standard OCx channels
16.4.12 TIM3 counter [alternate] (TIM3_CNT)
16.4.13 TIM3 counter [alternate] (TIM3_CNT)
16.4.14 TIM3 prescaler (TIM3_PSC)
16.4.15 TIM3 auto-reload register (TIM3_ARR)
16.4.16 TIM3 capture/compare register 1 (TIM3_CCR1)
16.4.17 TIM3 capture/compare register 2 (TIM3_CCR2)
16.4.18 TIM3 capture/compare register 3 (TIM3_CCR3)
16.4.19 TIM3 capture/compare register 4 (TIM3_CCR4)
16.4.20 TIM3 DMA control register (TIM3_DCR)
16.4.21 TIM3 DMA address for full transfer (TIM3_DMAR)
16.4.22 TIM3 alternate function option register 1 (TIM3_AF1)
16.4.23 TIM3 timer input selection register (TIM3_TISEL)
16.4.24 TIMx register map
Table 72. TIM3 register map and reset values
17 Basic timers (TIM6/TIM7)
17.1 TIM6/TIM7 introduction
17.2 TIM6/TIM7 main features
17.3 TIM6/TIM7 functional description
17.3.1 Time-base unit
Prescaler description
17.3.2 Counting mode
17.3.3 UIF bit remapping
17.3.4 Clock source
17.3.5 Debug mode
17.4 TIM6/TIM7 registers
17.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7)
17.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7)
17.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7)
17.4.4 TIMx status register (TIMx_SR)(x = 6 to 7)
17.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7)
17.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7)
17.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7)
17.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)
17.4.9 TIMx register map
Table 73. TIMx register map and reset values
18 General-purpose timers (TIM14)
18.1 TIM14 introduction
18.2 TIM14 main features
18.2.1 TIM14 main features
18.3 TIM14 functional description
18.3.1 Time-base unit
Prescaler description
18.3.2 Counter modes
Upcounting mode
18.3.3 Clock selection
Internal clock source (CK_INT)
18.3.4 Capture/compare channels
18.3.5 Input capture mode
18.3.6 Forced output mode
18.3.7 Output compare mode
18.3.8 PWM mode
18.3.9 One-pulse mode
18.3.10 UIF bit remapping
18.3.11 Debug mode
18.4 TIM14 registers
18.4.1 TIM14 control register 1 (TIM14_CR1)
18.4.2 TIM14 Interrupt enable register (TIM14_DIER)
18.4.3 TIM14 status register (TIM14_SR)
18.4.4 TIM14 event generation register (TIM14_EGR)
18.4.5 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)
18.4.6 TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1)
18.4.7 TIM14 capture/compare enable register (TIM14_CCER)
Table 74. Output control bit for standard OCx channels
18.4.8 TIM14 counter (TIM14_CNT)
18.4.9 TIM14 prescaler (TIM14_PSC)
18.4.10 TIM14 auto-reload register (TIM14_ARR)
18.4.11 TIM14 capture/compare register 1 (TIM14_CCR1)
18.4.12 TIM14 timer input selection register (TIM14_TISEL)
18.4.13 TIM14 register map
Table 75. TIM14 register map and reset values
19 General-purpose timers (TIM15/TIM16/TIM17)
19.1 TIM15/TIM16/TIM17 introduction
19.2 TIM15 main features
19.3 TIM16/TIM17 main features
Figure 189. TIM15 block diagram
Figure 190. TIM16/TIM17 block diagram
19.4 TIM15/TIM16/TIM17 functional description
19.4.1 Time-base unit
Figure 191. Counter timing diagram with prescaler division change from 1 to 2
Figure 192. Counter timing diagram with prescaler division change from 1 to 4
19.4.2 Counter modes
Figure 193. Counter timing diagram, internal clock divided by 1
Figure 194. Counter timing diagram, internal clock divided by 2
Figure 195. Counter timing diagram, internal clock divided by 4
Figure 196. Counter timing diagram, internal clock divided by N
Figure 197. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)
Figure 198. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
19.4.3 Repetition counter
Figure 199. Update rate examples depending on mode and TIMx_RCR register settings
19.4.4 Clock selection
Figure 200. Control circuit in normal mode, internal clock divided by 1
Figure 201. TI2 external clock connection example
Figure 202. Control circuit in external clock mode 1
19.4.5 Capture/compare channels
Figure 203. Capture/compare channel (example: channel 1 input stage)
Figure 204. Capture/compare channel 1 main circuit
Figure 205. Output stage of capture/compare channel (channel 1)
Figure 206. Output stage of capture/compare channel (channel 2 for TIM15)
19.4.6 Input capture mode
19.4.7 PWM input mode (only for TIM15)
Figure 207. PWM input mode timing
19.4.8 Forced output mode
19.4.9 Output compare mode
Figure 208. Output compare mode, toggle on OC1
19.4.10 PWM mode
Figure 209. Edge-aligned PWM waveforms (ARR=8)
19.4.11 Combined PWM mode (TIM15 only)
Figure 210. Combined PWM mode on channel 1 and 2
19.4.12 Complementary outputs and dead-time insertion
Figure 211. Complementary output with dead-time insertion.
Figure 212. Dead-time waveforms with delay greater than the negative pulse.
Figure 213. Dead-time waveforms with delay greater than the positive pulse.
19.4.13 Using the break function
Figure 214. Break circuitry overview
Figure 215. Output behavior in response to a break
19.4.14 Bidirectional break inputs
Table 76. Break protection disarming conditions
Figure 216. Output redirection
19.4.15 One-pulse mode
Figure 217. Example of one pulse mode.
19.4.16 Retriggerable one pulse mode (OPM) (TIM15 only)
Figure 218. Retriggerable one pulse mode
19.4.17 UIF bit remapping
19.4.18 Timer input XOR function (TIM15 only)
Figure 219. Measuring time interval between edges on 2 signals
19.4.19 External trigger synchronization (TIM15 only)
Figure 220. Control circuit in reset mode
Figure 221. Control circuit in gated mode
Figure 222. Control circuit in trigger mode
19.4.20 Slave mode – combined reset + trigger mode
19.4.21 DMA burst mode
19.4.22 Timer synchronization (TIM15)
19.4.23 Debug mode
19.5 TIM15 registers
19.5.1 TIM15 control register 1 (TIM15_CR1)
19.5.2 TIM15 control register 2 (TIM15_CR2)
19.5.3 TIM15 slave mode control register (TIM15_SMCR)
Table 77. TIMx Internal trigger connection
19.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER)
19.5.5 TIM15 status register (TIM15_SR)
19.5.6 TIM15 event generation register (TIM15_EGR)
19.5.7 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1)
19.5.8 TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1)
19.5.9 TIM15 capture/compare enable register (TIM15_CCER)
Table 78. Output control bits for complementary OCx and OCxN channels with break feature (TIM15)
19.5.10 TIM15 counter (TIM15_CNT)
19.5.11 TIM15 prescaler (TIM15_PSC)
19.5.12 TIM15 auto-reload register (TIM15_ARR)
19.5.13 TIM15 repetition counter register (TIM15_RCR)
19.5.14 TIM15 capture/compare register 1 (TIM15_CCR1)
19.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)
19.5.16 TIM15 break and dead-time register (TIM15_BDTR)
19.5.17 TIM15 DMA control register (TIM15_DCR)
19.5.18 TIM15 DMA address for full transfer (TIM15_DMAR)
19.5.19 TIM15 alternate register 1 (TIM15_AF1)
19.5.20 TIM15 input selection register (TIM15_TISEL)
19.5.21 TIM15 register map
Table 79. TIM15 register map and reset values
19.6 TIM16/TIM17 registers
19.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17)
19.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17)
19.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)
19.6.4 TIMx status register (TIMx_SR)(x = 16 to 17)
19.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17)
19.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17)
19.6.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17)
19.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)
Table 80. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17)
19.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17)
19.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17)
19.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)
19.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)
19.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)
19.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)
19.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17)
19.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)
19.6.17 TIM16 alternate function register 1 (TIM16_AF1)
19.6.18 TIM16 input selection register (TIM16_TISEL)
19.6.19 TIM17 alternate function register 1 (TIM17_AF1)
19.6.20 TIM17 input selection register (TIM17_TISEL)
19.6.21 TIM16/TIM17 register map
Table 81. TIM16/TIM17 register map and reset values
20 Infrared interface (IRTIM)
21 Independent watchdog (IWDG)
21.1 Introduction
21.2 IWDG main features
21.3 IWDG functional description
21.3.1 IWDG block diagram
21.3.2 Window option
Configuring the IWDG when the window option is enabled
Configuring the IWDG when the window option is disabled
21.3.3 Hardware watchdog
21.3.4 Register access protection
21.3.5 Debug mode
21.4 IWDG registers
21.4.1 IWDG key register (IWDG_KR)
21.4.2 IWDG prescaler register (IWDG_PR)
21.4.3 IWDG reload register (IWDG_RLR)
21.4.4 IWDG status register (IWDG_SR)
21.4.5 IWDG window register (IWDG_WINR)
21.4.6 IWDG register map
Table 82. IWDG register map and reset values
22 System window watchdog (WWDG)
22.1 Introduction
22.2 WWDG main features
22.3 WWDG functional description
22.3.1 WWDG block diagram
22.3.2 Enabling the watchdog
22.3.3 Controlling the downcounter
22.3.4 Advanced watchdog interrupt feature
22.3.5 How to program the watchdog timeout
22.3.6 Debug mode
22.4 WWDG registers
22.4.1 Control register (WWDG_CR)
22.4.2 Configuration register (WWDG_CFR)
22.4.3 Status register (WWDG_SR)
22.4.4 WWDG register map
Table 83. WWDG register map and reset values
23 Real-time clock (RTC)
23.1 Introduction
23.2 RTC main features
23.3 RTC functional description
23.3.1 RTC block diagram
23.3.2 RTC pins and internal signals
Table 84. RTC input/output pins
Table 85. RTC internal input/output signals
Table 86. RTC interconnection
23.3.3 GPIOs controlled by the RTC and TAMP
Table 87. PC13 configuration
Table 88. RTC_OUT mapping
23.3.4 Clock and prescalers
23.3.5 Real-time clock and calendar
23.3.6 Programmable alarms
23.3.7 Periodic auto-wakeup
23.3.8 RTC initialization and configuration
RTC register access
RTC register write protection
Calendar initialization and configuration
Daylight saving time
Programming the alarm
Programming the wakeup timer
23.3.9 Reading the calendar
When BYPSHAD control bit is cleared in the RTC_CR register
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)
23.3.10 Resetting the RTC
23.3.11 RTC synchronization
23.3.12 RTC reference clock detection
23.3.13 RTC smooth digital calibration
Calibration when PREDIV_A < 3
Verifying the RTC calibration
Re-calibration on-the-fly
23.3.14 Timestamp function
23.3.15 Calibration clock output
23.3.16 Tamper and alarm output
TAMPALRM output
23.4 RTC low-power modes
Table 89. Effect of low-power modes on RTC
Table 90. RTC pins functionality over modes
23.5 RTC interrupts
Table 91. Interrupt requests
23.6 RTC registers
23.6.1 RTC time register (RTC_TR)
23.6.2 RTC date register (RTC_DR)
23.6.3 RTC sub second register (RTC_SSR)
23.6.4 RTC initialization control and status register (RTC_ICSR)
23.6.5 RTC prescaler register (RTC_PRER)
23.6.6 RTC wakeup timer register (RTC_WUTR)
23.6.7 RTC control register (RTC_CR)
23.6.8 RTC write protection register (RTC_WPR)
23.6.9 RTC calibration register (RTC_CALR)
23.6.10 RTC shift control register (RTC_SHIFTR)
23.6.11 RTC timestamp time register (RTC_TSTR)
23.6.12 RTC timestamp date register (RTC_TSDR)
23.6.13 RTC timestamp sub second register (RTC_TSSSR)
23.6.14 RTC alarm A register (RTC_ALRMAR)
23.6.15 RTC alarm A sub second register (RTC_ALRMASSR)
23.6.16 RTC alarm B register (RTC_ALRMBR)
23.6.17 RTC alarm B sub second register (RTC_ALRMBSSR)
23.6.18 RTC status register (RTC_SR)
23.6.19 RTC masked interrupt status register (RTC_MISR)
23.6.20 RTC status clear register (RTC_SCR)
23.6.21 RTC register map
Table 92. RTC register map and reset values
24 Tamper and backup registers (TAMP)
24.1 Introduction
24.2 TAMP main features
24.3 TAMP functional description
24.3.1 TAMP block diagram
24.3.2 TAMP pins and internal signals
Table 93. TAMP input/output pins
Table 94. TAMP internal input/output signals
Table 95. TAMP interconnection
24.3.3 TAMP register write protection
24.3.4 Tamper detection
TAMP backup registers
Tamper detection initialization
Trigger output generation on tamper event
Timestamp on tamper event
Edge detection on tamper inputs (passive mode)
Level detection with filtering on tamper inputs (passive mode)
24.4 TAMP low-power modes
Table 96. Effect of low-power modes on TAMP
24.5 TAMP interrupts
Table 97. Interrupt requests
24.6 TAMP registers
24.6.1 TAMP control register 1 (TAMP_CR1)
24.6.2 TAMP control register 2 (TAMP_CR2)
24.6.3 TAMP filter control register (TAMP_FLTCR)
24.6.4 TAMP interrupt enable register (TAMP_IER)
24.6.5 TAMP status register (TAMP_SR)
24.6.6 TAMP masked interrupt status register (TAMP_MISR)
24.6.7 TAMP status clear register (TAMP_SCR)
24.6.8 TAMP backup x register (TAMP_BKPxR)
24.6.9 TAMP register map
Table 98. TAMP register map and reset values
25 Inter-integrated circuit (I2C) interface
25.1 Introduction
25.2 I2C main features
25.3 I2C implementation
25.4 I2C functional description
25.4.1 I2C1 block diagram
25.4.2 I2C2 block diagram
25.4.3 I2C clock requirements
25.4.4 Mode selection
25.4.5 I2C initialization
25.4.6 Software reset
25.4.7 Data transfer
25.4.8 I2C slave mode
25.4.9 I2C master mode
25.4.10 I2C_TIMINGR register configuration examples
25.4.11 SMBus specific features
25.4.12 SMBus initialization
25.4.13 SMBus: I2C_TIMEOUTR register configuration examples
25.4.14 SMBus slave mode
25.4.15 Wakeup from Stop mode on address match
25.4.16 Error conditions
25.4.17 DMA requests
25.4.18 Debug mode
25.5 I2C low-power modes
25.6 I2C interrupts
25.7 I2C registers
25.7.1 I2C control register 1 (I2C_CR1)
25.7.2 I2C control register 2 (I2C_CR2)
25.7.3 I2C own address 1 register (I2C_OAR1)
25.7.4 I2C own address 2 register (I2C_OAR2)
25.7.5 I2C timing register (I2C_TIMINGR)
25.7.6 I2C timeout register (I2C_TIMEOUTR)
25.7.7 I2C interrupt and status register (I2C_ISR)
25.7.8 I2C interrupt clear register (I2C_ICR)(
25.7.9 I2C PEC register (I2C_PECR)
25.7.10 I2C receive data register (I2C_RXDR)
25.7.11 I2C transmit data register (I2C_TXDR)
25.7.12 I2C register map
26 Universal synchronous/asynchronous receiver transmitter (USART/UART)
26.1 USART introduction
26.2 USART main features
26.3 USART extended features
26.4 USART implementation
Table 115. USART features
26.5 USART functional description
26.5.1 USART block diagram
26.5.2 USART signals
USART bidirectional communications
RS232 Hardware flow control mode
RS485 Hardware control mode
Synchronous master/slave mode and Smartcard mode
26.5.3 USART character description
26.5.4 USART FIFOs and thresholds
26.5.5 USART transmitter
Character transmission
Single byte communication
Break characters
Idle characters
26.5.6 USART receiver
Start bit detection
Character reception
Break character
Idle character
Overrun error
Selecting the clock source and the appropriate oversampling method
Table 116. Noise detection from sampled data
Framing error
Configurable stop bits during reception
26.5.7 USART baud rate generation
How to derive USARTDIV from USART_BRR register values
26.5.8 Tolerance of the USART receiver to clock deviation
Table 117. Tolerance of the USART receiver when BRR [3:0] = 0000
Table 118. Tolerance of the USART receiver when BRR[3:0] is different from 0000
26.5.9 USART Auto baud rate detection
26.5.10 USART multiprocessor communication
Idle line detection (WAKE=0)
4-bit/7-bit address mark detection (WAKE=1)
26.5.11 USART Modbus communication
Modbus/RTU
Modbus/ASCII
26.5.12 USART parity control
Table 119. USART frame formats
Even parity
Odd parity
Parity checking in reception
Parity generation in transmission
26.5.13 USART LIN (local interconnection network) mode
LIN transmission
LIN reception
26.5.14 USART synchronous mode
Master mode
Slave mode
26.5.15 USART single-wire Half-duplex communication
26.5.16 USART receiver timeout
26.5.17 USART Smartcard mode
Block mode (T=1)
Direct and inverse convention
26.5.18 USART IrDA SIR ENDEC block
IrDA low-power mode
26.5.19 Continuous communication using USART and DMA
Transmission using DMA
Reception using DMA
Error flagging and interrupt generation in multibuffer communication
26.5.20 RS232 Hardware flow control and RS485 Driver Enable
RS232 RTS flow control
RS232 CTS flow control
RS485 driver enable
26.5.21 USART low-power management
Using Mute mode with low-power mode
Wakeup from low-power mode when USART kernel clock (usart_ker_ck) is OFF in low-power mode
Determining the maximum USART baud rate that allows to correctly wake up the microcontroller from low-power mode
26.6 USART interrupts
Table 120. USART interrupt requests
26.7 USART registers
26.7.1 USART control register 1 [alternate] (USART_CR1)
26.7.2 USART control register 1 [alternate] (USART_CR1)
26.7.3 USART control register 2 (USART_CR2)
26.7.4 USART control register 3 (USART_CR3)
26.7.5 USART baud rate register (USART_BRR)
26.7.6 USART guard time and prescaler register (USART_GTPR)
26.7.7 USART receiver timeout register (USART_RTOR)
26.7.8 USART request register (USART_RQR)
26.7.9 USART interrupt and status register [alternate] (USART_ISR)
26.7.10 USART interrupt and status register [alternate] (USART_ISR)
26.7.11 USART interrupt flag clear register (USART_ICR)
26.7.12 USART receive data register (USART_RDR)
26.7.13 USART transmit data register (USART_TDR)
26.7.14 USART prescaler register (USART_PRESC)
26.7.15 USART register map
Table 121. USART register map and reset values
27 Serial peripheral interface / inter-IC sound (SPI/I2S)
27.1 Introduction
27.2 SPI main features
27.3 I2S main features
27.4 SPI/I2S implementation
Table 122. STM32G0x0 SPI and SPI/I2S implementation
27.5 SPI functional description
27.5.1 General description
27.5.2 Communications between one master and one slave
Full-duplex communication
Half-duplex communication
Simplex communications
27.5.3 Standard multi-slave communication
27.5.4 Multi-master communication
27.5.5 Slave select (NSS) pin management
27.5.6 Communication formats
Clock phase and polarity controls
Data frame format
27.5.7 Configuration of SPI
27.5.8 Procedure for enabling SPI
27.5.9 Data transmission and reception procedures
RXFIFO and TXFIFO
Sequence handling
Procedure for disabling the SPI
Data packing
Communication using DMA (direct memory addressing)
Packing with DMA
Communication diagrams
27.5.10 SPI status flags
Tx buffer empty flag (TXE)
Rx buffer not empty (RXNE)
Busy flag (BSY)
27.5.11 SPI error flags
Overrun flag (OVR)
Mode fault (MODF)
CRC error (CRCERR)
TI mode frame format error (FRE)
27.5.12 NSS pulse mode
27.5.13 TI mode
TI protocol in master mode
27.5.14 CRC calculation
CRC principle
CRC transfer managed by CPU
CRC transfer managed by DMA
Resetting the SPIx_TXCRC and SPIx_RXCRC values
27.6 SPI interrupts
Table 123. SPI interrupt requests
27.7 I2S functional description
27.7.1 I2S general description
27.7.2 Supported audio protocols
I2S Philips standard
MSB justified standard
LSB justified standard
PCM standard
27.7.3 Start-up description
27.7.4 Clock generator
For I2S modes:
For PCM modes:
Table 124. Audio-frequency precision using standard 8 MHz HSE
27.7.5 I2S master mode
Procedure
Transmission sequence
Reception sequence
27.7.6 I2S slave mode
Transmission sequence
Reception sequence
27.7.7 I2S status flags
Busy flag (BSY)
Tx buffer empty flag (TXE)
RX buffer not empty (RXNE)
Channel Side flag (CHSIDE)
27.7.8 I2S error flags
Underrun flag (UDR)
Overrun flag (OVR)
Frame error flag (FRE)
27.7.9 DMA features
27.8 I2S interrupts
Table 125. I2S interrupt requests
27.9 SPI and I2S registers
27.9.1 SPI control register 1 (SPIx_CR1)
27.9.2 SPI control register 2 (SPIx_CR2)
27.9.3 SPI status register (SPIx_SR)
27.9.4 SPI data register (SPIx_DR)
27.9.5 SPI CRC polynomial register (SPIx_CRCPR)
27.9.6 SPI Rx CRC register (SPIx_RXCRCR)
27.9.7 SPI Tx CRC register (SPIx_TXCRCR)
27.9.8 SPIx_I2S configuration register (SPIx_I2SCFGR)
27.9.9 SPIx_I2S prescaler register (SPIx_I2SPR)
27.9.10 SPI/I2S register map
Table 126. SPI/I2S register map and reset values
28 Debug support (DBG)
28.1 Overview
Figure 324. Block diagram of STM32G0x0 MCU and Cortex®-M0+-level debug support
28.2 Reference Arm documentation
28.3 Pinout and debug port pins
28.3.1 SWD port pins
Table 127. SW debug port pins
28.3.2 SW-DP pin assignment
28.3.3 Internal pull-up & pull-down on SWD pins
28.4 ID codes and locking mechanism
28.5 SWD port
28.5.1 SWD protocol introduction
28.5.2 SWD protocol sequence
Table 128. Packet request (8-bits)
Table 129. ACK response (3 bits)
Table 130. DATA transfer (33 bits)
28.5.3 SW-DP state machine (reset, idle states, ID code)
28.5.4 DP and AP read/write accesses
28.5.5 SW-DP registers
Table 131. SW-DP registers
28.5.6 SW-AP registers
Table 132. 32-bit debug port registers addressed through the shifted value A[3:2]
28.6 Core debug
Table 133. Core debug registers
28.7 BPU (Break Point Unit)
28.7.1 BPU functionality
28.8 DWT (Data Watchpoint)
28.8.1 DWT functionality
28.8.2 DWT Program Counter Sample Register
28.9 MCU debug component (DBG)
28.9.1 Debug support for low-power modes
28.9.2 Debug support for timers, watchdog and I2C
28.10 DBG registers
28.10.1 DBG device ID code register (DBG_IDCODE)
Table 134. DEV_ID and REV_ID field values
28.10.2 DBG configuration register (DBG_CR)
28.10.3 DBG APB freeze register 1 (DBG_APB_FZ1)
28.10.4 DBG APB freeze register 2 (DBG_APB_FZ2)
28.10.5 DBG register map
Table 135. DBG register map and reset values
29 Device electronic signature
29.1 Flash memory size data register
29.2 Package data register
30 Revision history
Table 136. Document revision history
RM0454
Reference manual
STM32G0x0 advanced Arm®-based 32-bit MCUs
Introduction
This reference manual complements the datasheets of the STM32G0x0 microcontrollers,
providing information required for application and in particular for software development. It
pertains to the superset of feature sets available on STM32G0x0 microcontrollers.
For feature set, ordering information, and mechanical and electrical characteristics of a
particular STM32G0x0 device, refer to its corresponding datasheet.
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ technical
reference manual.
“Cortex®-M0+ Technical Reference Manual”, available from: http://infocenter.arm.com
Related documents
•
• PM0223 programming manual for Cortex®-M0+ core(a)
• STM32G0x0 datasheets(a)
• AN2606 application note on booting STM32 MCUs(a)
a. Available on STMicroelectronics website www.st.com
April 2019
RM0454 Rev 2
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1
Contents
Contents
RM0454
1
2
3
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.1
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.3
1.4
Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1
System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2.1
2.2.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 42
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3
2.4
2.5
Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.1
FLASH Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2
FLASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3
3.3.1
FLASH memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
FLASH empty check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.2
3.3.3
FLASH error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
FLASH read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.4
FLASH memory acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.5
3.3.6
FLASH program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . 53
FLASH Main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.7
3.3.8
FLASH Main memory programming sequences . . . . . . . . . . . . . . . . . . 54
FLASH option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FLASH option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4.1
3.4.2
FLASH option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FLASH read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.5.1
3.5.2
FLASH write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.7.1
FLASH access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 68
FLASH key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.7.2
FLASH option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 69
3.7.3
3.7.4
FLASH status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
FLASH control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.7.5
FLASH ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.7.6
3.7.7
FLASH option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . 73
FLASH WRP area A address register (FLASH_WRP1AR) . . . . . . . . . . 75
3.7.8
FLASH WRP area B address register (FLASH_WRP1BR) . . . . . . . . . . 75
3.7.9
3.7.10
FLASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4
4.2
4.3
Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.1
ADC reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.1.1
4.1.2
Battery backup of RTC domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.1.3
4.1.4
Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . . 80
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.2.1
Power-on reset (POR) / power-down reset (PDR) . . . . . . . . . . . . . . . . . 81
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3.1
Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.3.2
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.3.3
4.3.4
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.3.5
Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.3.6
4.3.7
Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3.8
4.3.9
Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.4.1
Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.4.2
4.4.3
Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4.4
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4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
4.4.16
4.4.17
Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 101
Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 102
Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 102
Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 103
Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 103
Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 104
Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 104
Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 105
Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 105
Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 106
Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 106
PWR register map and reset value table . . . . . . . . . . . . . . . . . . . . . . . 108
5
5.2
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
5.1
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1.1
5.1.2
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1.3
RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.2.1
HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.2.2
5.2.3
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.2.4
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2.5
5.2.6
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 119
5.2.7
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.8
5.2.9
Clock security system for LSE clock (LSECSS) . . . . . . . . . . . . . . . . . 120
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.10
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.11
5.2.12
Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.13 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.14
5.2.15
Internal/external clock measurement with TIM14/TIM16/TIM17 . . . . . 122
5.2.16
Peripheral clock enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3
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RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.4.1
5.4.2
Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 127
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 128
5.4.3
PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 130
5.4.4
5.4.5
Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 132
Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 133
5.4.6
Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 134
5.4.7
5.4.8
I/O port reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . 135
AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 136
5.4.9
APB peripheral reset register 1 (RCC_APBRSTR1) . . . . . . . . . . . . . . 137
5.4.10
5.4.11
APB peripheral reset register 2 (RCC_APBRSTR2) . . . . . . . . . . . . . . 139
I/O port clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . 140
5.4.12
AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 141
5.4.13
5.4.14
APB peripheral clock enable register 1 (RCC_APBENR1) . . . . . . . . . 142
APB peripheral clock enable register 2(RCC_APBENR2) . . . . . . . . . . 144
5.4.15
I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . 145
5.4.16
AHB peripheral clock enable in Sleep/Stop mode register
5.4.17
(RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Peripherals independent clock configuration register (RCC_CCIPR) . 150
RTC domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . . . 152
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.4.20
5.4.21
5.4.22
5.4.23
5.4.18
5.4.19
6
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.2
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3
6.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 161
6.3.2
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.3
6.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.5
6.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.7
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.8
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.9
6.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.11
6.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 167
6.3.13
6.3.14
Using the GPIO pins in the RTC domain . . . . . . . . . . . . . . . . . . . . . . . 167
6.3.15
USB PD / Dead battery support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
GPIO port mode register (GPIOx_MODER) (x =A to D, F) . . . . . . . . . 168
6.4.1
6.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A to D, F) . . . . 168
GPIO port output speed register (GPIOx_OSPEEDR)
6.4.3
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
GPIO port input data register (GPIOx_IDR) (x = A to D, F) . . . . . . . . . 170
GPIO port output data register (GPIOx_ODR) (x = A to D, F) . . . . . . . 170
GPIO port bit set/reset register (GPIOx_BSRR) (x = A to D, F) . . . . . . 170
GPIO port configuration lock register (GPIOx_LCKR)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
GPIO alternate function low register (GPIOx_AFRL)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.4.5
6.4.6
6.4.7
6.4.8
6.4.4
6.4.9
7
6.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D, F) . . . . . . . . . . 173
6.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 176
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.1
7.1.1
SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 176
SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 179
7.1.2
SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . . . . 181
7.1.3
7.1.4
SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . . . . 181
SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . . . . 182
7.1.5
SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . . . . 182
7.1.6
7.1.7
SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . . . . 183
SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . . . . 183
7.1.8
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7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
7.1.19
7.1.20
7.1.21
7.1.22
7.1.23
7.1.24
7.1.25
7.1.26
7.1.27
7.1.28
7.1.29
7.1.30
SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . . . . 183
SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . . . . 184
SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . . 184
SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . . 185
SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . . 186
SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . . 186
SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . . 187
SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . . 187
SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . . 188
SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . . 188
SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . . 188
SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . . 189
SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . . 189
SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . . 189
SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . . 190
SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . . 190
SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . . 190
SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . . 191
SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . . 191
SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . . 191
SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . . 192
SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
8
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
8.1
8.2
Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
8.3
8.3.1
From TIM1, TIM3, TIM15, TIM16, and TIM17,
to TIM1, TIM3, and TIM15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
From TIM1, TIM3, TIM6, TIM15, and EXTI, to ADC . . . . . . . . . . . . . . . 197
From ADC to TIM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
From HSE, LSE, LSI, MCO, RTC and TAMP, to TIM14,
TIM16, and TIM17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
From internal analog sources to ADC . . . . . . . . . . . . . . . . . . . . . . . . . 198
From system errors to TIM1, TIM3, TIM15, TIM16, and TIM17 . . . . . . 198
From TIM16, TIM17, USART1, and USART4, to IRTIM . . . . . . . . . . . 198
From TIM14 to DMAMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
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10
RM0454
9.4
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 200
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
9.1
9.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.3
9.3.1
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.3.2
DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.4.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.4.2
DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.4.3
9.4.4
DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.4.5
DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 208
9.4.6
9.4.7
DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.6.1
DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 210
DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 213
9.6.2
DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 214
9.6.3
9.6.4
DMA channel x number of data to transfer register (DMA_CNDTRx) . 217
DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 217
9.6.5
DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 218
9.6.6
9.6.7
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
9.5
9.6
10.3.1
10.3.2
DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
10.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
10.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
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