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Intel MCS 51系列datasheet.pdf

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    MCS® 51 Microcontroller Family User's Manual
    Table of Contents
    Chapter 1: MCS 51 Family of Microcontrollers Architectural Overview
    Introduction
    Memory Organization
    Instruction Set
    CPU Timing
    Additional References
    Chapter 2: Programmer's Guide and Instruction Set
    Memory Organization
    Program Memory
    Indirect Address Area
    Special Function Registers
    What do the SFRs Contain Just After Power-on or a Reset
    SFR Memory Map
    PSW: Program Status Word. Bit Addressable
    PCON: Power Control Register. Not Bit Addressable
    Interrupts
    IE: Interrupt Enable Register. Bit Addressable.
    Assigning Higher Priority to One or More Interrupts
    Priority Within Level
    IP: Interrupt Priority Register. Bit Addressable
    TCON: Timer/Counter Control Register. Bit Addressable.
    TMOD: Timer/Counter Mode Control Register. Not Bit Addressable.
    Timer Set-Up
    Timer/Counter 0
    Timer/Counter 1
    T2CON: Timer/Counter 2 Control Register. Bit Addressable.
    Timer/Counter 2 Set-Up
    SCON: Serial Port Control Register. Bit Addressable.
    Generating Baud Rates
    Using Timer/Counter 1 to Generate Baud Rates
    Using Timer/Counter 2 to Generate Baud Rates
    Serial Port in Mode 2
    Serial Port in Mode 3
    MCS-51 Instruction Set
    Instruction Definitions
    Chapter 3: 8051, 8052, 80C51 Hardware Description
    Introduction
    Port Structures and Operation
    Accessing External Memory
    Timer/Counters
    Serial Interface
    Interrupts
    Single-Step Operation
    Reset
    Power-On Reset
    Power-Saving Modes of Operation
    EPROM Versions
    The On-Chip Oscillators
    Internal Timing
    MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994
    Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notk Contact your local Intel sales office or your distributor to obtain the latest speoificationa before placing your product order. MDS is an ordering code only and is not usad ae a product name or trademark of Intel Corporation. Intel Corporation and Intel’s FASTPATH are not affiliated with Kinetics, a division of Excelan, trademark or products, Inc. or its FASTPATH lOfher brands and names are the properly of their respective owners, Additional copies of this document or other Intel literature maybe obtained from: Intel Corporation Literature Selas P.O. Box 7S41 Mt. Prospect, IL 6005S-7641 or call 1-800-879-4683 c-INTELCORPORATION, 1093
    MCS” 51 CONTENTS PAGE MICROCONTROLLER c“*pTf==1 FAMILY MCS 51 Family of Microcontrollers USER’S MANUAL Archkedural Ovewiew .............................l-l CHAPTER 2 MCS 51 Programmer’s Guide and Instruction Set ..........................................2-l CHAPTER 3 8051, 8052 and 80C51 Hardware Description ...............................................3.l CHAPTER 4 8XC52J54/58 Hardware Description ............4-1 CHAPTER 5 8XC51 FX Hardware Description .................5-1 CHAPTER 6 87C51GB Hardware Description .................8-1 CHAPTER 7 83CI 52 Hardware Description ....................7-1
    MCS@51 Family of Microcontrollers Architectural Overview 1
    MCS@51 FAMILY OF CONTENTS PAGE MICROCONTROLLERS ARCHITECTURAL INTRODUCTION .........................................1-3 CHMOSDevices .....”.....’.......”.....-...-..........I-5 OVERVIEW M;~$&:RGA-~oN INMc- 51 .................................................1-6 Lo ical Separation of Program and Data h emoy ....................................................l+ Program Memo~ .........................................l-7 Data Memory ...............................................1 -8 THE MC951 INSTRUCTION SET .............1 -9 Program Status Word ..................................1 -9 lnstrudions Addressing Modes .....................................l-l O Arithmetic Instructions ...............................1-10 Logical Data Tran#ers Boolean Instructions ..................................1-14 Jump Instructions ......................................1-16 ....................................l.l2 ...........................................l.l2 CPU TIMING .............................................l-l7 Machine Cycles .........................................1-18 Interrupt Structure ......................................l.2O ADDITIONAL REFERENCES ...................1 -22 1-1
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