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ARM-Cortex_-M4内核参考手册.pdf
Cortex-M4 Technical Reference Manual
Contents
List of Tables
List of Figures
Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Typographical
Additional reading
ARM publications
Other publications
Feedback
Feedback on this product
Feedback on this manual
Introduction
1.1 About the processor
1.2 Features
1.3 Interfaces
1.4 Configurable options
1.5 Product documentation
1.5.1 Documentation
1.5.2 Design Flow
1.5.3 Architecture and protocol information
ARM architecture
Bus architecture
Debug
Embedded Trace Macrocell
Floating Point Unit
Functional Description
2.1 About the functions
2.2 Interfaces
2.2.1 Bus interfaces
ICode memory interface
DCode memory interface
System interface
Private Peripheral Bus (PPB)
2.2.2 ETM interface
2.2.3 AHB Trace Macrocell interface
2.2.4 Debug port AHB-AP interface
Programmers Model
3.1 About the programmers model
3.2 Modes of operation and execution
3.2.1 Operating modes
3.2.2 Operating states
3.2.3 Privileged access and user access
3.3 Instruction set summary
3.3.1 Cortex-M4 instructions
3.3.2 Load/store timings
3.3.3 Binary compatibility with other Cortex processors
3.4 System address map
3.4.1 Private peripheral bus
3.4.2 Unaligned accesses that cross regions
3.5 Write buffer
3.6 Exclusive monitor
3.7 Bit-banding
3.7.1 Directly accessing an alias region
3.7.2 Directly accessing a bit-band region
3.8 Processor core register summary
3.9 Exceptions
3.9.1 Exception handling
Base register update in LDM and STM operations
System Control
4.1 About system control
4.2 Register summary
4.3 Register descriptions
4.3.1 Auxiliary Control Register, ACTLR
4.3.2 CPUID Base Register, CPUID
4.3.3 Auxiliary Fault Status Register, AFSR
Memory Protection Unit
5.1 About the MPU
5.2 MPU functional description
5.3 MPU programmers model
Nested Vectored Interrupt Controller
6.1 About the NVIC
6.2 NVIC functional description
6.2.1 Low power modes
6.2.2 Level versus pulse interrupts
6.3 NVIC programmers model
6.3.1 Interrupt Controller Type Register, ICTR
Floating Point Unit
7.1 About the FPU
7.2 FPU Functional Description
7.2.1 FPU views of the register bank
7.2.2 Modes of operation
Full-compliance mode
Flush-to-zero mode
Default NaN mode
7.2.3 FPU instruction set
7.2.4 Compliance with the IEEE 754 standard
7.2.5 Complete implementation of the IEEE 754 standard
7.2.6 IEEE 754 standard implementation choices
NaN handling
Comparisons
Underflow
7.2.7 Exceptions
7.3 FPU Programmers Model
7.3.1 Enabling the FPU
Debug
8.1 About debug
8.1.1 Cortex-M4 ROM table identification and entries
8.1.2 System Control Space
SCS CoreSight identification
8.1.3 Debug register summary
8.2 About the AHB-AP
8.2.1 AHB-AP transaction types
8.2.2 AHB-AP programmers model
AHB-AP Control and Status Word Register, CSW
8.3 About the Flash Patch and Breakpoint Unit (FPB)
8.3.1 FPB functional description
8.3.2 FPB programmers model
Data Watchpoint and Trace Unit
9.1 About the DWT
9.2 DWT functional description
9.3 DWT Programmers Model
Instrumentation Trace Macrocell Unit
10.1 About the ITM
10.2 ITM functional description
10.3 ITM programmers model
10.3.1 ITM Trace Privilege Register, ITM_TPR
Trace Port Interface Unit
11.1 About the Cortex-M4 TPIU
11.2 TPIU functional description
11.2.1 TPIU block diagrams
11.2.2 TPIU Formatter
11.2.3 Serial Wire Output format
11.3 TPIU programmers model
11.3.1 Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.2 Formatter and Flush Status Register, TPIU_FFSR
11.3.3 Formatter and Flush Control Register, TPIU_FFCR
11.3.4 TRIGGER
11.3.5 Integration ETM Data
11.3.6 ITATBCTR2
11.3.7 Integration ITM Data
11.3.8 ITATBCTR0
11.3.9 Integration Mode Control, TPIU_ITCTRL
11.3.10 TPIU_DEVID
Revisions
Glossary
Cortex-M4
Revision r0p0
Technical Reference Manual
Copyright © 2009, 2010 ARM Limited. All rights reserved.
ARM DDI 0439B (ID030210)
Cortex-M4
Technical Reference Manual
Copyright © 2009, 2010 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Change History
Date
Issue
Confidentiality
Change
22 December 2009
02 March 2010
A
B
Non-Confidential, Restricted Access
First release for r0p0
Non-Confidential
Second release for r0p0
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® Limited in the EU and other
countries, except as otherwise stated in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied
or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any
loss or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Some material in this document is based on IEEE 754-2008 IEEE Standard for Binary Floating-Point Arithmetic. The
IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is Final (information on a developed product).
Web Address
http://www.arm.com
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ii
Contents
Cortex-M4 Technical Reference Manual
Chapter 1
Chapter 2
Chapter 3
Preface
About this book ........................................................................................................... ix
Feedback .................................................................................................................... xi
Introduction
1.1
1.2
1.3
1.4
1.5
About the processor ................................................................................................. 1-2
Features ................................................................................................................... 1-3
Interfaces ................................................................................................................. 1-4
Configurable options ................................................................................................ 1-5
Product documentation ............................................................................................ 1-6
Functional Description
2.1
2.2
About the functions .................................................................................................. 2-2
Interfaces ................................................................................................................. 2-5
Programmers Model
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
About the programmers model ................................................................................ 3-2
Modes of operation and execution ........................................................................... 3-3
Instruction set summary ........................................................................................... 3-4
System address map ............................................................................................. 3-14
Write buffer ............................................................................................................ 3-17
Exclusive monitor ................................................................................................... 3-18
Bit-banding ............................................................................................................. 3-19
Processor core register summary .......................................................................... 3-21
Exceptions ............................................................................................................. 3-23
Chapter 4
System Control
4.1
About system control ............................................................................................... 4-2
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Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Contents
4.2
4.3
Register summary .................................................................................................... 4-3
Register descriptions ............................................................................................... 4-5
Memory Protection Unit
5.1
5.2
5.3
About the MPU ........................................................................................................ 5-2
MPU functional description ...................................................................................... 5-3
MPU programmers model ........................................................................................ 5-4
Nested Vectored Interrupt Controller
6.1
6.2
6.3
About the NVIC ........................................................................................................ 6-2
NVIC functional description ..................................................................................... 6-3
NVIC programmers model ....................................................................................... 6-4
Floating Point Unit
7.1
7.2
7.3
About the FPU ......................................................................................................... 7-2
FPU Functional Description ..................................................................................... 7-3
FPU Programmers Model ........................................................................................ 7-9
Debug
8.1
8.2
8.3
About debug ............................................................................................................ 8-2
About the AHB-AP ................................................................................................... 8-6
About the Flash Patch and Breakpoint Unit (FPB) .................................................. 8-9
Data Watchpoint and Trace Unit
9.1
9.2
9.3
About the DWT ........................................................................................................ 9-2
DWT functional description ...................................................................................... 9-3
DWT Programmers Model ....................................................................................... 9-4
Instrumentation Trace Macrocell Unit
10.1
10.2
10.3
About the ITM ........................................................................................................ 10-2
ITM functional description ...................................................................................... 10-3
ITM programmers model ....................................................................................... 10-4
Trace Port Interface Unit
11.1
11.2
11.3
About the Cortex-M4 TPIU .................................................................................... 11-2
TPIU functional description .................................................................................... 11-3
TPIU programmers model ..................................................................................... 11-5
Appendix A
Revisions
Glossary
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List of Tables
Cortex-M4 Technical Reference Manual
Table 3-1
Table 3-2
Table 3-3
Table 4-1
Table 4-2
Table 4-3
Table 4-4
Table 5-1
Table 6-1
Table 6-2
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 9-1
Table 10-1
Table 10-2
Table 11-1
Table 11-2
Table 11-3
Table 11-4
Table 11-5
Change History ............................................................................................................................... ii
Cortex-M4 instruction set summary ............................................................................................ 3-4
Cortex-M4 DSP instruction set summary .................................................................................... 3-8
Memory regions ........................................................................................................................ 3-14
System control registers ............................................................................................................. 4-3
ACTLR bit assignments .............................................................................................................. 4-5
CPUID bit assignments ............................................................................................................... 4-6
AFSR bit assignments ................................................................................................................ 4-7
MPU registers ............................................................................................................................. 5-4
NVIC registers ............................................................................................................................. 6-4
ICTR bit assignments .................................................................................................................. 6-5
FPU instruction set ...................................................................................................................... 7-4
Default NaN values ..................................................................................................................... 7-6
QNaN and SNaN handling .......................................................................................................... 7-7
Cortex-M4F Floating Point system registers ............................................................................... 7-9
Cortex-M4 ROM table identification values ................................................................................. 8-3
Cortex-M4 ROM table components ............................................................................................ 8-3
SCS identification values ............................................................................................................ 8-4
Debug registers ........................................................................................................................... 8-5
AHB-AP register summary .......................................................................................................... 8-6
CSW bit assignments .................................................................................................................. 8-7
FPB register summary .............................................................................................................. 8-10
DWT register summary ............................................................................................................... 9-4
ITM register summary ............................................................................................................... 10-4
ITM_TPR bit assignments ......................................................................................................... 10-5
TPIU registers ........................................................................................................................... 11-5
TPIU_ACPR bit assignments .................................................................................................... 11-6
TPIU_FFSR bit assignments .................................................................................................... 11-7
TPIU_FFCR bit assignments .................................................................................................... 11-7
TRIGGER bit assignments ........................................................................................................ 11-8
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List of Tables
Table 11-6
Table 11-7
Table 11-8
Table 11-9
Table 11-10
Table 11-11
Table A-1
Table A-2
Integration ETM Data bit assignments ...................................................................................... 11-9
ITATBCTR2 bit assignments .................................................................................................. 11-10
Integration ITM Data bit assignments ..................................................................................... 11-10
ITATBCTR0 bit assignments .................................................................................................. 11-11
TPIU_ITCTRL bit assignments ............................................................................................... 11-12
TPIU_DEVID bit assignments ................................................................................................. 11-12
Issue A ........................................................................................................................................ A-1
Differences between issue A and issue BC ................................................................................ A-1
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List of Figures
Cortex-M4 Technical Reference Manual
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 4-1
Figure 4-2
Figure 4-3
Figure 6-1
Figure 7-1
Figure 8-1
Figure 8-2
Figure 10-1
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Figure 11-5
Figure 11-6
Figure 11-7
Figure 11-8
Figure 11-9
Figure 11-10
Figure 11-11
Cortex-M4 block diagram ............................................................................................................ 2-2
System address map ................................................................................................................ 3-14
Bit-band mapping ...................................................................................................................... 3-20
Processor register set ............................................................................................................... 3-21
ACTLR bit assignments .............................................................................................................. 4-5
CPUID bit assignments ............................................................................................................... 4-6
AFSR bit assignments ................................................................................................................ 4-6
ICTR bit assignments .................................................................................................................. 6-4
FPU register bank ....................................................................................................................... 7-3
CoreSight discovery .................................................................................................................... 8-2
CSW bit assignments .................................................................................................................. 8-7
ITM_TPR bit assignments ......................................................................................................... 10-5
TPIU block diagram .................................................................................................................. 11-3
TPIU_ACPR bit assignments .................................................................................................... 11-6
TPIU_FFSR bit assignments .................................................................................................... 11-6
TPIU_FFCR bit assignments .................................................................................................... 11-7
TRIGGER bit assignments ........................................................................................................ 11-8
Integration ETM Data bit assignments ...................................................................................... 11-9
ITATBCTR2 bit assignments .................................................................................................... 11-9
Integration ITM Data bit assignments ..................................................................................... 11-10
ITATBCTR0 bit assignments .................................................................................................. 11-11
TPIU_ITCTRL bit assignments ............................................................................................... 11-11
TPIU_DEVID bit assignments ................................................................................................. 11-12
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vii
Preface
This preface introduces the Cortex-M4 Technical Reference Manual (TRM). It contains the
following sections:
•
•
About this book on page ix
Feedback on page xi.
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viii
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