L6599的数据手册.pdf

发布时间：2022-06-14 发布人：admin 分类：说明书资料大小：0.59M 资料格式：pdf 举报版权申诉

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第1页.png

第1页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第2页.png

第2页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第3页.png

第3页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第4页.png

第4页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第5页.png

第5页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第6页.png

第6页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第7页.png

第7页 / 共36页

3e305f39-7a36-44ef-92b0-1d78c9f3ab2e.pdf-第8页.png

第8页 / 共36页

文本预览

元器件交易网www.cecb2b.com May 2006 Rev 11/3636L6599 High-voltage resonant controllerFeatures■50% duty cycle, variable frequency control of resonant half-bridge■High-accuracy oscillator■Up to 500kHz operating frequency■Two-level OCP: frequency-shift and latched shutdown ■Interface with PFC controller■Latched disable input ■Burst-mode operation at light load■Input for power-ON/OFF sequencing or brownout protection■Non-linear soft-start for monotonic output voltage rise■600V-rail compatible high-side gate driver with integrated bootstrap diode and high dV/dt immunity■-300/800mA high-side and low-side gate drivers with UVLO pull-down■DIP-16, SO-16N packages Applications■LCD & PDP TV■Desktop PC, entry-level server■Telecom SMPS■AC-DC adapter, open frame SMPSOrder codePart numberPackagePackagingL6599DSO-16NTubeL6599TRSO-16NTape and reelL6599NDIP-16TubeDIP-16SO-16Nwww.st.comBlock diagramSTANDBYDISISEN_DISGNDIfmin ISEN0.8V1.5VPFC_STOPVccVBOOTOUTCBOOT LC TANKCIRCUITH.V. LVGUV DETECTIONVs HVGSYNCHRONOUSBOOTSTRAP DIODEHVG DRIVER LVG DRIVERCssCFDISABLE +-DISLINEDEAD TIME +-+-LEVELSHIFTER12 87431 961011141516RFmin1.85VS QRUVLOUVLOQ SRUVLOCONTROLLOGIC+-LINE_OK1.25V15µADISISEN_DIS17V6.3VVCO-+1.25VSTANDBY+-STBY5DRIVING LOGIC 2V2DELAY

元器件交易网www.cecb2b.com ContentsL65992/36 Contents1Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Typical system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.2Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.3Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.4Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.6Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.7Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297.8Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

元器件交易网www.cecb2b.com L6599Device description 3/361 Device descriptionThe L6599 is a double-ended controller specific for the resonant half-bridge topology. It provides 50% complementary duty cycle: the high-side switch and the low-side switch are driven ON 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed dead-time inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well.The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum. IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP. An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.

元器件交易网www.cecb2b.com Pin SettingsL65994/36 2 Pin Settings2.1 ConnectionFigure 1.Pin Connection (Top view)2.2 FunctionsGNDCssDELAYSTBYISENLINELVGVBOOTHVGN.C.VccPFC_STOPOUTDISCFRFmin12345678161514131211109Table 1.Pin functionsN.NameFunction1CSSSoft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (VCC < UVLO, LINE < 1.25V or > 6V, DIS > 1.85V, ISEN > 1.5V, DELAY > 3.5V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V, as long as it stays above 0.75V.2DELAYDelayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8V the capacitor is charged by an internal 150µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2V, the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150µA is kept always on. As the voltage on the pin exceeds 3.5V the IC stops switching and the internal generator is turned OFF, so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V. In this way, under short circuit conditions, the converter will work intermittently with very low input average power.3CFTiming capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.

元器件交易网www.cecb2b.com L6599Pin Settings 5/364RFminMinimum oscillator frequency setting. This pin provides a precise 2V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operating frequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).5STBYBurst-mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.25V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50mV. Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.6ISENCurrent sense input. The pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8V threshold (with 50mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.7LINELine sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25V. The comparator is provided with current hysteresis: an internal 15µA current generator is ON as long as the voltage applied at the pin is below 1.25V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6V if the function is not used.8DISLatched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85V, shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.9PFC_STOPOpen-drain ON/OFF control of PFC controller. This pin, normally open, is intended for stopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85V, ISEN > 1.5V, LINE > 6V and STBY < 1.25V. The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V. During UVLO, it is open. Leave the pin unconnected if not used.10GNDChip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.Table 1.Pin functions

元器件交易网www.cecb2b.com Typical system block diagramL65996/36 3 Typical system block diagramFigure 2.Typical system block diagram11LVGLow-side gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.12VCCSupply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC. 13N.C.High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.14OUTHigh-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.15HVGHigh-side floating gate-drive output. The driver is capable of 0.3A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO. 16VBOOTHigh-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.Table 1.Pin functions

元器件交易网www.cecb2b.com L6599Electrical data 7/364 Electrical data4.1 Maximum ratingsNote:ESD immunity for pins 14, 15 and 16 is guaranteed up to 900V4.2 Thermal dataTable 2.Absolute maximum ratingsSymbol Pin Parameter Value Unit VBOOT16 Floating supply voltage -1 to 618 V VOUT14 Floating ground voltage -3 to VBOOT -18 V dVOUT /dt 14 Floating ground max. slew rate 50 V/ns VCC 12 IC Supply voltage (ICC ≤ 25 mA) Self-limited V VPFC_STOP9 Maximum voltage (pin open) -0.3 to VCC V IPFC_STOP9 Maximum sink current (pin low) Self-limited A VLINEmax7 Maximum pin voltage (Ipin ≤ 1mA) Self-limited V IRFmin4 Maximum source current 2 mA 1 to 6, 8 Analog inputs & outputs -0.3 to 5 V Table 3.Thermal dataSymbolDescriptionValueUnitRthJAMax. thermal resistance junction to ambient (DIP16)80°C/WMax. thermal resistance junction to ambient (SO16)120TSTGStorage temperature range-55 to 150°CTJJunction operating temperature range-40 to 150°CPTOT Recommended max. power dissipation @TA = 70°C (DIP16)1 W Recommended max. power dissipation @TA = 50°C (SO16) 0.83

元器件交易网www.cecb2b.com Electrical characteristicsL65998/36 5 Electrical characteristicsTJ = 0 to 105°C, VCC = 15V, VBOOT = 15V, CHVG = CLVG = 1nF; CF = 470pF; RRFmin = 12kΩ; unless otherwise specified.Table 4.Electrical characteristicsSymbol Parameter Test condition MinTypMaxUnit IC supply voltage VCCOperating range After device turn-on8.85 16 V VCC(ON)Turn-ON threshold Voltage rising10 10.7 11.4 V VCC(OFF)Turn-OFF threshold Voltage falling 7.45 8.15 8.85 V Hys Hysteresis 2.55 V VZVCC clamp voltage Iclamp = 10mA 16 17 17.9 V Supply currentIstart-upStart-up current Before device turn-ON VCC = VCC(ON) - 0.2V 200 250 µA IqQuiescent current Device ON, VSTBY = 1V 1.5 2 mA IopOperating current Device ON, VSTBY = VRFmin3.5 5 mA IqResidual consumption VDIS > 1.85V or VDELAY > 3.5V or VLINE < 1.25 V or VLINE = Vclamp300 400 µA High-side floating gate-drive supplyILKBOOTVBOOT pin leakage current VBOOT = 580V 5 µA ILKOUTOUT pin leakage current VOUT = 562V 5 µA rDS(on)Synchronous bootstrap diode ON-resistance VLVG = High 150 ΩOvercurrent comparator IISENInput bias current VISEN = 0 to VISENdis-1 µA tLEBLeading edge blanking After VHVG and VLVG low-to-high transition 250 ns VISENxFrequency shift threshold Voltage rising (1)0.76 0.8 0.84 V Hysteresis Voltage falling 50 mV VISENdisLatch OFF threshold Voltage rising (1)1.44 1.5 1.56 V td(H-L)Delay to output 300400 ns

分享到：

赞收藏

资料库

L6599的数据手册.pdf

相关推荐

开发技术

热门标签

最新资料