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powerpc mpc8313e 芯片手册.pdf
Contents
Figures
Tables
About This Book
Audience
Organization
Suggested Reading
Conventions
Signal Conventions
Acronyms and Abbreviations
Chapter 1 Overview
1.1 MPC8313E PowerQUICC II Pro Processor Overview
1.2 MPC8313E Architecture Overview
1.2.1 Power Architecture Core
1.2.2 Security Engine
1.2.3 DDR Memory Controller
1.2.4 Dual Enhanced Three-Speed Ethernet Controllers
1.2.5 PCI Controller
1.2.5.1 PCI Bus Arbitration Unit
1.2.6 Universal Serial Bus (USB) 2.0
1.2.6.1 USB Dual-Role Controller
1.2.7 Enhanced Local Bus Controller (eLBC)
1.2.8 Integrated Programmable Interrupt Controller (IPIC)
1.2.9 Dual I2C Interfaces
1.2.10 DMA Controller
1.2.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)
1.2.12 Serial Peripheral Interface (SPI)
1.2.13 System Timers
1.3 Application Examples
1.3.1 Low-End Printer CPU and Interface ASIC
1.3.2 High-End Printer I/O Processor
1.3.3 IEEE Std. 1588 in Test and Measurement and Industrial Automation
1.3.4 IEEE Std. 802.11n WLAN Access Point
1.3.5 Media Server
Chapter 2 Memory Map
2.1 Internal Memory Mapped Registers
2.2 Accessing IMMR Memory From the Local Processor
2.3 Complete IMMR Map
Chapter 3 Signal Descriptions
3.1 Signals Overview
3.2 Configuration Signals Sampled at Reset
3.3 Output Signal States During Reset
3.4 External Signal Description
Chapter 4 Reset, Clocking, and Initialization
4.1 External Signals
4.1.1 Reset Signals
4.1.2 Clock Signals
4.2 Functional Description
4.2.1 Reset Operations
4.2.1.1 Reset Causes
4.2.1.2 Reset Actions
4.2.2 Power-On Reset Flow
4.2.3 Hard Reset Flow
4.2.4 Soft Reset Flow
4.3 Reset Configuration
4.3.1 Reset Configuration Signals
4.3.1.1 Reset Configuration Word Source
4.3.1.2 SYS_CLK_IN Division
4.3.1.3 Selecting Reset Configuration Input Signals
4.3.2 Reset Configuration Words
4.3.2.1 Reset Configuration Word Low Register (RCWLR)
4.3.2.2 Reset Configuration Word High Register (RCWHR)
4.3.3 Loading the Reset Configuration Words
4.3.3.1 Loading from Local Bus
4.3.3.2 Loading from I2C EEPROM
4.3.3.3 Default Reset Configuration Words
4.4 Clocking
4.4.1 Clocking in PCI Host Mode
4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:2])
4.4.2 Clocking In PCI Agent Mode
4.4.3 System Clock Domains
4.4.4 USB Clocking
4.4.5 Ethernet Clocking
4.4.6 Real-Time Clock (RTC)
4.5 Memory Map/Register Definitions
4.5.1 Reset Configuration Register Descriptions
4.5.1.1 Reset Configuration Word Low Register (RCWLR)
4.5.1.2 Reset Configuration Word High Register (RCWHR)
4.5.1.3 Reset Status Register (RSR)
4.5.1.4 Reset Mode Register (RMR)
4.5.1.5 Reset Protection Register (RPR)
4.5.1.6 Reset Control Register (RCR)
4.5.1.7 Reset Control Enable Register (RCER)
4.5.2 Clock Configuration Registers
4.5.2.1 System PLL Mode Register (SPMR)
4.5.2.2 Output Clock Control Register (OCCR)
4.5.2.3 System Clock Control Register (SCCR)
Chapter 5 System Configuration
5.1 Introduction
5.2 Local Memory Map Overview and Example
5.2.1 Address Translation and Mapping
5.2.2 Window into Configuration Space
5.2.3 Local Access Windows
5.2.3.1 Local Access Register Memory Map
5.2.4 Local Access Register Descriptions
5.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR)
5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)
5.2.4.3 LBC Local Access Window n Base Address Registers (LBLAWBAR0-LBLAWBAR3)
5.2.4.4 LBC Local Access Window n Attributes Registers (LBLAWAR0-LBLAWAR3)
5.2.4.5 PCI Local Access Window n Base Address Register (PCILAWBAR0-PCILAWBAR1)
5.2.4.6 PCI Local Access Window n Attributes Registers (PCILAWAR0-PCILAWAR1)
5.2.4.7 DDR Local Access Window n Base Address Registers (DDRLAWBAR0-DDRLAWBAR1)
5.2.4.8 DDR Local Access Window n Attributes Registers (DDRLAWAR0-DDRLAWAR1)
5.2.5 Precedence of Local Access Windows
5.2.6 Configuring Local Access Windows
5.2.7 Distinguishing Local Access Windows from Other Mapping Functions
5.2.8 Outbound Address Translation and Mapping Windows
5.2.9 Inbound Address Translation and Mapping Windows
5.2.9.1 PCI Inbound Windows
5.2.10 Internal Memory Map
5.2.11 Accessing Internal Memory from External Masters
5.3 System Configuration
5.3.1 System Configuration Register Memory Map
5.3.2 System Configuration Registers
5.3.2.1 System General Purpose Register Low (SGPRL)
5.3.2.2 System General Purpose Register High (SGPRH)
5.3.2.3 System Part and Revision ID Register (SPRIDR)
5.3.2.4 System Priority and Configuration Register (SPCR)
5.3.2.5 System I/O Configuration Register Low (SICRL)
5.3.2.6 System I/O Configuration Register High (SICRH)
5.3.2.7 Debug Configuration
5.3.2.8 DDR Control Driver Register (DDRCDR)
5.3.2.9 DDR Debug Status Register (DDRDSR)
5.4 Software Watchdog Timer (WDT)
5.4.1 WDT Overview
5.4.2 WDT Features
5.4.3 WDT Modes of Operation
5.4.4 WDT Memory Map/Register Definition
5.4.4.1 System Watchdog Control Register (SWCRR)
5.4.4.2 System Watchdog Count Register (SWCNR)
5.4.4.3 System Watchdog Service Register (SWSRR)
5.4.5 Functional Description
5.4.5.1 Software Watchdog Timer Unit
5.4.5.2 Modes of Operation
5.4.6 Initialization/Application Information
5.4.6.1 WDT Programming Guidelines
5.5 Real Time Clock Module (RTC)
5.5.1 RTC Overview
5.5.2 RTC Features
5.5.3 RTC Modes of Operation
5.5.4 RTC External Signal Description
5.5.5 RTC Memory Map/Register Definition
5.5.5.1 Real Time Counter Control Register (RTCNR)
5.5.5.2 Real Time Counter Load Register (RTLDR)
5.5.5.3 Real Time Counter Prescale Register (RTPSR)
5.5.5.4 Real Time Counter Register (RTCTR)
5.5.5.5 Real Time Counter Event Register (RTEVR)
5.5.5.6 Real Time Counter Alarm Register (RTALR)
5.5.6 Functional Description
5.5.6.1 Real Time Counter Unit
5.5.6.2 RTC Operational Modes
5.5.7 RTC Programming Guidelines
5.6 Periodic Interval Timer (PIT)
5.6.1 PIT Overview
5.6.2 PIT Features
5.6.3 PIT Modes of Operation
5.6.4 PIT External Signal Description
5.6.5 PIT Memory Map/Register Definition
5.6.5.1 Periodic Interval Timer Control Register (PTCNR)
5.6.5.2 Periodic Interval Timer Load Register (PTLDR)
5.6.5.3 Periodic Interval Timer Prescale Register (PTPSR)
5.6.5.4 Periodic Interval Timer Counter Register (PTCTR)
5.6.5.5 Periodic Interval Timer Event Register (PTEVR)
5.6.6 Functional Description
5.6.6.1 Periodic Interval Timer Unit
5.6.6.2 PIT Operational Modes
5.6.7 PIT Programming Guidelines
5.7 General-Purpose Timers (GTMs)
5.7.1 GTM Overview
5.7.2 GTM Features
5.7.3 GTM Modes of Operation
5.7.3.1 Cascaded Modes
5.7.3.2 Clock Source Modes
5.7.3.3 Reference Modes
5.7.3.4 Capture Modes
5.7.4 GTM External Signal Description
5.7.5 GTM Memory Map/Register Definition
5.7.5.1 Global Timers Configuration Registers (GTCFRn)
5.7.5.2 Global Timers Mode Registers (GTMDR1-GTMDR4)
5.7.5.3 Global Timers Reference Registers (GTRFR1-GTRFR4)
5.7.5.4 Global Timers Capture Registers (GTCPR1-GTCPR4)
5.7.5.5 Global Timers Counter Registers (GTCNR1-GTCNR4)
5.7.5.6 Global Timers Event Registers (GTEVR1-GTEVR4)
5.7.5.7 Global Timers Prescale Registers (GTPSR1-GTPSR4)
5.7.6 Functional Description
5.7.6.1 General-Purpose Timer Units
5.7.6.2 Reference Modes
5.7.6.3 Capture Modes
5.7.6.4 Cascaded Modes
5.7.7 Initialization/Application Information
5.7.7.1 Programming Guidelines
5.8 Power Management Control (PMC)
5.8.1 External Signal Description
5.8.2 PMC Memory Map/Register Definition
5.8.2.1 Power Management Controller Configuration Register (PMCCR)
5.8.2.2 Power Management Controller Event Register (PMCER)
5.8.2.3 Power Management Controller Mask Register (PMCMR)
5.8.2.4 Power Management Controller Configuration Register 1 (PMCCR1)
5.8.2.5 Power Management Controller Configuration Register 2 (PMCCR2)
5.8.3 Functional Description
5.8.3.1 Dynamic Power Management
5.8.3.2 Shutting Down Unused Blocks
5.8.3.3 Software-Controlled Power-Down States
5.8.3.4 Software-Controlled Power Supply Switching
5.8.3.5 Support of PCI Power Management Interface Specification
5.8.3.6 Exiting Core and System Low Power States
5.8.3.7 MPC8313E-Specific PMC Low Power States
5.8.4 Initialization/Application Information
5.8.4.1 Core Disable in Low Power Mode
Chapter 6 Arbiter and Bus Monitor
6.1 Arbiter Overview
6.1.1 Coherent System Bus Overview
6.2 Arbiter Memory Map/Register Definition
6.2.1 Arbiter Configuration Register (ACR)
6.2.2 Arbiter Timers Register (ATR)
6.2.3 Arbiter Event Enable Register (AEER)
6.2.4 Arbiter Event Register (AER)
6.2.5 Arbiter Interrupt Definition Register (AIDR)
6.2.6 Arbiter Mask Register (AMR)
6.2.7 Arbiter Event Attributes Register (AEATR)
6.2.8 Arbiter Event Address Register (AEADR)
6.2.9 Arbiter Event Response Register (AERR)
6.3 Functional Description
6.3.1 Arbitration Policy
6.3.1.1 Address Bus Arbitration with PRIORITY[0:1]
6.3.1.2 Address Bus Arbitration with REPEAT
6.3.1.3 Address Bus Arbitration After ARTRY
6.3.1.4 Address Bus Parking
6.3.1.5 Data Bus Arbitration
6.3.2 Bus Error Detection
6.3.2.1 Address Time Out
6.3.2.2 Data Time Out
6.3.2.3 Transfer Error
6.3.2.4 Address Only Transaction Type
6.3.2.5 Reserved Transaction Type
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type
6.4 Initialization/Applications Information
6.4.1 Initialization Sequence
6.4.2 Error Handling Sequence
Chapter 7 e300 Processor Core Overview
7.1 e300c3 Overview
7.1.1 e300c3 Features
7.1.2 Instruction Unit
7.1.2.1 Instruction Queue and Dispatch Unit
7.1.2.2 Branch Processing Unit (BPU)
7.1.3 Independent Execution Units
7.1.3.1 Integer Unit (IU)
7.1.3.2 Floating-Point Unit (FPU)
7.1.3.3 Load/Store Unit (LSU)
7.1.3.4 System Register Unit (SRU)
7.1.4 Completion Unit
7.1.5 Memory Subsystem Support
7.1.5.1 Memory Management Units (MMUs)
7.1.5.2 Cache Units
7.1.6 Bus Interface Unit (BIU)
7.1.7 System Support Functions
7.1.7.1 Power Management
7.1.7.2 Time Base/Decrementer
7.1.7.3 JTAG Test and Debug Interface
7.1.7.4 Clock Multiplier
7.1.7.5 Core Performance Monitor
7.2 PowerPC Architecture Implementation
7.3 Implementation-Specific Information
7.3.1 Register Model
7.3.1.1 UISA Registers
7.3.1.2 VEA Registers
7.3.1.3 OEA Registers
7.3.2 Instruction Set and Addressing Modes
7.3.2.1 PowerPC Instruction Set and Addressing Modes
7.3.2.2 Implementation-Specific Instruction Set
7.3.3 Cache Implementation
7.3.3.1 PowerPC Cache Characteristics
7.3.3.2 Implementation-Specific Cache Organization
7.3.3.3 Instruction and Data Cache Way-Locking
7.3.4 Interrupt Model
7.3.4.1 PowerPC Interrupt Model
7.3.4.2 Implementation-Specific Interrupt Model
7.3.5 Memory Management
7.3.5.1 PowerPC Memory Management
7.3.5.2 Implementation-Specific Memory Management
7.3.6 Instruction Timing
7.3.7 Core Interface
7.3.7.1 Memory Accesses
7.3.7.2 Signals
7.3.8 Debug Features
7.3.8.1 Breakpoint Signaling
7.4 Differences Between Cores
Chapter 8 Integrated Programmable Interrupt Controller (IPIC)
8.1 IPIC Introduction
8.2 IPIC Features
8.3 IPIPC Modes of Operation
8.3.1 Core Enable Mode
8.3.2 Core Disable Mode
8.4 IPIC External Signal Description
8.4.1 IPIC External Signals Overview
8.4.2 IPIC Detailed Signal Descriptions
8.5 IPIC Memory Map/Register Definition
8.5.1 System Global Interrupt Configuration Register (SICFR)
8.5.2 System Global Interrupt Vector Register (SIVCR)
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L)
8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)
8.5.5 System Internal Interrupt Group D Priority Register (SIPRR_D)
8.5.6 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)
8.5.7 System Internal Interrupt Control Register (SICNR)
8.5.8 System External Interrupt Pending Register (SEPNR)
8.5.9 System Mixed Interrupt Group A Priority Register (SMPRR_A)
8.5.10 System Mixed Interrupt Group B Priority Register (SMPRR_B)
8.5.11 System External Interrupt Mask Register (SEMSR)
8.5.12 System External Interrupt Control Register (SECNR)
8.5.13 System Error Status Register (SERSR)
8.5.14 System Error Mask Register (SERMR)
8.5.15 System Error Control Register (SERCR)
8.5.16 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)
8.5.17 System External Interrupt Force Register (SEFCR)
8.5.18 System Error Force Register (SERFR)
8.5.19 System Critical Interrupt Vector Register (SCVCR)
8.5.20 System Management Interrupt Vector Register (SMVCR)
8.6 Functional Description
8.6.1 Interrupt Types
8.6.2 Interrupt Configuration
8.6.3 Internal Interrupts Group Relative Priority
8.6.4 Mixed Interrupts Group Relative Priority
8.6.5 Highest Priority Interrupt
8.6.6 Interrupt Source Priorities
8.6.7 Masking Interrupt Sources
8.6.8 Interrupt Vector Generation and Calculation
8.6.9 Machine Check Interrupts
Chapter 9 DDR Memory Controller
9.1 Introduction
9.2 Features
9.2.1 Modes of Operation
9.3 External Signal Descriptions
9.3.1 Signals Overview
9.3.2 Detailed Signal Descriptions
9.3.2.1 Memory Interface Signals
9.3.2.2 Clock Interface Signals
9.3.2.3 Debug Signals
9.4 Memory Map/Register Definition
9.4.1 Register Descriptions
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)
9.4.1.2 Chip Select Configuration (CSn_CONFIG)
9.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)
9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)
9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)
9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)
9.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)
9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT)
9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)
9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)
9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)
9.5 Functional Description
9.5.1 DDR SDRAM Interface Operation
9.5.1.1 Supported DDR SDRAM Organizations
9.5.2 DDR SDRAM Address Multiplexing
9.5.3 JEDEC Standard DDR SDRAM Interface Commands
9.5.4 DDR SDRAM Interface Timing
9.5.4.1 Clock Distribution
9.5.5 DDR SDRAM Mode-Set Command Timing
9.5.6 DDR SDRAM Registered DIMM Mode
9.5.7 DDR SDRAM Write Timing Adjustments
9.5.8 DDR SDRAM Refresh
9.5.8.1 DDR SDRAM Refresh Timing
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes
9.5.9 DDR Data Beat Ordering
9.5.10 Page Mode and Logical Bank Retention
9.6 Initialization/Application Information
9.6.1 Programming Differences between Memory Types
9.6.2 DDR SDRAM Initialization Sequence
Chapter 10 Enhanced Local Bus Controller
10.1 Introduction
10.1.1 Overview
10.1.2 Features
10.1.3 Modes of Operation
10.1.3.1 eLBC Bus Clock and Clock Ratios
10.1.3.2 Source ID Debug Mode
10.2 External Signal Descriptions
10.3 Memory Map/Register Definition
10.3.1 Register Descriptions
10.3.1.1 Base Registers (BR0-BR3)
10.3.1.2 Option Registers (OR0-OR3)
10.3.1.3 UPM Memory Address Register (MAR)
10.3.1.4 UPM Mode Registers (MxMR)
10.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR)
10.3.1.6 UPM/FCM Data Register (MDR)
10.3.1.7 Special Operation Initiation Register (LSOR)
10.3.1.8 UPM Refresh Timer (LURT)
10.3.1.9 Transfer Error Status Register (LTESR)
10.3.1.10 Transfer Error Check Disable Register (LTEDR)
10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR)
10.3.1.12 Transfer Error Attributes Register (LTEATR)
10.3.1.13 Transfer Error Address Register (LTEAR)
10.3.1.14 Transfer Error ECC Register (LTECCR)
10.3.1.15 Local Bus Configuration Register (LBCR)
10.3.1.16 Clock Ratio Register (LCRR)
10.3.1.17 Flash Mode Register (FMR)
10.3.1.18 Flash Instruction Register (FIR)
10.3.1.19 Flash Command Register (FCR)
10.3.1.20 Flash Block Address Register (FBAR)
10.3.1.21 Flash Page Address Register (FPAR)
10.3.1.22 Flash Byte Count Register (FBCR)
10.3.1.23 Flash ECC Blockn Register (FECC0-FECC3)
10.4 Functional Description
10.4.1 Basic Architecture
10.4.1.1 Address and Address Space Checking
10.4.1.2 External Address Latch Enable Signal (LALE)
10.4.1.3 Data Transfer Acknowledge (TA)
10.4.1.4 Data Buffer Control (LBCTL)
10.4.1.5 Atomic Operation
10.4.1.6 Bus Monitor
10.4.2 General-Purpose Chip-Select Machine (GPCM)
10.4.2.1 GPCM Read Signal Timing
10.4.2.2 GPCM Write Signal Timing
10.4.2.3 Chip-Select Assertion Timing
10.4.2.4 External Access Termination (LGTA)
10.4.2.5 GPCM Boot Chip-Select Operation
10.4.3 Flash Control Machine (FCM)
10.4.3.1 FCM Buffer RAM
10.4.3.2 Programming FCM
10.4.3.3 FCM Signal Timing
10.4.3.4 FCM Boot Chip-Select Operation
10.4.4 User-Programmable Machines (UPMs)
10.4.4.1 UPM Requests
10.4.4.2 Programming the UPMs
10.4.4.3 UPM Signal Timing
10.4.4.4 RAM Array
10.4.4.5 Extended Hold Time on Read Accesses
10.5 Initialization/Application Information
10.5.1 Interfacing to Peripherals in Different Address Modes
10.5.1.1 Multiplexed Address/Data Bus for 26-Bit Addressing
10.5.1.2 Non-Multiplexed Address and Data Buses
10.5.1.3 Peripheral Hierarchy on the Local Bus for High Bus Speeds
10.5.1.4 GPCM Timings
10.5.2 Bus Turnaround
10.5.2.1 Address Phase after Previous Read
10.5.2.2 Read Data Phase after Address Phase
10.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks
10.5.2.4 UPM Cycles with Additional Address Phases
10.5.3 Interface to Different Port-Size Devices
10.5.4 Command Sequence Examples for NAND Flash EEPROM
10.5.4.1 NAND Flash Soft Reset Command Sequence Example
10.5.4.2 NAND Flash Read Status Command Sequence Example
10.5.4.3 NAND Flash Read Identification Command Sequence Example
10.5.4.4 NAND Flash Page Read Command Sequence Example
10.5.4.5 NAND Flash Block Erase Command Sequence Example
10.5.4.6 NAND Flash Program Command Sequence Example
10.5.5 Interfacing to Fast-Page Mode DRAM Using UPM
10.5.6 Interfacing to ZBT SRAM Using UPM
Chapter 11 Sequencer
11.1 Sequencer Overview
11.1.1 Sequencer Features
11.2 Sequencer External Signal Description
11.3 Sequencer Memory Map/Register Definition
11.4 Sequencer Register Descriptions
11.4.1 PCI Outbound Translation Address Registers (POTARn)
11.4.2 PCI Outbound Base Address Registers (POBARn)
11.4.3 PCI Outbound Comparison Mask Registers (POCMRn)
11.4.4 Power Management Control Register (PMCR)
11.4.5 Discard Timer Control Register (DTCR)
11.5 Functional Description
11.5.1 Transaction Forwarding
11.5.1.1 Transactions from the Coherency System Bus (CSB) Port
11.5.1.2 Transactions from the PCI Port
11.5.1.3 Transactions from the DMA Port
11.5.2 PCI Outbound Address Translation
11.5.3 Transaction Ordering
Chapter 12 DMA/Messaging Unit
12.1 DMA Features
12.2 DMA Memory Map/Register Definition
12.3 DMA Register Descriptions
12.3.1 Outbound Message Interrupt Status Register (OMISR)
12.3.2 Outbound Message Interrupt Mask Register (OMIMR)
12.3.3 Inbound Message Registers (IMR0-IMR1)
12.3.4 Outbound Message Registers (OMR0-OMR1)
12.3.5 Doorbell Registers
12.3.5.1 Outbound Doorbell Register (ODR)
12.3.5.2 Inbound Doorbell Register (IDR)
12.3.6 Inbound Message Interrupt Status Register (IMISR)
12.3.7 Inbound Message Interrupt Mask Register (IMIMR)
12.3.8 DMA Registers
12.3.8.1 DMA Mode Register (DMAMRn)
12.3.8.2 DMA Status Register (DMASRn)
12.3.8.3 DMA Current Descriptor Address Register (DMACDARn)
12.3.8.4 DMA Source Address Register (DMASARn)
12.3.8.5 DMA Destination Address Register (DMADARn)
12.3.8.6 DMA Byte Count Register (DMABCRn)
12.3.8.7 DMA Next Descriptor Address Register (DMANDARn)
12.3.8.8 DMA General Status Register (DMAGSR)
12.4 Functional Description
12.4.1 Message Unit
12.4.1.1 Messaging Registers (IMR0-IMR1, OMR0-OMR1)
12.4.1.2 Doorbell Registers (IDR and ODR)
12.4.2 DMA Controller
12.4.3 DMA Operation
12.4.3.1 DMA Coherency
12.4.3.2 Halt and Error Conditions
12.4.4 DMA Segment Descriptors
12.4.4.1 Descriptor in Big-Endian Mode
12.4.4.2 Descriptor in Little-Endian Mode
12.5 Initialization/Application Information
12.5.1 Initialization Steps in Direct Mode
12.5.2 Initialization Steps in Chaining Mode
Chapter 13 PCI Bus Interface
13.1 PCI Introduction
13.1.1 PCI Features
13.1.2 PCI Modes of Operation
13.1.2.1 Host/Agent Mode Configuration
13.1.2.2 PCI Arbiter Configuration
13.2 PCI External Signal Description
13.3 PCI Memory Map/Register Definitions
13.3.1 PCI Configuration Access Registers
13.3.1.1 PCI_CONFIG_ADDRESS
13.3.1.2 PCI_CONFIG_DATA
13.3.1.3 PCI Interrupt Acknowledge Register (PCI_INT_ACK)
13.3.2 PCI Memory-Mapped Control and Status Registers
13.3.2.1 PCI Error Status Register (PCI_ESR)
13.3.2.2 PCI Error Capture Disable Register (PCI_ECDR)
13.3.2.3 PCI Error Enable Register (PCI_EER)
13.3.2.4 PCI Error Attributes Capture Register (PCI_EATCR)
13.3.2.5 PCI Error Address Capture Register (PCI_EACR)
13.3.2.6 PCI Error Extended Address Capture Register (PCI_EEACR)
13.3.2.7 PCI Error Data Low Capture Register (PCI_EDLCR)
13.3.2.8 PCI General Control Register (PCI_GCR)
13.3.2.9 PCI Error Control Register (PCI_ECR)
13.3.2.10 PCI General Status Register (PCI_GSR)
13.3.2.11 PCI Inbound Translation Address Registers (PITARn)
13.3.2.12 PCI Inbound Base Address Registers (PIBARn)
13.3.2.13 PCI Inbound Extended Base Address Registers (PIEBARn)
13.3.2.14 PCI Inbound Window Attribute Registers (PIWARn)
13.3.3 PCI Configuration Space Registers
13.3.3.1 Vendor ID Configuration Register
13.3.3.2 Device ID Configuration Register
13.3.3.3 PCI Command Configuration Register
13.3.3.4 PCI Status Configuration Register
13.3.3.5 Revision ID Configuration Register
13.3.3.6 Standard Programming Interface Configuration Register
13.3.3.7 Subclass Code Configuration Register
13.3.3.8 Base Class Code Configuration Register
13.3.3.9 Cache Line Size Configuration Register
13.3.3.10 Latency Timer Configuration Register
13.3.3.11 Header Type Configuration Register
13.3.3.12 BIST Control Configuration Register
13.3.3.13 PIMMR Base Address Configuration Register
13.3.3.14 GPL Base Address Register 0
13.3.3.15 GPL Base Address Registers 1-2
13.3.3.16 GPL Extended Base Address Registers 1-2
13.3.3.17 Subsystem Vendor ID Configuration Register
13.3.3.18 Subsystem Device ID Configuration Register
13.3.3.19 Capabilities Pointer Configuration Register
13.3.3.20 Interrupt Line Configuration Register
13.3.3.21 Interrupt Pin Configuration Register
13.3.3.22 Minimum Grant Configuration Register
13.3.3.23 Maximum Latency Configuration Register
13.3.3.24 PCI Function Configuration Register
13.3.3.25 PCI Arbiter Control Register (PCIACR)
13.3.3.26 Hot Swap Register Block
13.3.3.27 PCI Power Management Register 0 (PCIPMR0)
13.3.3.28 PCI Power Management Register 1 (PCIPMR1)
13.4 Functional Description
13.4.1 PCI Bus Arbitration
13.4.1.1 Bus Parking
13.4.1.2 Arbitration Algorithm
13.4.1.3 Broken Master Lock-Out
13.4.1.4 Master Latency Timer
13.4.2 Bus Commands
13.4.3 PCI Protocol Fundamentals
13.4.3.1 Basic Transfer Control
13.4.3.2 Addressing
13.4.3.3 Device Selection
13.4.3.4 Byte Enable Signals
13.4.3.5 Bus Driving and Turnaround
13.4.3.6 Bus Transactions
13.4.3.7 Read and Write Transactions
13.4.3.8 Transaction Termination
13.4.4 Other Bus Operations
13.4.4.1 Fast Back-to-Back Transactions
13.4.4.2 Dual Address Cycles
13.4.4.3 Data Streaming
13.4.4.4 Host Mode Configuration Access
13.4.4.5 Agent Mode Configuration Access
13.4.4.6 Special Cycle Command
13.4.4.7 Interrupt Acknowledge
13.4.5 Error Functions
13.4.5.1 Parity
13.4.5.2 Error Reporting
13.4.6 PCI Inbound Address Translation
13.4.7 CompactPCI Hot Swap Specification Support
13.4.8 Byte Ordering
13.4.8.1 Byte Order for Configuration Transactions
13.5 Initialization/Application Information
13.5.1 Initialization Sequence for Host Mode
13.5.2 Initialization Sequence for Agent Mode
Chapter 14 Security Engine (SEC) 2.2
14.1 SEC 2.2 Architecture Overview
14.1.1 Descriptors
14.1.2 Execution Units (EUs)
14.1.2.1 Data Encryption Standard Execution Unit (DEU)
14.1.2.2 Advanced Encryption Standard Execution Unit (AESU)
14.1.2.3 Message Digest Execution Unit (MDEU)
14.1.3 Channel
14.1.4 SEC Controller
14.1.4.1 Channel-Controlled Access
14.1.4.2 Host-Controlled Access
14.2 Configuration of Internal Memory Space
14.3 Descriptor Overview
14.3.1 Descriptor Structure
14.3.2 Descriptor Format: Header Dword
14.3.2.1 Selecting Execution Units-EU_SEL0 and EU_SEL1
14.3.2.2 Selecting Descriptor Type-DESC_TYPE
14.3.3 Descriptor Format: Pointer Dwords
14.3.4 Link Table Format
14.3.5 Descriptor Types
14.4 Execution Units
14.4.1 Data Encryption Standard Execution Unit (DEU)
14.4.1.1 DEU Mode Register (DEUMR)
14.4.1.2 DEU Key Size Register (DEUKSR)
14.4.1.3 DEU Data Size Register (DEUDSR)
14.4.1.4 DEU Reset Control Register (DEURCR)
14.4.1.5 DEU Status Register (DEUSR)
14.4.1.6 DEU Interrupt Status Register (DEUISR)
14.4.1.7 DEU Interrupt Control Register (DEUICR)
14.4.1.8 DEU End-of-Message Register (DEUEMR)
14.4.1.9 DEU IV Register (DEUIV)
14.4.1.10 DEU Key Registers (DEUKn)
14.4.1.11 DEU FIFOs
14.4.2 Message Digest Execution Unit (MDEU)
14.4.2.1 MDEU Mode Register (MDEUMR)
14.4.2.2 Recommended Settings for MDEUMR
14.4.2.3 MDEU Key Size Register (MDEUKSR)
14.4.2.4 MDEU Data Size Register (MDEUDSR)
14.4.2.5 MDEU Reset Control Register (MDEURCR)
14.4.2.6 MDEU Status Register (MDEUSR)
14.4.2.7 MDEU Interrupt Status Register (MDEUISR)
14.4.2.8 MDEU Interrupt Control Register (MDEUICR)
14.4.2.9 MDEU ICV Size Register
14.4.2.10 MDEU End-of-Message Register (MDEUEMR)
14.4.2.11 MDEU Context Registers
14.4.2.12 MDEU Key Registers
14.4.2.13 MDEU FIFOs
14.4.3 Advanced Encryption Standard Execution Unit (AESU)
14.4.3.1 AESU Mode Register (AESUMR)
14.4.3.2 AESU Key Size Register (AESUKSR)
14.4.3.3 AESU Data Size Register (AESUDSR)
14.4.3.4 AESU Reset Control Register (AESURCR)
14.4.3.5 AESU Status Register (AESUSR)
14.4.3.6 AESU Interrupt Status Register (AESUISR)
14.4.3.7 AESU Interrupt Control Register (AESUICR)
14.4.3.8 AESU End-of-Message Register (AESUEMR)
14.4.3.9 AESU Context Registers
14.5 Channel
14.5.1 Channel Registers
14.5.1.1 Crypto-Channel Configuration Register (CCCR)
14.5.1.2 Crypto-Channel Pointer Status Register (CCPSR)
14.5.1.3 Crypto-Channel Current Descriptor Pointer Register (CDPR)
14.5.1.4 Fetch FIFO (FF)
14.5.1.5 Descriptor Buffer (DB)
14.5.2 Channel Interrupts
14.5.2.1 Channel Done Interrupt
14.5.2.2 Channel Error Interrupt
14.5.2.3 Channel Reset
14.6 Controller
14.6.1 Assignment of EUs to Channel
14.6.2 Bus Interface
14.6.2.1 Arbitration for Use of the Controller and Buses
14.6.2.2 Master Read
14.6.2.3 Master Write
14.6.3 Controller Interrupts
14.6.4 Controller Registers
14.6.4.1 EU Assignment Status Register (EUASR)
14.6.4.2 Interrupt Mask Register (IMR)
14.6.4.3 Interrupt Status Register (ISR)
14.6.4.4 Interrupt Clear Register (ICR)
14.6.4.5 Identification Register (ID)
14.6.4.6 IP Block Revision Register
14.6.4.7 Master Control Register (MCR)
14.6.5 Snooping by Caches
14.6.6 Interrupts
14.7 Power Saving Mode
Chapter 15 Enhanced Three-Speed Ethernet Controllers
15.1 Overview
15.2 Features
15.3 Modes of Operation
15.4 External Signals Description
15.4.1 Detailed Signal Descriptions
15.5 Memory Map/Register Definition
15.5.1 Top-Level Module Memory Map
15.5.2 Detailed Memory Map
15.5.3 Memory-Mapped Register Descriptions
15.5.3.1 eTSEC General Control and Status Registers
15.5.3.2 eTSEC Transmit Control and Status Registers
15.5.3.3 eTSEC Receive Control and Status Registers
15.5.3.4 MAC Functionality
15.5.3.5 MAC Registers
15.5.3.6 MIB Registers
15.5.3.7 Hash Function Registers
15.5.3.8 DMA Attribute Registers
15.5.3.9 Lossless Flow Control Configuration Registers
15.5.3.10 IEEE 1588-Compatible Timestamping Registers
15.5.4 Ten-Bit Interface (TBI)
15.5.4.1 TBI Transmit Process
15.5.4.2 TBI Receive Process
15.5.4.3 TBI MII Set Register Descriptions
15.6 Functional Description
15.6.1 Connecting to Physical Interfaces on Ethernet
15.6.1.1 Media-Independent Interface (MII)
15.6.1.2 Reduced Media-Independent Interface (RMII)
15.6.1.3 Reduced Gigabit Media-Independent Interface (RGMII)
15.6.1.4 Reduced Ten-Bit Interface (RTBI)
15.6.1.5 Serial Gigabit Media-Independent Interface (SGMII)
15.6.1.6 Ethernet Physical Interfaces Signal Summary
15.6.2 Gigabit Ethernet Controller Channel Operation
15.6.2.1 Initialization Sequence
15.6.2.2 Soft Reset and Reconfiguring Procedure
15.6.2.3 Gigabit Ethernet Frame Transmission
15.6.2.4 Gigabit Ethernet Frame Reception
15.6.2.5 Ethernet Preamble Customization
15.6.2.6 RMON Support
15.6.2.7 Frame Recognition
15.6.2.8 Magic Packet Mode
15.6.2.9 Flow Control
15.6.2.10 Interrupt Handling
15.6.2.11 Inter-Frame Gap Time
15.6.2.12 Internal and External Loop Back
15.6.2.13 Error-Handling Procedure
15.6.3 TCP/IP Off-Load
15.6.3.1 Frame Control Blocks
15.6.3.2 Transmit Path Off-Load and Tx PTP Packet Parsing
15.6.3.3 Receive Path Off-Load
15.6.4 Quality of Service (QoS) Provision
15.6.4.1 Receive Parser
15.6.4.2 Receive Queue Filer
15.6.4.3 Transmission Scheduling
15.6.5 Lossless Flow Control
15.6.5.1 Back Pressure Determination through Free Buffers
15.6.5.2 Software Use of Hardware-Initiated Back Pressure
15.6.6 Hardware Assist for IEEE 1588-Compatible Timestamping
15.6.6.1 Features
15.6.6.2 Timer Logic Overview
15.6.6.3 Time-Stamp Insertion on the Received Packets
15.6.6.4 PTP Packet Parsing
15.6.6.5 Time-Stamp Insertion on Transmit Packets
15.6.6.6 Tx PTP Packet Parsing
15.6.7 Buffer Descriptors
15.6.7.1 Data Buffer Descriptors
15.6.7.2 Transmit Data Buffer Descriptors (TxBD)
15.6.7.3 Receive Buffer Descriptors (RxBD)
15.7 Initialization/Application Information
15.7.1 Interface Mode Configuration
15.7.1.1 MII Interface Mode
15.7.1.2 RGMII Interface Mode
15.7.1.3 RMII Interface Mode
15.7.1.4 RTBI Interface Mode
15.7.1.5 SGMII Interface Support
Chapter 16 Universal Serial Bus Interface
16.1 Introduction
16.1.1 Overview
16.1.2 Features
16.1.3 Modes of Operation
16.2 External Signals
16.2.1 UTMI Interface
16.2.2 ULPI Interface
16.2.3 PHY Clocks
16.3 Memory Map/Register Definitions
16.3.1 Capability Registers
16.3.1.1 Capability Registers Length (CAPLENGTH)
16.3.1.2 Host Controller Interface Version (HCIVERSION)
16.3.1.3 Host Controller Structural Parameters (HCSPARAMS)
16.3.1.4 Host Controller Capability Parameters (HCCPARAMS)
16.3.1.5 Device Controller Interface Version (DCIVERSION)-Non-EHCI
16.3.1.6 Device Controller Capability Parameters (DCCPARAMS)-Non-EHCI
16.3.2 Operational Registers
16.3.2.1 USB Command Register (USBCMD)
16.3.2.2 USB Status Register (USBSTS)
16.3.2.3 USB Interrupt Enable Register (USBINTR)
16.3.2.4 Frame Index Register (FRINDEX)
16.3.2.5 Control Data Structure Segment Register (CTRLDSSEGMENT)
16.3.2.6 Periodic Frame List Base Address Register (PERIODICLISTBASE)
16.3.2.7 Device Address Register (DEVICEADDR)-Non-EHCI
16.3.2.8 Current Asynchronous List Address Register (ASYNCLISTADDR)
16.3.2.9 Endpoint List Address Register (ENDPOINTLISTADDR)-Non-EHCI
16.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)-Non-EHCI
16.3.2.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)-Non-EHCI
16.3.2.12 ULPI Register Access (ULPI VIEWPORT)
16.3.2.13 Configure Flag Register (CONFIGFLAG)
16.3.2.14 Port Status and Control Register (PORTSC)
16.3.2.15 On-The-Go Status and Control (OTGSC)-Non-EHCI
16.3.2.16 USB Mode Register (USBMODE)-Non-EHCI
16.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)-Non-EHCI
16.3.2.18 Endpoint Initialization Register (ENDPTPRIME)-Non-EHCI
16.3.2.19 Endpoint Flush Register (ENDPTFLUSH)-Non-EHCI
16.3.2.20 Endpoint Status Register (ENDPTSTATUS)-Non-EHCI
16.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)-Non-EHCI
16.3.2.22 Endpoint Control Register 0 (ENDPTCTRL0)-Non-EHCI
16.3.2.23 Endpoint Control Register n (ENDPTCTRLn)-Non-EHCI
16.3.2.24 SNOOP1 and SNOOP2-Non-EHCI
16.3.2.25 Age Count Threshold Register (AGE_CNT_THRESH)-Non-EHCI
16.3.2.26 Priority Control Register (PRI_CTRL)-Non-EHCI
16.3.2.27 System Interface Control Register (SI_CTRL)-Non-EHCI
16.3.2.28 USB General Purpose Register (CONTROL)-Non-EHCI
16.4 Functional Description
16.4.1 System Interface
16.4.2 DMA Engine
16.4.3 FIFO RAM Controller
16.4.4 PHY Interface
16.5 Host Data Structures
16.5.1 Periodic Frame List
16.5.2 Asynchronous List Queue Head Pointer
16.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)
16.5.3.1 Next Link Pointer
16.5.3.2 iTD Transaction Status and Control List
16.5.3.3 iTD Buffer Page Pointer List (Plus)
16.5.4 Split Transaction Isochronous Transfer Descriptor (siTD)
16.5.4.1 Next Link Pointer
16.5.4.2 siTD Endpoint Capabilities/Characteristics
16.5.4.3 siTD Transfer State
16.5.4.4 siTD Buffer Pointer List (Plus)
16.5.4.5 siTD Back Link Pointer
16.5.5 Queue Element Transfer Descriptor (qTD)
16.5.5.1 Next qTD Pointer
16.5.5.2 Alternate Next qTD Pointer
16.5.5.3 qTD Token
16.5.5.4 qTD Buffer Page Pointer List
16.5.6 Queue Head
16.5.6.1 Queue Head Horizontal Link Pointer
16.5.6.2 Endpoint Capabilities/Characteristics
16.5.6.3 Transfer Overlay
16.5.7 Periodic Frame Span Traversal Node (FSTN)
16.5.7.1 FTSN Normal Path Pointer
16.5.7.2 FSTN Back Path Link Pointer
16.6 Host Operations
16.6.1 Host Controller Initialization
16.6.2 Power Port
16.6.3 Reporting Over-Current
16.6.4 Suspend/Resume
16.6.4.1 Port Suspend/Resume
16.6.5 Schedule Traversal Rules
16.6.6 Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
16.6.7 Periodic Schedule
16.6.8 Managing Isochronous Transfers Using iTDs
16.6.8.1 Host Controller Operational Model for iTDs
16.6.8.2 Software Operational Model for iTDs
16.6.9 Asynchronous Schedule
16.6.9.1 Adding Queue Heads to Asynchronous Schedule
16.6.9.2 Removing Queue Heads from Asynchronous Schedule
16.6.9.3 Empty Asynchronous Schedule Detection
16.6.9.4 Asynchronous Schedule Traversal: Start Event
16.6.9.5 Reclamation Status Bit (USBSTS Register)
16.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads
16.6.10.1 Buffer Pointer List Use for Data Streaming with qTDs
16.6.10.2 Adding Interrupt Queue Heads to the Periodic Schedule
16.6.10.3 Managing Transfer Complete Interrupts from Queue Heads
16.6.11 Ping Control
16.6.12 Split Transactions
16.6.12.1 Split Transactions for Asynchronous Transfers
16.6.12.2 Split Transaction Interrupt
16.6.12.3 Split Transaction Isochronous
16.6.13 Port Test Modes
16.6.14 Interrupts
16.6.14.1 Transfer/Transaction Based Interrupts
16.6.14.2 Host Controller Event Interrupts
16.7 Device Data Structures
16.7.1 Endpoint Queue Head
16.7.1.1 Endpoint Capabilities/Characteristics
16.7.1.2 Transfer Overlay
16.7.1.3 Current dTD Pointer
16.7.1.4 Setup Buffer
16.7.2 Endpoint Transfer Descriptor (dTD)
16.8 Device Operational Model
16.8.1 Device Controller Initialization
16.8.2 Port State and Control
16.8.2.1 Bus Reset
16.8.2.2 Suspend/Resume
16.8.3 Managing Endpoints
16.8.3.1 Endpoint Initialization
16.8.3.2 Data Toggle
16.8.3.3 Device For Packet Transfers
16.8.3.4 Interrupt/Bulk Endpoint Operational Model
16.8.3.5 Control Endpoint Operation Model
16.8.3.6 Isochronous Endpoint Operational Model
16.8.4 Managing Queue Heads
16.8.4.1 Queue Head Initialization
16.8.4.2 Operational Model for Setup Transfers
16.8.5 Managing Transfers with Transfer Descriptors
16.8.5.1 Software Link Pointers
16.8.5.2 Building a Transfer Descriptor
16.8.5.3 Executing a Transfer Descriptor
16.8.5.4 Transfer Completion
16.8.5.5 Flushing/Depriming an Endpoint
16.8.5.6 Device Error Matrix
16.8.6 Servicing Interrupts
16.8.6.1 High-Frequency Interrupts
16.8.6.2 Low-Frequency Interrupts
16.8.6.3 Error Interrupts
16.9 Deviations from the EHCI Specifications
16.9.1 Embedded Transaction Translator Function
16.9.1.1 Capability Registers
16.9.1.2 Operational Registers
16.9.1.3 Discovery
16.9.1.4 Data Structures
16.9.1.5 Operational Model
16.9.2 Device Operation
16.9.3 Non-Zero Fields the Register File
16.9.4 SOF Interrupt
16.9.5 Embedded Design
16.9.5.1 Frame Adjust Register
16.9.6 Miscellaneous Variations from EHCI
16.9.6.1 Discovery
16.10 Timing Diagrams
Chapter 17 I2C Interfaces
17.1 I2C Introduction
17.1.1 I2C Features
17.1.2 I2C Modes of Operation
17.2 I2C External Signal Descriptions
17.2.1 I2C Signal Overview
17.2.2 I2C Detailed Signal Descriptions
17.3 I2C Memory Map/Register Definition
17.3.1 I2C Register Descriptions
17.3.1.1 I2Cn Address Register (I2CnADR)
17.3.1.2 I2Cn Frequency Divider Register (I2CnFDR)
17.3.1.3 I2Cn Control Register (I2CnCR)
17.3.1.4 I2Cn Status Register (I2CnSR)
17.3.1.5 I2Cn Data Register (I2CnDR)
17.3.1.6 Digital Filter Sampling Rate Register (I2CnDFSRR)
17.4 Functional Description
17.4.1 Transaction Protocol
17.4.1.1 START Condition
17.4.1.2 Slave Address Transmission
17.4.1.3 Repeated START Condition
17.4.1.4 STOP Condition
17.4.1.5 Protocol Implementation Details
17.4.1.6 Address Compare-Implementation Details
17.4.2 Arbitration Procedure
17.4.2.1 Arbitration Control
17.4.3 Handshaking
17.4.4 Clock Control
17.4.4.1 Clock Synchronization
17.4.4.2 Input Synchronization and Digital Filter
17.4.4.3 Clock Stretching
17.4.5 Boot Sequencer Mode
17.4.5.1 Using the Boot Sequencer for Reset Configuration
17.4.5.2 EEPROM Calling Address
17.4.5.3 EEPROM Data Format
17.4.5.4 Boot Sequencer Done Indication
17.5 Initialization/Application Information
17.5.1 Interrupt Service Routine Flowchart
17.5.2 Initialization Sequence
17.5.3 Generation of START
17.5.4 Post-Transfer Software Response
17.5.5 Generation of STOP
17.5.6 Generation of Repeated START
17.5.7 Generation of SCLn When SDAn is Negated
17.5.8 Slave Mode Interrupt Service Routine
17.5.8.1 Slave Transmitter and Received Acknowledge
17.5.8.2 Loss of Arbitration and Forcing of Slave Mode
Chapter 18 DUART
18.1 DUART Overview
18.1.1 DUART Features
18.1.2 DUART Modes of Operation
18.2 DUART External Signal Descriptions
18.2.1 DUART Signal Overview
18.2.2 DUART Detailed Signal Descriptions
18.3 DUART Memory Map/Register Definition
18.3.1 DUART Register Descriptions
18.3.1.1 Receiver Buffer Registers (URBR1 and URBR2)
18.3.1.2 Transmitter Holding Registers (UTHR1 and UTHR2)
18.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
18.3.1.4 Interrupt Enable Registers (UIER1 and UIER2)
18.3.1.5 Interrupt ID Registers (UIIR1 and UIIR2)
18.3.1.6 FIFO Control Registers (UFCR1 and UFCR2)
18.3.1.7 Alternate Function Registers (UAFR1 and UAFR2)
18.3.1.8 Line Control Registers (ULCR1 and ULCR2)
18.3.1.9 MODEM Control Registers (UMCR1 and UMCR2)
18.3.1.10 Line Status Registers (ULSR1 and ULSR2)
18.3.1.11 MODEM Status Registers (UMSR1 and UMSR2)
18.3.1.12 Scratch Registers (USCR1 and USCR2)
18.3.1.13 DMA Status Registers (UDSR1 and UDSR2)
18.4 Functional Description
18.4.1 Serial Interface
18.4.1.1 START Bit
18.4.1.2 Data Transfer
18.4.1.3 Parity Bit
18.4.1.4 STOP Bit
18.4.2 Baud-Rate Generator Logic
18.4.3 Local Loopback Mode
18.4.4 Errors
18.4.4.1 Framing Error
18.4.4.2 Parity Error
18.4.4.3 Overrun Error
18.4.5 FIFO Mode
18.4.5.1 FIFO Interrupts
18.4.5.2 DMA Mode Select
18.4.5.3 Interrupt Control Logic
18.5 DUART Initialization/Application Information
Chapter 19 Serial Peripheral Interface
19.1 Overview
19.2 Introduction
19.2.1 Features
19.2.2 SPI Transmission and Reception Process
19.2.3 Modes of Operation
19.2.3.1 SPI as a Master Device
19.2.3.2 SPI as a Slave Device
19.2.3.3 SPI in Multiple-Master Operation
19.3 External Signal Descriptions
19.3.1 Overview
19.3.2 Detailed Signal Descriptions
19.4 Memory Map/Register Definition
19.4.1 Register Descriptions
19.4.1.1 SPI Mode Register (SPMODE)
19.4.1.2 SPI Event Register (SPIE)
19.4.1.3 SPI Mask Register (SPIM)
19.4.1.4 SPI Command Register (SPCOM)
19.4.1.5 SPI Transmit Data Hold Register (SPITD)
19.4.1.6 SPI Receive Data Hold Register (SPIRD)
19.5 Initialization/Application Information
19.5.1 SPI Master Programming Example
19.5.2 SPI Slave Programming Example
Chapter 20 JTAG/Testing Support
20.1 JTAG Overview
20.2 JTAG Signals
20.2.1 JTAG External Signal Descriptions
20.3 JTAG Registers and Scan Chains
Chapter 21 General Purpose I/O (GPIO)
21.1 Introduction
21.1.1 Overview
21.1.2 Features
21.2 External Signal Description
21.2.1 Signals Overview
21.3 Memory Map/Register Definition
21.3.1 GPIO Direction Register (GPDIR)
21.3.2 GPIO Open Drain Register (GPODR)
21.3.3 GPIO Data Register (GPDAT)
21.3.4 GPIO Interrupt Event Register (GPIER)
21.3.5 GPIO Interrupt Mask Register (GPIMR)
21.3.6 GPIO Interrupt Control Register (GPICR)
Appendix A Revision History
A.1 Changes From Revision 2 to Revision 3
A.2 Changes From Revision 1 to Revision 2
A.3 Changes From Revision 0 to Revision 1
MPC8313E PowerQUICC II Pro
Integrated Processor
Family Reference Manual
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MPC8313E
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Rev. 3
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Semiconductor was negligent regarding the design or manufacture of the part.
Freescale, the Freescale logo, CodeWarrior, ColdFire, PowerQUICC,
StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.
Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ, QUICC Engine, and VortiQa are
trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. The Power Architecture
and Power.org word marks and the Power and Power.org logos and related
marks are trademarks and service marks licensed by Power.org. IEEE 754,
802.1, 802.2, 802.1p, 802.1Q, 802.3, 802.3u, 802.3x, 802.3z, 802.3ab,
802.3ac, 802.11a/g, 802.11b, 802.11i, 802.11n, 1149.1, and 1588 are
registered trademarks of the Institute of Electrical and Electronics
Engineers, Inc. (IEEE). This product is not endorsed or approved by the
IEEE.
© 2010 Freescale Semiconductor, Inc.
Paragraph
Number
Contents
Title
About This Book
Page
Number
Audience ........................................................................................................................ lxxv
Organization................................................................................................................... lxxv
Suggested Reading....................................................................................................... lxxvii
General Information................................................................................................. lxxvii
Related Documentation........................................................................................... lxxviii
Conventions ................................................................................................................ lxxviii
Signal Conventions ....................................................................................................... lxxix
Acronyms and Abbreviations ....................................................................................... lxxix
Chapter 1
Overview
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.5.1
1.2.6
1.2.6.1
1.2.7
1.2.8
1.2.9
1.2.10
1.2.11
1.2.12
1.2.13
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
MPC8313E PowerQUICC II Pro Processor Overview ................................................... 1-1
MPC8313E Architecture Overview................................................................................. 1-7
Power Architecture Core ............................................................................................. 1-7
Security Engine......................................................................................................... 1-10
DDR Memory Controller........................................................................................... 1-10
Dual Enhanced Three-Speed Ethernet Controllers.................................................... 1-11
PCI Controller............................................................................................................ 1-12
PCI Bus Arbitration Unit....................................................................................... 1-13
Universal Serial Bus (USB) 2.0................................................................................. 1-13
USB Dual-Role Controller .................................................................................... 1-14
Enhanced Local Bus Controller (eLBC).................................................................... 1-14
Integrated Programmable Interrupt Controller (IPIC) ............................................... 1-16
Dual I2C Interfaces .................................................................................................... 1-16
DMA Controller......................................................................................................... 1-17
Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-17
Serial Peripheral Interface (SPI)................................................................................ 1-18
System Timers ........................................................................................................... 1-18
Application Examples.................................................................................................... 1-18
Low-End Printer CPU and Interface ASIC................................................................ 1-19
High-End Printer I/O Processor................................................................................. 1-20
IEEE Std. 1588 in Test and Measurement and Industrial Automation ...................... 1-21
IEEE Std. 802.11n WLAN Access Point................................................................... 1-23
Media Server.............................................................................................................. 1-24
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
iii
Paragraph
Number
2.1
2.2
2.3
3.1
3.2
3.3
3.4
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.3
4.2.4
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.2
4.3.2.1
4.3.2.1.1
4.3.2.2
4.3.2.2.1
4.3.2.2.2
4.3.2.2.3
4.3.2.2.4
iv
Contents
Title
Chapter 2
Memory Map
Page
Number
Internal Memory Mapped Registers ................................................................................ 2-1
Accessing IMMR Memory From the Local Processor.................................................... 2-1
Complete IMMR Map ..................................................................................................... 2-1
Chapter 3
Signal Descriptions
Signals Overview ............................................................................................................. 3-1
Configuration Signals Sampled at Reset ....................................................................... 3-29
Output Signal States During Reset ................................................................................ 3-30
External Signal Description ........................................................................................... 3-32
Chapter 4
Reset, Clocking, and Initialization
External Signals ............................................................................................................... 4-1
Reset Signals................................................................................................................ 4-1
Clock Signals ............................................................................................................... 4-3
Functional Description..................................................................................................... 4-4
Reset Operations.......................................................................................................... 4-4
Reset Causes ............................................................................................................ 4-5
Reset Actions ........................................................................................................... 4-5
Power-On Reset Flow.................................................................................................. 4-6
Hard Reset Flow .......................................................................................................... 4-8
Soft Reset Flow............................................................................................................ 4-9
Reset Configuration ......................................................................................................... 4-9
Reset Configuration Signals ........................................................................................ 4-9
Reset Configuration Word Source ......................................................................... 4-10
SYS_CLK_IN Division ......................................................................................... 4-11
Selecting Reset Configuration Input Signals......................................................... 4-11
Reset Configuration Words........................................................................................ 4-12
Reset Configuration Word Low Register (RCWLR)............................................. 4-13
System PLL Configuration................................................................................ 4-14
Reset Configuration Word High Register (RCWHR)............................................ 4-15
PCI Host/Agent Configuration .......................................................................... 4-16
Boot Memory Space (BMS) .............................................................................. 4-17
Boot Sequencer Configuration .......................................................................... 4-17
Boot ROM Location .......................................................................................... 4-18
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Paragraph
Number
4.3.2.2.5
4.3.2.2.6
4.3.2.2.7
4.3.2.2.8
4.3.3
4.3.3.1
4.3.3.1.1
4.3.3.2
4.3.3.2.1
4.3.3.2.2
4.3.3.2.3
4.3.3.2.4
4.3.3.3
4.3.3.3.1
4.4
4.4.1
4.4.1.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.5
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.5.1.4
4.5.1.5
4.5.1.6
4.5.1.7
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
Contents
Title
Page
Number
eTSEC1 Mode ................................................................................................... 4-19
eTSEC2 Mode ................................................................................................... 4-20
e300 Core True Little-Endian............................................................................ 4-21
LALE Configuration.......................................................................................... 4-21
Loading the Reset Configuration Words ................................................................... 4-21
Loading from Local Bus........................................................................................ 4-21
Local Bus Controller Setting ............................................................................. 4-22
Loading from I2C EEPROM ................................................................................. 4-23
Using the Boot Sequencer Reset Configuration ................................................ 4-23
EEPROM Calling Address ................................................................................ 4-23
EEPROM Data Format in Reset Configuration Mode ...................................... 4-24
Reset Configuration Load Fail .......................................................................... 4-26
Default Reset Configuration Words....................................................................... 4-26
Examples for Hard-Coded Reset Configuration Words Usage ......................... 4-27
Clocking ........................................................................................................................ 4-28
Clocking in PCI Host Mode....................................................................................... 4-30
PCI Clock Outputs (PCI_CLK_OUT[0:2]) ........................................................... 4-30
Clocking In PCI Agent Mode .................................................................................... 4-30
System Clock Domains.............................................................................................. 4-30
USB Clocking ............................................................................................................ 4-31
Ethernet Clocking ...................................................................................................... 4-32
Real-Time Clock (RTC)............................................................................................. 4-32
Memory Map/Register Definitions................................................................................ 4-32
Reset Configuration Register Descriptions................................................................ 4-32
Reset Configuration Word Low Register (RCWLR)............................................. 4-33
Reset Configuration Word High Register (RCWHR)............................................ 4-33
Reset Status Register (RSR) .................................................................................. 4-33
Reset Mode Register (RMR) ................................................................................. 4-34
Reset Protection Register (RPR) ........................................................................... 4-35
Reset Control Register (RCR) ............................................................................... 4-35
Reset Control Enable Register (RCER)................................................................. 4-36
Clock Configuration Registers................................................................................... 4-36
System PLL Mode Register (SPMR) .................................................................... 4-37
Output Clock Control Register (OCCR)................................................................ 4-38
System Clock Control Register (SCCR)................................................................ 4-39
Chapter 5
System Configuration
5.1
5.2
Introduction...................................................................................................................... 5-1
Local Memory Map Overview and Example .................................................................. 5-1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
v
Paragraph
Number
Contents
Title
Page
Number
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.4
5.2.4.1
5.2.4.1.1
5.2.4.2
5.2.4.3
5.2.4.3.1
5.2.4.4
5.2.4.4.1
5.2.4.5
5.2.4.5.1
5.2.4.6
5.2.4.6.1
5.2.4.7
5.2.4.7.1
5.2.4.8
5.2.4.8.1
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.9.1
5.2.10
5.2.11
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
5.3.2.3
5.3.2.3.1
5.3.2.4
vi
Address Translation and Mapping ............................................................................... 5-3
Window into Configuration Space............................................................................... 5-4
Local Access Windows................................................................................................ 5-4
Local Access Register Memory Map ...................................................................... 5-4
Local Access Register Descriptions ............................................................................ 5-6
Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-6
Updating IMMRBAR .......................................................................................... 5-6
Alternate Configuration Base Address Register (ALTCBAR)................................ 5-7
LBC Local Access Window n Base Address Registers
(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-8
LBLAWBAR0[BASE_ADDR] Reset Value ....................................................... 5-8
LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3). 5-9
LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value .................................... 5-9
PCI Local Access Window n Base Address Register
(PCILAWBAR0–PCILAWBAR1) .................................................................... 5-10
PCILAWBAR0[BASE_ADDR] Reset Value.................................................... 5-10
PCI Local Access Window n Attributes Registers
(PCILAWAR0–PCILAWAR1) .......................................................................... 5-11
PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value ................................ 5-11
DDR Local Access Window n Base Address Registers
(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-12
DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-12
DDR Local Access Window n Attributes Registers
(DDRLAWAR0–DDRLAWAR1)...................................................................... 5-13
DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................ 5-13
Precedence of Local Access Windows ...................................................................... 5-14
Configuring Local Access Windows ......................................................................... 5-14
Distinguishing Local Access Windows from Other Mapping Functions .................. 5-14
Outbound Address Translation and Mapping Windows............................................ 5-15
Inbound Address Translation and Mapping Windows .............................................. 5-15
PCI Inbound Windows........................................................................................... 5-15
Internal Memory Map................................................................................................ 5-15
Accessing Internal Memory from External Masters.................................................. 5-16
System Configuration .................................................................................................... 5-16
System Configuration Register Memory Map........................................................... 5-16
System Configuration Registers ................................................................................ 5-17
System General Purpose Register Low (SGPRL) ................................................. 5-17
System General Purpose Register High (SGPRH) ................................................ 5-17
System Part and Revision ID Register (SPRIDR)................................................. 5-18
SPRIDR[PARTID] Coding................................................................................ 5-18
System Priority and Configuration Register (SPCR) ............................................ 5-18
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Paragraph
Number
Contents
Title
Page
Number
5.3.2.5
5.3.2.6
5.3.2.7
5.3.2.7.1
5.3.2.7.2
5.3.2.8
5.3.2.9
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.4.1
5.4.4.2
5.4.4.3
5.4.5
5.4.5.1
5.4.5.2
5.4.6
5.4.6.1
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.5.1
5.5.5.2
5.5.5.3
5.5.5.4
5.5.5.5
5.5.5.6
5.5.6
5.5.6.1
5.5.6.2
5.5.7
5.6
5.6.1
5.6.2
5.6.3
5.6.4
System I/O Configuration Register Low (SICRL) ................................................ 5-21
System I/O Configuration Register High (SICRH) ............................................... 5-23
Debug Configuration ............................................................................................. 5-26
DDR Debug Configuration................................................................................ 5-27
Local Bus Debug Configuration........................................................................ 5-27
DDR Control Driver Register (DDRCDR)............................................................ 5-27
DDR Debug Status Register (DDRDSR) .............................................................. 5-28
Software Watchdog Timer (WDT)................................................................................. 5-29
WDT Overview.......................................................................................................... 5-29
WDT Features............................................................................................................ 5-30
WDT Modes of Operation ......................................................................................... 5-30
WDT Memory Map/Register Definition ................................................................... 5-31
System Watchdog Control Register (SWCRR) ..................................................... 5-31
System Watchdog Count Register (SWCNR) ....................................................... 5-32
System Watchdog Service Register (SWSRR)...................................................... 5-33
Functional Description............................................................................................... 5-34
Software Watchdog Timer Unit ............................................................................. 5-34
Modes of Operation ............................................................................................... 5-35
Initialization/Application Information....................................................................... 5-36
WDT Programming Guidelines............................................................................. 5-36
Real Time Clock Module (RTC).................................................................................... 5-36
RTC Overview ........................................................................................................... 5-36
RTC Features ............................................................................................................. 5-37
RTC Modes of Operation........................................................................................... 5-37
RTC External Signal Description .............................................................................. 5-37
RTC Memory Map/Register Definition..................................................................... 5-38
Real Time Counter Control Register (RTCNR) .................................................... 5-38
Real Time Counter Load Register (RTLDR)......................................................... 5-39
Real Time Counter Prescale Register (RTPSR) .................................................... 5-40
Real Time Counter Register (RTCTR) .................................................................. 5-40
Real Time Counter Event Register (RTEVR)........................................................ 5-41
Real Time Counter Alarm Register (RTALR) ....................................................... 5-41
Functional Description............................................................................................... 5-42
Real Time Counter Unit......................................................................................... 5-42
RTC Operational Modes ........................................................................................ 5-42
RTC Programming Guidelines................................................................................... 5-43
Periodic Interval Timer (PIT) ........................................................................................ 5-43
PIT Overview............................................................................................................. 5-44
PIT Features............................................................................................................... 5-44
PIT Modes of Operation ............................................................................................ 5-44
PIT External Signal Description ................................................................................ 5-45
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
vii
Paragraph
Number
Contents
Title
Page
Number
5.6.5
5.6.5.1
5.6.5.2
5.6.5.3
5.6.5.4
5.6.5.5
5.6.6
5.6.6.1
5.6.6.2
5.6.7
5.7
5.7.1
5.7.2
5.7.3
5.7.3.1
5.7.3.2
5.7.3.3
5.7.3.4
5.7.4
5.7.5
5.7.5.1
5.7.5.2
5.7.5.3
5.7.5.4
5.7.5.5
5.7.5.6
5.7.5.7
5.7.6
5.7.6.1
5.7.6.2
5.7.6.3
5.7.6.4
5.7.7
5.7.7.1
5.7.7.1.1
5.8
5.8.1
5.8.2
5.8.2.1
5.8.2.2
5.8.2.3
viii
PIT Memory Map/Register Definition ...................................................................... 5-45
Periodic Interval Timer Control Register (PTCNR) .............................................. 5-46
Periodic Interval Timer Load Register (PTLDR) .................................................. 5-46
Periodic Interval Timer Prescale Register (PTPSR) .............................................. 5-47
Periodic Interval Timer Counter Register (PTCTR).............................................. 5-47
Periodic Interval Timer Event Register (PTEVR) ................................................. 5-48
Functional Description............................................................................................... 5-48
Periodic Interval Timer Unit.................................................................................. 5-48
PIT Operational Modes.......................................................................................... 5-49
PIT Programming Guidelines .................................................................................... 5-49
General-Purpose Timers (GTMs)................................................................................... 5-50
GTM Overview .......................................................................................................... 5-50
GTM Features ............................................................................................................ 5-51
GTM Modes of Operation.......................................................................................... 5-51
Cascaded Modes .................................................................................................... 5-51
Clock Source Modes.............................................................................................. 5-52
Reference Modes ................................................................................................... 5-52
Capture Modes....................................................................................................... 5-52
GTM External Signal Description ............................................................................. 5-52
GTM Memory Map/Register Definition.................................................................... 5-54
Global Timers Configuration Registers (GTCFRn)............................................... 5-55
Global Timers Mode Registers (GTMDR1–GTMDR4) ........................................ 5-58
Global Timers Reference Registers (GTRFR1–GTRFR4) .................................... 5-60
Global Timers Capture Registers (GTCPR1–GTCPR4) ........................................ 5-60
Global Timers Counter Registers (GTCNR1–GTCNR4) ...................................... 5-60
Global Timers Event Registers (GTEVR1–GTEVR4) .......................................... 5-61
Global Timers Prescale Registers (GTPSR1–GTPSR4) ........................................ 5-62
Functional Description............................................................................................... 5-63
General-Purpose Timer Units ................................................................................ 5-63
Reference Modes ................................................................................................... 5-63
Capture Modes....................................................................................................... 5-63
Cascaded Modes .................................................................................................... 5-64
Initialization/Application Information....................................................................... 5-66
Programming Guidelines ....................................................................................... 5-66
GTM Registers................................................................................................... 5-66
Power Management Control (PMC) .............................................................................. 5-66
External Signal Description ....................................................................................... 5-67
PMC Memory Map/Register Definition .................................................................... 5-67
Power Management Controller Configuration Register (PMCCR)....................... 5-68
Power Management Controller Event Register (PMCER).................................... 5-68
Power Management Controller Mask Register (PMCMR) ................................... 5-70
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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