NewCoSemi 
 
NCS8806 
Datasheet 
 
FHD-to-4K TV-Signal Scaler 
 
1  Features 
 
V-By-One (VBO) Output 
4/8-lane VBO @ max 3Gbps per lane 
Up to 4K@60Hz supported 
Up to 6dB pre-emphasis 
Lane and polarity swap supported 
 
LVDS Input 
Dual-channel LVDS interface 
Up to 1080p@60Hz supported 
Built-in termination 
Channel and polarity swap supported 
 
Scaler 
Hi-Fidelity scaler w/ super-resolution engine 
 
Reference Clock 
Any freq. between 19MHz and 100MHz 
Crystal or single-ended clock input 
 
2  Block Diagram 
 
Built-in 5000ppm SSC generator 
Misc 
I2C for chip configuration 
Built-in VBO handshake protocol 
Built-in video test pattern 
 
Power 
1.5V core supply 
3.3V IO supply 
Deep-sleep mode power <5mW 
~1.1W @4K60Hz w/ scaling  
 
Package 
eLQFP128 (14mm x 14mm) package 
RoHS Compliant 
 
 
TEST
PLL /w SSC
XO
XTAL_IN
XTAL_OU T
LVDIE[3:0]P/N
LVCIEP/N 
LVDIO[3:0]P/N
LVCIOP/N
LVDS I/F
BIST
Link layer
Time-Base
Converter
Hi-Fi
Scaler
S
c
r
a
m
b
e
r
l
E
n
c
o
d
e
r
SDA
SCL
I2C Slave
Registers
Bandgap
VBO
TX
VBOTX
[7-0]P/N
DVDD33
AVDD33
HSDVDD33
DVDD15
AVDD15
HSDVDD15
RESETB
PW D
I2CSEL
TEST
GND
 
 
 
 
 
 
 
 
 
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3 General Description 
NCS8806 
Datasheet 
 
 
NCS8806 is a low-power FHD-to-4K TV-Signal Scaler, which is designed for low cost 4K TV, 
Commercial display, Advertising Machine, etc. Market. 
 
NCS8806 supports 4/8 lane VBO output which is typically required to support UHD 
(3840*2160) and above at 60Hz frame rate. And also support various types of color video 
format data mapping. 
 
All the functions pack into a small 14mm*14mm eLQFP128 package which saves the 
precious space and cost in TV devices. 
 
 
4  Pin Diagram 
  
5
1
D
D
V
D
C
N
C
N
N
K
C
O
L
C
N
3
3
D
D
V
D
B
T
S
R
D
W
P
T
S
E
T
A
D
S
L
C
S
C
N
C
N
C
N
C
N
C
N
5
1
D
D
V
A
P
0
O
B
V
N
0
O
B
V
P
1
O
B
V
N
1
O
B
V
P
2
O
B
V
N
2
O
B
V
C
N
C
N
5
1
D
D
V
A
P
3
O
B
V
N
3
O
B
V
C
N
C
N
C
N
C
N
8
2
1
7
2
1
6
2
1
5
2
1
4
2
1
3
2
1
2
2
1
1
2
1
0
2
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
1
9
0
1
8
0
1
7
0
1
6
0
1
5
0
1
4
0
1
3
0
1
2
0
1
1
0
1
0
0
1
9
9
8
9
7
9
NC
NC
I2C_MASTER_ENB
NC
NC
NC
NC
NC
NC
NC
NC
DVDD15
NC
NC
NC
NC
HSDVDD15
NC
NC
NC
NC
HSDVDD15
LVDIO0N
LVDIO0P
LVDIO1N
LVDIO1P
LVDIO2N
LVDIO2P
LVCION
LVCIOP
LVDIO3N
LVDIO3P
NCS
GND
AVDD15
AVDD15
NC
NC
VBO4P
VBO4N
VBO5P
VBO5N
VBO6P
VBO6N
AVDD15
VBO7P
VBO7N
NC
NC
NC
NC
NC
NC
AVDD15
RESERVE
RESERVE
RESERVE
RESERVE
RESERVE
RESERVE
RESERVE
RESERVE
NC
NC
AVDD15
AVDD33
3
3
4
3
5
3
6
3
7
3
8
3
9
3
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
4
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
5
0
6
1
6
2
6
3
6
4
6
3
3
D
D
V
D
S
H
5
1
D
D
V
D
S
H
N
0
E
I
D
V
L
P
0
E
I
D
V
L
N
1
E
I
D
V
L
P
1
E
I
D
V
L
N
2
E
I
D
V
L
P
2
E
I
D
V
L
N
E
I
C
V
L
P
E
I
C
V
L
N
3
E
I
D
V
L
P
3
E
I
D
V
L
D
N
G
E
V
R
E
S
E
R
E
V
R
E
S
E
R
5
1
D
D
V
A
E
V
R
E
S
E
R
E
V
R
E
S
E
R
E
V
R
E
S
E
R
E
V
R
E
S
E
R
E
V
R
E
S
E
R
E
V
R
E
S
E
R
C
N
C
N
5
1
D
D
V
A
C
N
C
N
C
N
C
N
5
1
D
D
V
A
N
I
L
A
T
X
T
U
O
L
A
T
X
(TOP VIEW) 
 
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91
90
89
88
87
86
85
84
83
82
81
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8806
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5  Pin Description  
NCS8806 
Datasheet 
 
No. 
3 
23,24 
25,26 
27,28 
29,30 
31,32 
35,36 
37,38 
39,40 
41,42 
43,44 
Pin Name 
Description 
I2C_MASTER_ENB 
LVDIO0N,P 
I2C Master/Slave select: L-Master, H-Slave(Default) 
LVDS data channel 0,odd pixel 
LVDIO1N,P 
LVDIO2N,P 
LVCION,P 
LVDIO3N,P 
LVDIE0N,P 
LVDIE1N,P 
LVDIE2N,P 
LVCIEN,P 
LVDIE3N,P 
LVDS data channel 1, odd pixel 
LVDS data channel 2, odd pixel 
LVDS clock channel, odd pixel 
LVDS data channel 3, odd pixel 
LVDS data channel 0, even pixel 
LVDS data channel 1, even pixel 
LVDS data channel 2, even pixel 
LVDS clock channel, even pixel 
LVDS data channel 3, even pixel 
46,47,49,50,51
,52,53,54,69,7
0,71,72,73,74,
RESERVE 
RESERVED, NO Connect 
75,76 
63 
64 
84,85 
87,88 
89,90 
91,92 
101,102 
104,105 
106,107 
108,109 
117 
118 
119 
122 
126 
127 
XTALIN 
XTALOUT 
VBO7N,P 
VBO6N,P 
VBO5N,P 
VBO4N,P 
VBO3N,P 
VBO2N,P 
VBO1N,P 
VBO0N,P 
TEST 
PWD 
RSTB 
LOCKN 
SCL 
SDA 
Crystal or clock input 
Crystal 
V-By-One  Channel 7 Data Output 
V-By-One  Channel 6 Data Output 
V-By-One  Channel 5 Data Output 
V-By-One  Channel 4  Data Output 
V-By-One  Channel 3 Data Output 
V-By-One  Channel 2 Data Output 
V-By-One  Channel 1  Data Output 
V-By-One  Channel 0  Data Output 
Not connected 
Power down, active high 
Reset, active low 
V-By-One Lock Detection Input 
I2C clock 
I2C data 
12,125 
DVDD15 
1.5V Power supply for digital core 
17,22,34 
HSDVDD15 
1.5V Power supply for high-speed digital 
AVDD15 
1.5V Power supply for analog 
48,57,62,66,77
,86,95,96,103,
112 
 
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NCS8806 
Datasheet 
 
No. 
33 
65 
120 
45 
Pin Name 
Description 
HSDVDD33 
3.3V power supply for high-speed digital 
AVDD33 
DVDD33 
GND 
3.3V power supply for analog 
3.3V power supply for digital IOs 
Ground 
1,2,4,5,6,7,8,9,
10,11,13,14,15
,16,18,19,20,2
1,55,56,58,59,
60,61,67,68,78
,79,80,81,82,8
3,93,94,97,98,
99,100,110,11
1,113,114,115,
116,121,123,1
24,128 
NC 
NO Connect  
Thermal 
GND 
Ground 
 
 
 
 
 
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6  Electrical Specifications 
 
6.1 Absolute maximum ratings 
NCS8806 
Datasheet 
 
parameter 
Symbol 
Spec 
Min 
Typ 
Max 
Unit 
1.5V Supply voltage 
3.3V Supply voltage 
COMS/TTL input voltage 
COMS/TTL output voltage 
LVDS receiver input voltage 
Storage temperature 
Junction temperature 
Thermal  resistance(junction 
ambient) 
DVDD15,AVDD15,HSDV
DD15 
DVDD33,AVDD33,HSDV
DD33  
VIO 
VOUT 
VIN 
TSTG 
TJ 
θJA 
-0.3 
-0.3 
-0.3 
-0.3 
-0.3 
-40 
- 
- 
- 
- 
- 
- 
- 
- 
- 
- 
1.6 
4 
DVDD3.3 
DVDD3.3 
AVDD3.3 
125 
125 
80 
V 
V 
 
 
 
℃ 
℃ 
℃ 
 
6.2 Recommended operating conditions 
Parameter 
1.5V Supply voltage 
3.3V Supply voltage 
Operating temperature 
Symbol 
VDD15 
VDD33 
TA 
LVDS receiver input voltage 
VIN 
 
6.3 Power Consumption 
Mode 
Min 
1.45 
3.0 
0 
0 
Typ 
1.5 
3.3 
25 
- 
Max 
1.55 
3.6 
70 
2.4 
Unit 
V 
V 
℃ 
V 
Power 
VDD15 
713mA 
<5mA 
Power 
1119mW1 
VDD33 
15mA 
3840X2160 @ 60Hz 
Deep-sleep 
Note: 1. VDD33=3.3V, VDD15=1.5V,1920X1080@60Hz LVDS input, 3840X2460@60Hz VBO 4Byte 2 subarea 
<5mW 
- 
Data Format Output, TX diff p-p voltage 200mV. 
 
6.4 DC electrical characteristics 
Symbol 
parameter 
Condition 
IDD 
Supply current 
F=75MHz,VDD=3.3V/
1.5V,PI=14KΩ, 
RL=100Ω, 
Pixel checker pattern 
CMOS/TTL DC Specifications 
VIH 
VIL 
VOH 
VOL 
High level input voltage 
Low level input voltage 
High level output voltage 
Low level output voltage 
- 
- 
- 
- 
 
6.5 LVDS electrical characteristics 
 
Min. 
- 
- 
2.0 
-0.3 
2.4 
- 
Spec. 
Typ. 
TBD 
(1.5V) 
TBD 
(3.3V) 
Max. 
- 
- 
Unit 
mA 
mA 
- 
- 
- 
- 
DVDD 
0.8 
- 
0.4 
V 
V 
V 
V 
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NewCoSemi 
NCS8806 
Datasheet 
 
 
 
Symbol 
RateLVDS 
fCLK-LVDS 
VTH-LVDS 
VTL-LVDS 
VCM-LVDS 
VDiff-LVDS 
RLVDS 
Description 
LVDS data rate per pair  
LVDS input clock frequency 
Differential input high threshold 
Differential input low threshold 
LVDS common mode voltage  
Differential Input Voltage 
Internal built-in termination 
Min 
400 
57 
 
-0.1 
0.9 
100 
75 
Typ 
 
 
 
 
1.2 
 
100 
Max  Units 
1000  Mbps 
143 
MHz 
0.1 
 
1.4 
600 
150 
V 
V 
V 
mV 
Ω 
6.6 VBO electrical characteristics 
Description 
Symbol 
Min 
Typ 
Max  Units 
UI 
VTXpp 
VTX-DC-CM 
CTX 
 
Unit interval for high bit rate(3.0 Gbps/ 
lane) 
Differential peak-to-peak  
TX DC common mode voltage 
AC coupling capacitor 
 
0.1 
0 
75 
333 
0.6 
 
100 
 
1.2 
1.2 
200 
ps 
V 
V 
nF 
6.7 XTAL electrical characteristics 
 
Internal to IC
Rf
C2
Crystal
C1
Rf  is used to bias the inverter in the high gain region.  It cannot be too low or the loop may 
not oscillate. For mega Hertz range applications, Rf of 1 Mohm is applied. 
 
 
 
 
 
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7  V-By-One Function 
 
7.1 VBO Data Mapping 
NCS8806 
Datasheet 
 
 
NCS8806 VBO Output Support more than two formats data mapping. 
 
The almost 8 lane VBO 4K panels (TCON)   have two formats data mapping. NCS8806 
perfectly support the all formats data mapping output. 
 
(Figure 1 and Figure 2 show the different formats data mapping)  
 
Area 
Lane 
Data Stream 
A 
Lane0 
1, 9, 17, ..........., 3825, 3833 
Lane1 
2, 10, 18, ........., 3826, 3834 
Lane2 
3, 11, 19, ........., 3827, 3835 
Lane3 
4, 12, 20, ........., 3828, 3836 
Lane4 
5, 13, 21, ...........,3829, 3837 
Lane5 
6, 14, 22, ........., 3830, 3838 
Lane6 
7, 15, 23, ........., 3831, 3839 
Lane7 
8, 16, 24, ........., 3832, 3840 
Figure 1   Single subarea data mapping 
Area 
Lane 
Data Stream 
A 
B 
Lane0 
Lane1 
Lane2 
Lane3 
1, 5, 9, ..........., 1973, 1977 
2, 6, 10, ........., 1974, 1978 
3, 7, 11, ........., 1975, 1979 
4, 8, 12, ........., 1976, 1980 
Lane4 
1981,1985 ...........,3833, 3837 
Lane5 
1982, 1986........., 3834, 3838 
Lane6 
1983,1987 ........., 3835, 3839 
Lane7 
1984,1988 ........., 3836, 3840 
Figure 2   Dual subarea data mapping 
 
 
 
 
 
 
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7.2 VBO Byte length and Color mapping 
 
NCS8806 
Datasheet 
 
NCS8806 support various types of color video format allocating bit[31:0] to pixel 
data in packer mapping. The color data mapping should refer to Figure 3. 
 
Mode 
Byte 
Packer 
Output 
Color data mapping 
24bpp RGB 
18bpp RGB 
 
e
d
o
m
 
e
t
y
b
4
Byte 0 
 
e
d
o
m
 
e
t
y
b
3
Byte 1 
Byte 2 
    Byte 3 
Bit0 
Bit1 
Bit2 
Bit3 
Bit4 
Bit5 
Bit6 
Bit7 
Bit8 
Bit9 
Bit10 
Bit11 
Bit12 
Bit13 
Bit14 
Bit15 
Bit16 
Bit17 
Bit18 
Bit19 
Bit20 
Bit21 
Bit22 
Bit23 
Bit24 
Bit25 
Bit26 
Bit27 
Bit28 
Bit29 
Bit30 
Bit31 
R0 
R1 
R2 
R3 
R4 
R5 
R6 
R7 
G0 
G1 
G2 
G3 
G4 
G5 
G6 
G7 
B0 
B1 
B2 
B3 
B4 
B5 
B6 
B7 
(3DLR*) 
(3DEN*) 
- 
- 
- 
- 
- 
- 
- 
- 
R0 
R1 
R2 
R3 
R4 
R5 
- 
- 
G0 
G1 
G2 
G3 
G4 
G5 
- 
- 
B0 
B1 
B2 
B3 
B4 
B5 
- 
- 
- 
- 
   
- 
- 
- 
Figure 3    Various types of color video format data mapping 
 
 
 
 
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