led.vhd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Mon Jan 02 22:56:57 2012 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:53:36 01/02/2012 -- Design Name: -- Module Name: led - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- ---基于状态机的流水灯VHDL程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity led is Port ( clk : in STD_LOGIC; led_out : out STD_LOGIC_VECTOR (4 downto 0)); end led; architecture Behavioral of led is signal n:integer range 0 to 6; type state_type is (a,b,c,d); signal next_state,present_state :state_type; begin tem:process(present_state) begin case present_state is when a => led_out<="10001";--*...* 两边灯亮 next_state <=b; when b => led_out<="01010";--.*.*. 第二个和点三个灯亮 next_state <=c; when c => led_out<="00100";--..*..中间灯亮 next_state <=d; when d => led_out<="11111";--全亮 next_state <=a; end case; Page 1 

Mon Jan 02 22:56:58 2012 end process tem; tep:process(clk) begin if rising_edge(clk) then n<=n+1; if n=5 then n<=0; present_state<=next_state; end if ; --可通过设计n的值进行延时 led.vhd 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 end if; end process tep; end Behavioral; Page 2