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Xilinx VIvado FFT IP核手册.pdf
Fast Fourier Transform v9.1
Table of Contents
IP Facts
Ch. 1: Overview
Core Overview
Algorithm
Licensing and Ordering
Ch. 2: Product Specification
Resource Utilization
Port Descriptions
Ch. 3: Designing with the Core
Clocking
aclken (Clock Enable)
Resets
aresetn (Synchronous Clear)
Event Signals
event_frame_started
event_tlast_missing
event_tlast_unexpected
event_fft_overflow
event_data_in_channel_halt
event_data_out_channel_halt
event_status_channel_halt
AXI4-Stream Considerations
Basic Handshake
AXI Channel Rules
Configuration Channel
TDATA Fields
TDATA Format
TDATA Example
Data Input Channel
Pinout
TDATA Fields
TDATA Format
TDATA Example
Data Output Channel
Pinout
TDATA Fields
TDATA Format
TDATA Example
TUSER Fields
TUSER Format
TUSER Examples
Status Channel
Pinout
TDATA Fields
TDATA Format
TDATA Example
Theory of Operation
Finite Word Length Considerations
Floating-Point Considerations
Denormalized Numbers
NaNs and ± Infinity
Real-Valued Input Data
Rounding Implementation
Dynamic Range Characteristics
Architecture Options
Bit and Digit Reversal
Pipelined Streaming I/O
Radix-4 Burst I/O
Radix-2 Burst I/O
Radix-2 Lite Burst I/O
Run Time Transform Configuration
Transform Size
Forward/Inverse and Scaling Schedule
Cyclic Prefix Insertion
Transform Status
Overflow
Block Exponent
XK Index
Controlling the FFT Core
Transform Timing
Pipelined Streaming I/O with no Cyclic Prefix Insertion
Pipelined Streaming I/O with Cyclic Prefix Insertion
Burst I/O Architectures
Configuring the FFT
Applying a New Configuration While Idle
Applying a New Configuration While Streaming Frames
How Changing the Configuration Can Change Transform Timing
Ch. 4: Design Flow Steps
Customizing and Generating the Core
Configuration Tab
Implementation Tab
Detailed Implementation Tab
Information Tabs
User Parameters
Output Generation
System Generator for DSP Graphical User Interface
Tab 1: Basic
Tab 2: Advanced
Tab 3: Implementation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Ch. 5: C Model
Features
Overview
Unpacking and Model Contents
Installation
Software Requirements
FFT C Model Interface
Create a State Structure
Simulate the FFT Core
Destroy the State Structure
C Model Example Code
Compiling with the FFT C Model
Linux
Windows
FFT MATLAB Software MEX Function
Building the MEX Function
Installing and Running the MEX Function
MEX Function Example Code
Modeling Multichannel FFTs
Dependent Libraries
Ch. 6: Test Bench
Demonstration Test Bench
Using the Demonstration Test Bench
Demonstration Test Bench in Detail
Customizing the Demonstration Test Bench
Appx. A: Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Parameter Changes
Port Changes
Functionality Changes
Latency Changes
Numerical Behavior Changes
Appx. B: Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
C Model Reference
Simulation Debug
AXI4-Stream Interface Debug
Appx. C: Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices
Fast Fourier
Transform v9.1
LogiCORE IP Product Guide
Vivado Design Suite
PG109 June 17, 2020
Table of Contents
IP Facts
Chapter 1: Overview
Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Product Specification
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3: Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Event Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AXI4-Stream Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
System Generator for DSP Graphical User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 5: C Model
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Unpacking and Model Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
FFT C Model Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C Model Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Compiling with the FFT C Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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FFT MATLAB Software MEX Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MEX Function Example Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Modeling Multichannel FFTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Dependent Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 6: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AXI4-Stream Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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LogiCORE IP Facts Table
Core Specifics
IP Facts
UltraScale+™
UltraScale™
Zynq®-7000 SoC
7 Series
AXI4-Stream
Performance and Resource Utilization web
page
Provided with Core
Encrypted RTL
Not Provided
VHDL
Not Provided
Encrypted VHDL
C Model
N/A
Tested Design Flows(2)
Vivado® Design Suite
System Generator for DSP
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Master Answer Record: 54501
Master Vivado IP Change Logs: 72775
Xilinx Support web page
Supported
Device Family(1)
Supported User
Interfaces
Resources
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Design Entry
Simulation
Synthesis
Release Notes
and Known
Issues
All Vivado IP
Change Logs
Notes:
1. For a complete listing of supported devices, see the Vivado IP
2. For the supported versions of the tools, see the
catalog.
Xilinx Design Tools: Release Notes Guide.
Introduction
The Xilinx® LogiCORE™ IP Fast Fourier
Transform (FFT) core implements the
Cooley-Tukey FFT algorithm, a computationally
efficient method for calculating the Discrete
Fourier Transform (DFT).
Features
•
Forward and inverse complex FFT, run time
configurable
•
Transform sizes N = 2m, m = 3 – 16
• Data sample precision bx = 8 – 34
•
Phase factor precision bw = 8 – 34
• Arithmetic types:
Scaled fixed-point
Block floating-point
° Unscaled (full-precision) fixed-point
°
°
Fixed-point or floating-point interface
Rounding or truncation after the butterfly
Block RAM or Distributed RAM for data and
phase-factor storage
•
•
•
•
•
•
• Optional run time configurable transform
point size
Run time configurable scaling schedule for
scaled fixed-point cores
Bit/digit reversed or natural output order
•
• Optional cyclic prefix insertion for digital
communications systems
Four architectures offer a trade-off between
core size and transform time
Bit accurate C model and MEX function for
system modeling available for download
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Product Specification
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Overview
Chapter 1
Core Overview
The FFT core computes an N-point forward DFT or inverse DFT (IDFT) where N can be 2m,
m = 3–16.
For fixed-point inputs, the input data is a vector of N complex values represented as dual
bx-bit twos-complement numbers, that is, bx bits for each of the real and imaginary
components of the data sample, where bx is in the range 8 to 34 bits inclusive. Similarly, the
phase factors bw can be 8 to 34 bits wide.
For single-precision floating-point inputs, the input data is a vector of N complex values
represented as dual 32-bit floating-point numbers with the phase factors represented as
24- or 25-bit fixed-point numbers.
All memory is on-chip using either block RAM or distributed RAM. The N element output
vector is represented using by bits for each of the real and imaginary components of the
output data. Input data is presented in natural order and the output data can be in either
natural or bit/digit reversed order. The complex nature of data input and output is intrinsic
to the FFT algorithm, not the implementation.
Three arithmetic options are available for computing the FFT:
•
•
•
The point size N, the choice of forward or inverse transform, the scaling schedule and the
cyclic prefix length are run time configurable. Transform type (forward or inverse), scaling
schedule and cyclic prefix length can be changed on a frame-by-frame basis. Changing the
point size resets the core.
Four architecture options are available: Pipelined Streaming I/O, Radix-4 Burst I/O, Radix-2
Burst I/O, and Radix-2 Lite Burst I/O. For detailed information about each architecture, see
Architecture Options.
Full-precision unscaled arithmetic
Scaled fixed-point, where you provide the scaling schedule
Block floating-point (run time adjusted scaling)
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The FFT is a computationally efficient algorithm for computing a Discrete Fourier Transform
(DFT) of sample sizes that are a positive integer power of 2. The DFT
of a
sequence
is defined as
X k
( ),
0,
K
N
=
−
=
−
1
k
,
( ),
x n
0,
K
,
N
n
1
Chapter 1: Overview
where N is the transform size and
( )
X k
=
=
0
n
N
−
1
( )
x n e
−
jnk
π
2 /
N
=
k
0,
K
,
N
−
1
Equation 1-1
j = −
1
. The inverse DFT (IDFT) is given by
( )
x n
=
1
N
−
1
N
=
0
k
( )
X k e
jnk
π
2 /
N
=
n
0,
K
,
N
−
1
Equation 1-2
Algorithm
The FFT core uses the Radix-4 and Radix-2 decompositions for computing the DFT. For Burst
I/O architectures, the decimation-in-time (DIT) method is used, while the
decimation-in-frequency (DIF) method is used for the Pipelined Streaming I/O architecture.
When using Radix-4 decomposition, the N-point FFT consists of log4 (N) stages, with each
stage containing N/4 Radix-4 butterflies. Point sizes that are not a power of 4 need an extra
Radix-2 stage for combining data. An N-point FFT using Radix-2 decomposition has log2 (N)
stages, with each stage containing N/2 Radix-2 butterflies.
The inverse FFT (IFFT) is computed by conjugating the phase factors of the corresponding
forward FFT. The FFT core does not implement the 1/N scaling for inverse FFT. The scaling is
therefore as per forward FFT, simply with conjugated phase factors (twiddle factors).
Licensing and Ordering
This Xilinx® LogiCORE IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information about pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Resource Utilization
For details about resource utilization, visit Performance and Resource Utilization.
Port Descriptions
This section describes the core ports as shown in Figure 2-1 and described in Table 2-1.
X-Ref Target - Figure 2-1
s_axis_config_tvalid
s_axis_config_tready
s_axis_config_tdata
m_axis_data_tvalid
m_axis_data_tready
m_axis_data_tdata
m_axis_data_tuser
m_axis_data_tlast
s_axis_data_tvalid
s_axis_data_tready
s_axis_data_tdata
s_axis_data_tlast
m_axis_status_tvalid
m_axis_status_tready
m_axis_status_tdata
aclk
aresetn
aclken
event_frame_started
event_tlast_unexpected
event_tlast_missing
event_fft_overflow
event_data_in_channel_halt
event_data_out_channel_halt
event_status_channel_halt
Figure 2-1: Core Schematic Symbol
DS808_01_080910
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Table 2-1: Core Signal Pinout
Chapter 2: Product Specification
Name
aclk
aclken
aresetn
s_axis_config_tvalid
s_axis_config_tready
s_axis_config_tdata
s_axis_data_tvalid
s_axis_data_tready
s_axis_data_tdata
s_axis_data_tlast
m_axis_data_tvalid
m_axis_data_tready
m_axis_data_tdata
m_axis_data_tuser
m_axis_data_tlast
I/O Optional
I
I
No
Yes
I
I
O
I
I
O
I
I
O
I
O
O
O
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Description
Rising-edge clock.
Active-High clock enable (optional).
Active-Low synchronous clear (optional, always take priority over
aclken).
A minimum aresetn active pulse of two cycles is required.
TVALID for the Configuration channel.
Asserted by the external master to signal that it is able to provide
data.
TREADY for the Configuration channel.
Asserted by the core to signal that it is ready to accept data.
TDATA for the Configuration channel.
Carries the configuration information: CP_LEN, FWD/INV, NFFT
and SCALE_SCH.
See Run Time Transform Configuration.
TVALID for the Data Input channel.
Used by the external master to signal that it is able to provide
data.
TREADY for the Data Input channel.
Used by the core to signal that it is ready to accept data.
TDATA for the Data Input channel.
Carries the unprocessed sample data: XN_RE and XN_IM.
See Data Input Channel.
TLAST for the Data Input channel.
Asserted by the external master on the last sample of the frame.
This is not used by the core except to generate the events
event_tlast_unexpected and event_tlast_missing events
TVALID for the Data Output channel.
Asserted by the core to signal that it is able to provide sample
data.
TREADY for the Data Output channel.
Asserted by the external slave to signal that it is ready to accept
data. Only present in Non-Realtime mode.
TDATA for the Data Output channel.
Carries the processed sample data XK_RE and XK_IM.
See Data Output Channel.
TUSER for the Data Output channel.
Carries additional per-sample information, such as XK_INDEX,
OVFLO and BLK_EXP.
See Data Output Channel.
TLAST for the Data Output channel.
Asserted by the core on the last sample of the frame.
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