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AMBA 协议 3。0 AMBAaxi.pdf

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    AMBA
    Contents
    List of Tables
    List of Figures
    Preface
    About this document
    Intended audience
    Using this specification
    Conventions
    Typographical
    Timing diagrams
    Signals
    Further reading
    ARM publications
    Feedback
    Feedback on this product
    Feedback on this specification
    Introduction
    1.1 About the AXI protocol
    1.2 Architecture
    1.2.1 Channel definition
    Read and write address channels
    Read data channel
    Write data channel
    Write response channel
    1.2.2 Interface and interconnect
    1.2.3 Register slices
    1.3 Basic transactions
    1.3.1 Read burst example
    1.3.2 Overlapping read burst example
    1.3.3 Write burst example
    1.3.4 Transaction ordering
    1.4 Additional features
    Signal Descriptions
    2.1 Global signals
    2.2 Write address channel signals
    2.3 Write data channel signals
    2.4 Write response channel signals
    2.5 Read address channel signals
    2.6 Read data channel signals
    2.7 Low-power interface signals
    Channel Handshake
    3.1 Handshake process
    3.1.1 Write address channel
    3.1.2 Write data channel
    3.1.3 Write response channel
    3.1.4 Read address channel
    3.1.5 Read data channel
    3.2 Relationships between the channels
    3.3 Dependencies between channel handshake signals
    Addressing Options
    4.1 About addressing options
    4.2 Burst length
    4.3 Burst size
    4.4 Burst type
    4.4.1 Fixed burst
    4.4.2 Incrementing burst
    4.4.3 Wrapping burst
    4.5 Burst address
    Additional Control Information
    5.1 Cache support
    5.2 Protection unit support
    Atomic Accesses
    6.1 About atomic accesses
    6.2 Exclusive access
    6.2.1 Exclusive access process
    6.2.2 Exclusive access from the perspective of the master
    6.2.3 Exclusive access from the perspective of the slave
    6.2.4 Exclusive access restrictions
    6.2.5 Slaves that do not support exclusive access
    6.3 Locked access
    Response Signaling
    7.1 About response signaling
    7.2 Response types
    7.2.1 Normal access success
    7.2.2 Exclusive access
    7.2.3 Slave error
    7.2.4 Decode error
    Ordering Model
    8.1 About the ordering model
    8.2 Transfer ID fields
    8.3 Read ordering
    8.4 Normal write ordering
    8.5 Write data interleaving
    8.6 Read and write interaction
    8.7 Interconnect use of ID fields
    8.8 Recommended width of ID fields
    Data Buses
    9.1 About the data buses
    9.2 Write strobes
    9.3 Narrow transfers
    9.4 Byte invariance
    Unaligned Transfers
    10.1 About unaligned transfers
    10.2 Examples
    Clock and Reset
    11.1 Clock and reset requirements
    11.1.1 Clock
    11.1.2 Reset
    Low-power Interface
    12.1 About the low-power interface
    12.2 Low-power clock control
    12.2.1 Acceptance of low-power request
    12.2.2 Denial of a low-power request
    12.2.3 Exiting a low-power state
    12.2.4 Clock control sequence summary
    12.2.5 Combining peripherals in a low-power domain
    Index
    A
    B
    C
    D
    E
    F
    G
    H
    I
    L
    M
    N
    O
    P
    R
    S
    T
    U
    V
    W
    AMBA® AXI Protocol v1.0 Specification Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B
    AMBA AXI Protocol Specification Copyright © 2003, 2004 ARM Limited. All rights reserved. Release Information Change history Date Issue Change 16 June, 2003 19 March 2004 A B First release Define read and write address channels Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. AMBA Specification License 1.Subject to the provisions of Clauses 2 and 3, ARM hereby grants to LICENSEE a perpetual, non-exclusive, nontransferable, royalty free, worldwide licence to use and copy the AMBA Specification for the purpose of developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the AMBA Specification. 2.THE AMBA SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE. 3. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARM tradename, or AMBA trademark in connection with the AMBA Specification or any products based thereon. Nothing in Clause 1 shall be construed as authority for LICENSEE to make any representations on behalf of ARM in respect of the AMBA Specification. ii Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B
    Confidentiality Status This document is Open Access. This document has no restriction on distribution. Product Status The information in this document is Final (information on a developed product). Web Address http://www.arm.com ARM IHI 0022B Copyright © 2003, 2004 ARM Limited. All rights reserved. iii
    iv Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B
    Contents AMBA AXI Protocol Specification Chapter 1 Chapter 2 Preface About this document .................................................................................... xiv Feedback ................................................................................................... xviii Introduction 1.1 1.2 1.3 1.4 About the AXI protocol ................................................................................ 1-2 Architecture ................................................................................................. 1-3 Basic transactions ....................................................................................... 1-7 Additional features .................................................................................... 1-11 Signal Descriptions 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Global signals ............................................................................................. 2-2 Write address channel signals .................................................................... 2-3 Write data channel signals .......................................................................... 2-4 Write response channel signals .................................................................. 2-5 Read address channel signals .................................................................... 2-6 Read data channel signals .......................................................................... 2-7 Low-power interface signals ........................................................................ 2-8 ARM IHI 0022B Copyright © 2003, 2004 ARM Limited. All rights reserved. v
    Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Channel Handshake 3.1 3.2 3.3 Handshake process .................................................................................... 3-2 Relationships between the channels .......................................................... 3-6 Dependencies between channel handshake signals .................................. 3-7 Addressing Options 4.1 4.2 4.3 4.4 4.5 About addressing options ........................................................................... 4-2 Burst length ................................................................................................ 4-3 Burst size .................................................................................................... 4-4 Burst type ................................................................................................... 4-5 Burst address ............................................................................................. 4-7 Additional Control Information 5.1 5.2 Cache support ............................................................................................ 5-2 Protection unit support ................................................................................ 5-5 Atomic Accesses 6.1 6.2 6.3 About atomic accesses ............................................................................... 6-2 Exclusive access ........................................................................................ 6-3 Locked access ............................................................................................ 6-7 Response Signaling 7.1 7.2 About response signaling ........................................................................... 7-2 Response types .......................................................................................... 7-4 Ordering Model 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 About the ordering model ........................................................................... 8-2 Transfer ID fields ........................................................................................ 8-3 Read ordering ............................................................................................. 8-4 Normal write ordering ................................................................................. 8-5 Write data interleaving ................................................................................ 8-6 Read and write interaction .......................................................................... 8-8 Interconnect use of ID fields ....................................................................... 8-9 Recommended width of ID fields .............................................................. 8-10 Data Buses 9.1 9.2 9.3 9.4 About the data buses .................................................................................. 9-2 Write strobes .............................................................................................. 9-3 Narrow transfers ......................................................................................... 9-4 Byte invariance ........................................................................................... 9-5 Chapter 10 Unaligned Transfers 10.1 10.2 About unaligned transfers ......................................................................... 10-2 Examples .................................................................................................. 10-3 vi Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B
    Chapter 11 Chapter 12 Clock and Reset 11.1 Clock and reset requirements ................................................................... 11-2 Low-power Interface 12.1 12.2 About the low-power interface .................................................................. 12-2 Low-power clock control ............................................................................ 12-3 ARM IHI 0022B Copyright © 2003, 2004 ARM Limited. All rights reserved. vii
    viii Copyright © 2003, 2004 ARM Limited. All rights reserved. ARM IHI 0022B
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