Preliminary
CONTENTS
LIST OF TABLES
LIST OF FIGURES
1.0 Introduction
2.0 LP4 General Changes
2.1 Background
2.2 Detailed Description
2.3 Compatibility with Older Version of DFI
2.4 Compliance
3.0 LPDDR4 Channel
3.1 Background
3.2 Detailed Description
3.2.1 Independent Operation
3.2.2 Multi-Configuration Support
3.2.3 New Parameter Description
3.3 Compatibility with Older Version of DFI
3.4 Compliance
4.0 DB Data Buffer (DB) Training
4.1 Background
4.2 Detailed Description
4.2.1 Parameters
4.3 Compatibility with Older Version of DFI
4.4 Compliance
5.0 Per-Slice Read Leveling
5.1 Background
5.2 Detailed Description
5.2.1 MC-Driven Training Request
5.2.2 PHY-Driven Training Request
5.3 Compatibility with Older Version of DFI
5.4 Compliance
6.0 CA Training
6.1 Background
6.2 Detailed Description
6.2.1 Simplifying the DFI CA Training Bus
6.2.2 Setting CA VREF Values During CA Training
6.2.3 Frequency Change Events
6.3 Compatibility with Older Version of DFI
6.3.1 Using a DFI 4.0 PHY that is Operating with a DFI 3.1 MC
6.3.2 Using a DFI 4.0 MC that is Operating with a DFI 3.1 PHY
6.4 Compliance
7.0 DFI Read Data Eye Training Sequence Enhancement
7.1 Background
7.2 Detailed Description
7.3 Compatibility with Older Version of DFI
7.4 Compliance
8.0 DFI Read/Write Chip Select
8.1 Background
8.2 Detailed Description
8.3 Compatibility with Older Version of DFI
8.4 Compliance
9.0 Write Leveling Strobe Update
9.1 Background
9.2 Detailed Description
9.3 Compatibility with Older Version of DFI
9.4 Compliance
10.0 WR DQ Training
10.1 Background
10.2 Detailed Description
10.3 Compatibility with Older Version of DFI
10.4 Compliance
11.0 PHY Master Interface
11.1 Background
11.2 Detailed Description
11.3 Compatibility with Older Version of DFI
11.4 Compliance
12.0 Frequency Indicator
12.1 Background
12.2 Detailed Description
12.3 Compatibility with Older Version of DFI
12.4 Compliance
13.0 DFI Disconnect Protocol
13.1 Background
13.2 Detailed Description
13.2.1 DFI Update Interface
13.2.2 PHY Master Interface
13.2.3 DFI Training Interface
13.2.4 Frequency Change
13.2.5 Low Power
13.3 Compatibility with Older Version of DFI
13.4 Compliance
14.0 DFI Data Bit Disable
14.1 Background
14.2 Detailed Description
14.3 Compatibility with Older Version of DFI
14.4 Compliance
15.0 Slice Parameter
15.1 Background
15.2 Detailed Description
15.3 Compatibility with Older Version of DFI
15.4 Compliance
16.0 Geardown Mode
16.1 Background
16.2 Detailed Description
16.3 Compatibility with Older Version of DFI
16.4 Compliance
17.0 DFI Feature and Memory Topology Matrix
17.1 Background
17.2 Detailed Description
17.3 Compatibility with Older Version of DFI
17.4 Compliance
18.0 Optional DFI Training
18.1 Background
18.2 Detailed Description
18.3 Compatibility with Older Version of DFI
18.4 Compliance
19.0 3D Stack (3DS) Support
19.1 Background
19.2 Detailed Description
19.3 Compatibility with Older Version of DFI
19.4 Compliance
20.0 Update Interface Clarification on Self Refresh Exit
20.1 Background
20.2 Detailed Description
20.3 Compatibility with Older Version of DFI
20.4 Compliance
21.0 Inactive CS
21.1 Background
21.1.1 Limitation 1
21.1.2 Limitation 2
21.2 Detailed Description
21.2.1 PHY Master Interface
21.2.2 PHY Initiated Training
21.3 Compatibility with Older Version of DFI (3.1)
21.3.1 PHY Master Interface
21.3.2 PHY Initiated Training