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基于FPGA的温度测量.doc
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
----------------------------------
entity lcd_clk is
port
(
clk
rst
lcd_clk
in
in
std_logic;
:
std_logic;
:
: out std_logic
);
end lcd_clk;
---------------------------------------
architecture lcd_clk_arch of lcd_clk is
signal clk_cnt
signal clk_temp
: std_logic_vector(5 downto 0):=(others => '0');
: std_logic:='0';
begin
lcd_clk <= clk_temp;
process(clk,rst)
begin
if rst = '0' then
clk_cnt <= (others => '0');
elsif rising_edge(clk) then
if clk_cnt = 49 then
clk_temp <= not clk_temp;
clk_cnt <= (others => '0');
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
end lcd_clk_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_show is
port
(
clk
rst
: in
: in
std_logic;
std_logic;
sign_show
show_12864
data_out_sign
show_data
: in
: in
: out
: out
std_logic;
std_logic_vector(15 downto 0);
std_logic;
std_logic_vector(7 downto 0)
);
end lcd_show;
architecture lcd_show_arch of lcd_show is
: type_state:=state1;
: integer range 0 to 2000;
type type_state is(state1,state2,state3,state4,state5,state6,state7);
signal state
signal temp_data
signal dot1,dot2,dot3,dot4 : std_logic_vector(7 downto 0);
signal ten,one
signal count
signal pon_temp
signal show_12864_s
signal div
constant jishu
: std_logic_vector(7 downto 0);
: std_logic_vector(13 downto 0):=(others => '0');
: std_logic_vector(7 downto 0);
: std_logic_vector(15 downto 0);
: std_logic_vector(7 downto 0):="00001010";
: std_logic_vector(7 downto 0):="00110000";
begin
process(clk,rst)
begin
if rst = '0' then
state <= state1;
data_out_sign <= '0';
elsif rising_edge(clk) then
case state is
when state1 =>
if sign_show = '1' then
data_out_sign <= '0';
state <= state2;
end if;
when state2 =>
state <= state3;
if show_12864(15) = '1' then
show_12864_s <= not show_12864 + 1;
pon_temp <= "00101101";
else
show_12864_s <= show_12864 ;
pon_temp <= "00101011";
end if;
when state3 =>
if show_12864_s(0) = '1' then
dot4 <= jishu + 5;
else
dot4 <= jishu;
end if;
state <= state4;
when state4 =>
state <= state5;
case show_12864_s(3 downto 0) is
when "0000" =>
dot1 <= jishu;dot2 <= jishu;dot3 <= jishu;
when "0001" =>
dot1 <= jishu + 0;dot2 <= jishu + 6;dot3 <= jishu + 2;
when "0010" =>
dot1 <= jishu + 1;dot2 <= jishu + 2;dot3 <= jishu + 5;
when "0011" =>
dot1 <= jishu + 1;dot2 <= jishu + 8;dot3 <= jishu + 7;
when "0100" =>
dot1 <= jishu + 2;dot2 <= jishu + 5;dot3 <= jishu + 0;
when "0101" =>
dot1 <= jishu + 3;dot2 <= jishu + 1;dot3 <= jishu + 2;
when "0110" =>
dot1 <= jishu + 3;dot2 <= jishu + 7;dot3 <= jishu + 5;
when "0111" =>
dot1 <= jishu + 4;dot2 <= jishu + 3;dot3 <= jishu + 7;
when "1000" =>
dot1 <= jishu + 5;dot2 <= jishu + 0;dot3 <= jishu + 0;
when "1001" =>
dot1 <= jishu + 5;dot2 <= jishu + 6;dot3 <= jishu + 2;
when "1010" =>
dot1 <= jishu + 6;dot2 <= jishu + 2;dot3 <= jishu + 5;
when "1011" =>
dot1 <= jishu + 6;dot2 <= jishu + 8;dot3 <= jishu + 7;
when "1100" =>
dot1 <= jishu + 7;dot2 <= jishu + 5;dot3 <= jishu + 0;
when "1101" =>
dot1 <= jishu + 8;dot2 <= jishu + 1;dot3 <= jishu + 2;
when "1110" =>
dot1 <= jishu + 8;dot2 <= jishu + 7;dot3 <= jishu + 5;
when "1111" =>
dot1 <= jishu + 9;dot2 <= jishu + 3;dot3 <= jishu + 7;
when others =>
null;
end case;
when state5 =>
if show_12864_s(11 downto 4) >= 50 then
show_12864_s(11 downto 4) <= show_12864_s(11 downto 4) - 50;
else
ten <= "00110101";
ten <= "00110000";
end if;
state <= state6;
when state6 =>
if show_12864_s(11 downto 4) >= 40 then
ten <= ten + 4;one <= jishu + show_12864_s(11 downto 4) - 40;
elsif show_12864_s(11 downto 4) >= 30 then
ten <= ten + 3;one <= jishu + show_12864_s(11 downto 4) - 30;
elsif show_12864_s(11 downto 4) >= 20 then
ten <= ten + 2;one <= jishu + show_12864_s(11 downto 4) - 20;
elsif show_12864_s(11 downto 4) >= 10 then
ten <= ten + 1;one <= jishu + show_12864_s(11 downto 4) - 10;
else
one <= jishu + show_12864_s(11 downto 4);
end if;
state <= state7;
data_out_sign <= '1';
when state7 =>
count <= count + 1;
if count < 851 then
show_data <= pon_temp;
elsif count <1702 then
data_out_sign <= '0';
show_data <= ten;
elsif count < 2553 then
show_data <= one;
elsif count < 3404 then
show_data <= "00101110";
elsif count < 4255 then
show_data <= dot1;
elsif count < 5106 then
show_data <= dot2;
elsif count < 5957 then
show_data <= dot3;
elsif count < 6808 then
show_data <= dot4;
elsif count <= 7659 then
show_data <= x"a1";
elsif count <= 8510 then
show_data <= x"e6";
elsif count = 8511 then
state <= state1;
count <= (others => '0');
end if;
end case;
end if;
end process;
end lcd_show_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_temp is
port
(
clk
rst
dq_i
led1
dq_o
dq_t
sign_temp
lcd
temp_12864
: in
: in
: in
: out
: out
: out
: out
: out
: out
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector(6 downto 0):=(others=> '0');
std_logic_vector(15 downto 0)
);
end lcd_temp;
architecture lcd_temp_arch of lcd_temp is
type
state_type
is(reset,skip_rom,state_switch,convert,convert_over,read_cmd,read_data1,read_data,over);
signal state
signal count
signal count1
signal data1
signal cnt_shift
signal state_cnt
signal dq_temp
signal temp
begin
process(clk,rst,temp)
begin
: state_type;
: std_logic_vector(9 downto 0):=(others=> '0');
: std_logic_vector(18 downto 0):=(others=> '0');
: std_logic_vector(7 downto 0);
: std_logic_vector(4 downto 0):=(others=> '0');
: std_logic:='0';
: std_logic;
: std_logic_vector(15 downto 0):=(others=> '0');
temp_12864 <= temp;
lcd(6 downto 0) <= temp(11 downto 5);
if rst = '0' then
led1 <= '1';
dq_o <= '1';
state <= reset;
sign_temp <= '0';
state_cnt <= '0';
lcd <= (others=> '0');
temp <= (others=> '0');
count <= (others=> '0');
count1 <= (others=> '0');
cnt_shift <= (others=> '0');
elsif rising_edge(clk) then
count <= count + 1;
case state is
when reset =>
sign_temp <= '0';
if count < 250 then
dq_t <= '0';
dq_o <= '0';
elsif count < 272 then
dq_t <= '1';
elsif count < 290 then
if dq_i /= '0' then
state <= reset;
count <= (others=> '0');
end if;
elsif count = 430 then
state <= skip_rom;
count <= (others=> '0');
data1 <= x"cc";
else null;
end if;
when skip_rom =>
if cnt_shift = 8 then
state <= state_switch;
cnt_shift <= "00000";
count <= (others=> '0');
elsif count < 8 then
dq_t <= '0';
dq_o <= '0';
elsif count < 29 then
dq_t <= '0';
dq_o <= data1(0);
elsif count < 35 then
dq_t <= '1';
elsif count = 35 then
data1 <= data1(0)&data1(7 downto 1);
cnt_shift <= cnt_shift + 1;
count <= (others=> '0');
end if;
when state_switch =>
count <= (others=> '0');
if state_cnt = '0' then
state <= convert;
data1 <= x"44";
state_cnt <= '1';
else
state <= read_cmd;
data1 <= x"be";
state_cnt <= '0';
end if;
when convert =>
if cnt_shift = 8 then
state <= convert_over;
cnt_shift <= "00000";
count <= (others=> '0');
elsif count < 8 then
dq_t <= '0';
dq_o <= '0';
elsif count < 29 then
dq_t <= '0';
dq_o <= data1(0);
elsif count < 35 then
dq_t <= '1';
elsif count = 35 then
data1 <= data1(0)&data1(7 downto 1);
cnt_shift <= cnt_shift + 1;
count <= (others=> '0');
end if;
when convert_over =>
count <= (others=> '0');
if count1 = 400000 then
count1 <= (others=> '0');
state <= reset;
else
count1 <= count1 + 1;
end if;
when read_cmd =>
if cnt_shift = 8 then
state <= read_data;
cnt_shift <= "00000";
count <= (others=> '0');
elsif count < 8 then
dq_t <= '0';
dq_o <= '0';
elsif count < 29 then
dq_t <= '0';
dq_o <= data1(0);
elsif count < 35 then
dq_t <= '1';
elsif count = 35 then
data1 <= data1(0)&data1(7 downto 1);
cnt_shift <= cnt_shift + 1;
count <= (others=> '0');
end if;
when read_data =>
led1 <= '0';
count <= (others=> '0');
if cnt_shift = 16 then
state <= over;
sign_temp <= '1';
cnt_shift <= "00000";
state <= read_data1;
else
end if;
when read_data1 =>
if count < 3 then
dq_t <= '0';
dq_o <= '0';
elsif count < 8 then
dq_t <= '1';
dq_temp <= dq_i;
elsif count = 35 then
temp <= dq_temp & temp(15 downto 1);
cnt_shift <= cnt_shift + 1;
count <= (others=> '0');
state <= read_data;
else
null;
end if;
when over =>
if count < 240 then
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