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AXI vdma IP说明文档.pdf
AXI Video Direct Memory Access v6.2
Table of Contents
IP Facts
Ch. 1: Overview
Feature Summary
AXI4 Compliant
AXI4 Data Width
AXI4-Stream Data Width
32 Frame Buffers
Data Realignment Engine
Genlock Synchronization
Asynchronous Channels
Frame Sync Options
Dynamic Clock Frequency Change on AXI4-Stream Interface
Frame Advance or Repeat on Error
Applications
Unsupported Features
Licensing and Ordering Information
Ch. 2: Product Specification
Performance
Latency
Throughput
Resource Utilization
Port Descriptions
Timing Diagrams
Example Read (MM2S) Path Timing
Example Write (S2MM) Path Timing
Register Space
Endianess
AXI VDMA Register Address Map
Memory Map to Stream Register Details
Register Access Type Description
MM2S_VDMACR (MM2S VDMA Control Register – Offset 00h)
MM2S_VDMASR (MM2S VDMA Status Register – Offset 04h)
MM2S_REG_INDEX (MM2S Register Index – Offset 14h)
PARK_PTR_REG (Park Pointer Register – Offset 28h)
VDMA_VERSION (AXI VDMA Version Register – Offset 2Ch)
Stream to Memory Map Register Detail
S2MM_VDMACR (S2MM VDMA Control Register – Offset 30h)
S2MM_VDMASR (S2MM VDMA Status Register – Offset 34h)
S2MM_VDMA_IRQ_MASK (S2MM Error Interrupt Mask – Offset 3Ch)
S2MM_REG_INDEX (S2MM Register Index – Offset 44h)
MM2S Vertical Size (MM2S_VSIZE – Offset 0x50)
MM2S Horizontal Size (MM2S_HSIZE – Offset 0x54)
MM2S Frame Delay and Stride (MM2S_FRMDLY_STRIDE – Offset 0x58)
MM2S Start Addresses (Offsets 0x5C to Maximum Offset 0x98)
S2MM Vertical Size (S2MM_VSIZE – Offset 0xA0)
S2MM Horizontal Size (S2MM_HSIZE – Offset 0xA4)
S2MM Frame Delay and Stride (S2MM_FRMDLY_STRIDE – Offset 0xA8)
S2MM Start Addresses (Offsets 0xAC to Maximum Offset 0xE8)
Genlock Synchronization
Genlock Master
Genlock Slave
Dynamic Genlock Master
Dynamic Genlock Slave
Errors
VDMAIntErr
VDMASlvErr
VDMADecErr
Line and Frame Errors
Ch. 3: Designing with the Core
General Design Guidelines
Clocking
Frequency
Dynamic Resolution
Resets
Programming Sequence
Interrupts
Ch. 4: Design Flow Steps
Customizing and Generating the Core
Basic Options
Address Width (32-64)
Frame Buffers
Enable Write Channel
Memory Map Data Width
Enable Read Channel
Advanced Options
Enable Asynchronous Mode
Write Channel Options
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Ch. 5: Example Design
Implementing the Example Design
Test Bench for the Example Design
Simulating the Example Design
Setting up the Simulation
Simulation Results
Ch. 6: General Use Cases
Appx. A: Migrating and Updating
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Appx. B: Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Vivado Design Suite Debug Feature
Hardware Debug
Appx. C: Additional Design Information
FRMPTR_STS (MM2S and S2MM Current Frame Pointer Status – Offset 24h)
S2MM HSIZE Status Register S2MM_HSIZE_STATUS (offset 0xF0h)
S2MM VSIZE Status Register S2MM_VSIZE_STATUS (offset 0xF4h)
Appx. D: Frame Pointers Gray Code Outputs
Appx. E: Additional Resources and Legal Notices
Xilinx Resources
References
Revision History
Please Read: Important Legal Notices
AXI Video Direct
Memory Access v6.2
LogiCORE IP Product Guide
Vivado Design Suite
PG020 November 18, 2015
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Licensing and Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Genlock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 5: Example Design
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Test Bench for the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Chapter 6: General Use Cases
Appendix A: Migrating and Updating
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix C: Additional Design Information
FRMPTR_STS (MM2S and S2MM Current Frame Pointer Status – Offset 24h) . . . . . . . . . . . . . . . . 77
S2MM HSIZE Status Register S2MM_HSIZE_STATUS (offset 0xF0h) . . . . . . . . . . . . . . . . . . . . . . . . 78
S2MM VSIZE Status Register S2MM_VSIZE_STATUS (offset 0xF4h). . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendix D: Frame Pointers Gray Code Outputs
Appendix E: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Introduction
The Xilinx® LogiCORE™ IP AXI VDMA core is a
soft IP core. It provides high-bandwidth direct
memory access between memory and
AXI4-Stream video type target peripherals
including peripherals which support the
AXI4-Stream Video protocol as described in the
Video IP: AXI Feature Adoption section of the
Vivado AXI Reference Guide (UG1037)[Ref 1].
Features
• AXI4 Compliant
•
Primary AXI4 data width support of 32, 64,
128, 256, 512, and 1,024 bits
Primary AXI4-Stream data width support of
multiples of 8 up to 1,024 bits
•
• Optional Data Re-Alignment Engine
• Optional Genlock Synchronization
•
Independent, asynchronous channel
operation
• Dynamic clock frequency change of
AXI4-Stream interface clocks
• Optional frame advance or repeat on error
•
•
Supports up to 32 frame buffers
Supports up to 64-bit address space
IP Facts
LogiCORE IP Facts Table
Core Specifics
UltraScale+™ Families,
UltraScale™ Architecture,
Zynq®-7000, 7 Series
AXI4, AXI4-Lite, AXI4-Stream
See Table 2-4 and Table 2-5
Provided with Core
VHDL
Provided
Provided
Provided
Not Provided
Standalone and Linux
Tested Design Flows(4)
Vivado® Design Suite
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Supported
Device
Family(1)
Supported
User Interfaces
Resources
Design Files(2)
Example
Design
Test Bench
Constraints
File
Simulation
Model
Supported
S/W Drivers(3)
Design Entry
Simulation
Synthesis
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
IP catalog.
2. Contains a few Verilog files. Top level is VHDL.
3. Standalone driver information can be found in the SDK
installation directory. See xilinx_drivers.htm in
/doc/usenglish. Linux OS and driver
support information is available from the
Xilinx Wiki page.
4. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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Product Specification
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Chapter 1
Overview
Many video applications require frame buffers to handle frame rate changes or changes to
the image dimensions (scaling or cropping). The AXI VDMA is designed to allow for efficient
high-bandwidth access between the AXI4-Stream video interface and the AXI4 interface.
Figure 1-1 illustrates the AXI VDMA Block Diagram.
X-Ref Target - Figure 1-1
Figure 1-1: AXI VDMA Block Diagram
After registers are programmed through the AXI4-Lite interface, Control/ Status logic block
generates appropriate commands to the Datamover to initiate Write and Read commands
on the AXI4 Master interface.
A configurable asynchronous line buffer is used to temporarily hold the pixel data prior to
writing it out to the AXI4-Memory Map interface or the AXI4-Stream interface.
In the Write path, the AXI VDMA accepts frames on the AXI4-Stream Slave interface and
writes it to system memory using the AXI4 Master interface.
In the Read path, the AXI VDMA uses the AXI4 Master interface for reading frames from
system memory and outputs it on the AXI4-Stream Master interface.
Both write and read paths operate independently. The AXI VDMA also provides an option to
synchronize the incoming/outgoing frames with an external synchronization signal.
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Chapter 1: Overview
Feature Summary
AXI4 Compliant
The AXI VDMA core is fully compliant with the AXI4 interface, AXI4-Stream interface and
AXI4-Lite interface. The AXI4-Stream also supports the Video Protocol as described in the
“Video IP: AXI Feature Adoption” section of the Vivado AXI Reference Guide (UG1037)[Ref 1].
AXI4 Data Width
The AXI VDMA core supports the primary AXI4 data bus width of 32, 64, 128, 256, 512, and
1,024 bits.
AXI4-Stream Data Width
The AXI VDMA core supports the primary AXI4-Stream data bus width of multiples of 8 bits
up to 1,024 bits. The AXI4-Stream data width must be less than or equal to the AXI4 data
width for the respective channel.
32 Frame Buffers
The AXI VDMA core supports addressing up to 32 frame buffers for a 32-bit address space
and up to 8 frame buffers for more than a 32-bit address space.
Data Realignment Engine
The AXI VDMA core supports the optional Data Realignment Engine (DRE). The DRE lets
unaligned access to memory, allowing the frame buffer to start at any address in memory.
There is no restriction on the hsize and stride as well. This feature is supported for the
AXI4-Stream interface width up to 64 bits.
Genlock Synchronization
The AXI VDMA supports a mechanism to synchronize writing and reading of frames in the
frame buffer through genlock synchronization. Each channel of the AXI VDMA can be
designed to operate as either a Genlock Master/Slave or Dynamic Genlock Master/Slave. By
using this feature, the master and slave are kept in sync by not allowing both to use the
same buffer at the same time.
The AXI VDMA core supports internal Genlock Bus by default when both read and write
channels are selected. This eliminates the need for an external connection between the
write and read channels. See Genlock Synchronization in Chapter 2 for more details.
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Chapter 1: Overview
Asynchronous Channels
The AXI VDMA core supports asynchronous clock domains for AXI4-Lite, S2MM
AXI4-Stream interface, MM2S AXI4-Stream interface, S2MM AXI4 interface and MM2S AXI4
interface.
Frame Sync Options
The AXI VDMA core supports the following three sources for frame synchronization.
• AXI4-Stream based frame synchronization using the tuser(0) port
° Drives the start-of-frame on the m_axis_mm2s_tuser(0) output for read path
°
Synchronizes the incoming frame with the start-of-frame on the
s_axis_s2mm_tuser(0) input for write path
•
Streaming to Memory Mapped frame sync port (s2mm_fsync)
• Memory Mapped to Streaming frame sync port (mm2s_fsync)
Dynamic Clock Frequency Change on AXI4-Stream Interface
The AXI VDMA core allows changing the AXI4-Stream interface clock dynamically to
support different video frame resolution and frame rates.
Frame Advance or Repeat on Error
When any frame or line error is detected in a particular frame, this optional feature allows
you to let the frame number advance on the next frame sync or not advance and reuse the
errored frame number. It is controlled by VDMACR bit 15.
Applications
The AXI VDMA core provides high-speed data movement between system memory and the
AXI4-Stream Video Protocol Video IP. See General Use Cases in Chapter 6 for information
and instructions for a quick bring-up of AXI VDMA.
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Chapter 1: Overview
Unsupported Features
The following AXI4 features are not supported by the AXI VDMA design.
• User signals on the AXI4 Interface
•
•
•
Locked transfers
Exclusive transfers
FIXED and WRAP Burst transfers
Licensing and Ordering Information
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx
Vivado® Design Suite under the terms of the Xilinx End User License. Information about
this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property
page. For information about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representative.
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