SystemVerilog for Verification.pdf

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Chapter 7

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SYSTEMVERILOG FOR VERIFICATION A Guide to Learning the Testbench Language Features

SYSTEMVERILOG FOR VERIFICATION A Guide to Learning the Testbench Language Features CHRIS SPEAR Synopsys, Inc. 1 3

Chris Spear Synopsys, Inc. 377 Simarano Drive Marlboro, MA 01752 SystemVerilog for Verification: A Guide to Learning the Testbench Language Features Library of Congress Control Number: 2006926262 ISBN-10: 0-387-27036-1 ISBN-13: 9780387270364 e-ISBN-10: 0-387-27038-8 e-ISBN-13: 9780387270388 Printed on acid-free paper. 2006 Springer Science+Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed in the United States of America. 9 8 7 6 5 4 3 2 1 springer.com

This book is dedicated to my wonderful wife Laura, whose patience during this project was invaluable, and my children, Allie and Tyler, who kept me laughing.

Contents List of Examples List of Figures List of Tables Foreword Preface Acknowledgments 1. VERIFICATION GUIDELINES Introduction The Verification Process The Verification Plan The Verification Methodology Manual 1.1 1.2 1.3 1.4 1.5 Basic Testbench Functionality 1.6 Directed Testing 1.7 Methodology Basics 1.8 Constrained-Random Stimulus 1.9 What Should You Randomize? 1.10 Functional Coverage 1.11 Testbench Components 1.12 Layered Testbench 1.13 Building a Layered Testbench 1.14 Simulation Environment Phases 1.15 Maximum Code Reuse 1.16 Testbench Performance 1.17 Conclusion 2. DATA TYPES Introduction 2.1 2.2 Built-in Data Types xi xxi xxiii xxv xxvii xxxiii 1 1 2 4 4 5 5 7 8 10 13 15 16 22 23 24 24 25 27 27 27

viii SystemVerilog for Verification Linked Lists Fixed-Size Arrays 2.3 2.4 Dynamic Arrays 2.5 Queues 2.6 Associative Arrays 2.7 2.8 Array Methods 2.9 Choosing a Storage Type 2.10 Creating New Types with typedef 2.11 Creating User-Defined Structures 2.12 Enumerated Types 2.13 Constants 2.14 Strings 2.15 Expression Width 2.16 Net Types 2.17 Conclusion 3. PROCEDURAL STATEMENTS AND ROUTINES Introduction Procedural Statements Tasks, Functions, and Void Functions Task and Function Overview 3.1 3.2 3.3 3.4 3.5 Routine Arguments 3.6 Returning from a Routine Local Data Storage 3.7 3.8 Time Values 3.9 Conclusion 4. BASIC OOP Introduction Think of Nouns, not Verbs 4.1 4.2 4.3 Your First Class 4.4 Where to Define a Class 4.5 OOP Terminology 4.6 Creating New Objects 4.7 Object Deallocation 4.8 Using Objects 4.9 4.10 Class Routines 4.11 Defining Routines Outside of the Class 4.12 Scoping Rules 4.13 Using One Class Inside Another 4.14 Understanding Dynamic Objects 4.15 Copying Objects 4.16 Public vs. Private Static Variables vs. Global Variables 29 34 36 37 39 40 42 45 46 47 51 51 52 53 53 55 55 55 56 57 57 62 62 64 65 67 67 67 68 69 69 70 74 76 76 78 79 81 85 87 91 95

Contents 4.17 Straying Off Course 4.18 Building a Testbench 4.19 Conclusion 5. CONNECTING THE TESTBENCH AND DESIGN Introduction Separating the Testbench and Design The Interface Construct Stimulus Timing Interface Driving and Sampling 5.1 5.2 5.3 5.4 5.5 5.6 Connecting It All Together 5.7 5.8 5.9 5.10 The Four-Port ATM Router 5.11 Conclusion Top-Level Scope Program – Module Interactions SystemVerilog Assertions 6. RANDOMIZATION Introduction Solution Probabilities 6.1 6.2 What to Randomize 6.3 Randomization in SystemVerilog 6.4 Constraint Details 6.5 6.6 Controlling Multiple Constraint Blocks 6.7 Valid Constraints In-line Constraints 6.8 6.9 The pre_randomize and post_randomize Functions 6.10 Constraints Tips and Techniques 6.11 Common Randomization Problems 6.12 Iterative and Array Constraints 6.13 Atomic Stimulus Generation vs. Scenario Generation 6.14 Random Control 6.15 Random Generators 6.16 Random Device Configuration 6.17 Conclusion 7. THREADS AND INTERPROCESS COMMUNICATION Introduction 7.1 7.2 Working with Threads 7.3 7.4 7.5 7.6 Mailboxes 7.7 Building a Testbench with Threads and IPC Interprocess Communication Events Semaphores ix 96 96 97 99 99 99 102 108 114 121 121 123 124 126 134 135 135 136 138 141 149 154 154 155 156 158 164 165 172 175 177 180 182 183 183 184 194 195 199 201 210

x SystemVerilog for Verification 7.8 Conclusion 8. ADVANCED OOP AND GUIDELINES Introduction Introduction to Inheritance Factory Patterns Type Casting and Virtual Methods 8.1 8.2 8.3 8.4 8.5 Composition, Inheritance, and Alternatives 8.6 Copying an Object 8.7 Callbacks 8.8 Conclusion 9. FUNCTIONAL COVERAGE Introduction Functional Coverage Strategies Simple Functional Coverage Example 9.1 9.2 Coverage Types 9.3 9.4 9.5 Anatomy of a Cover Group 9.6 Triggering a Cover Group 9.7 Data Sampling 9.8 Cross Coverage 9.9 Coverage Options 9.10 Parameterized Cover Groups 9.11 Analyzing Coverage Data 9.12 Measuring Coverage Statistics During Simulation 9.13 Conclusion 10. ADVANCED INTERFACES 10.1 Introduction 10.2 Virtual Interfaces with the ATM Router 10.3 Connecting to Multiple Design Configurations 10.4 Procedural Code in an Interface 10.5 Conclusion References Index 214 215 215 216 221 225 228 233 236 240 241 241 243 246 248 251 253 256 265 272 274 275 276 277 279 279 279 284 290 294 295 297

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