VC707_DDR3_datasheet.pdf

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DDR3 SDRAM SODIMM

Features

Pin Assignments

Pin Descriptions

DQ Map

Functional Block Diagram

General Description

Fly-By Topology

Serial Presence-Detect EEPROM Operation

Electrical Specifications

DRAM Operating Conditions

Design Considerations

IDD Specifications

Serial Presence-Detect EEPROM

Module Dimensions

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Features DDR3 SDRAM SODIMM MT8JTF12864HZ – 1GB MT8JTF25664HZ – 2GB MT8JTF51264HZ – 4GB Features • DDR3 functionality and operations supported as defined in the component data sheet • 204-pin, small-outline dual in-line memory module (SODIMM) • Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400 • 1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512 Meg x 64) • VDD = 1.5V ±0.075V • VDDSPD = 3.0–3.6V • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Single-rank • Serial presence-detect (SPD) EEPROM • 8 internal device banks • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Selectable BC4 or BL8 on-the-fly (OTF) • Gold edge contacts • Halogen-free • Fly-by topology • Terminated control, command, and address bus Table 1: Key Timing Parameters Figure 1: 204-Pin SODIMM (MO-268 R/C B) Module height: 30mm (1.181in) Options • Operating temperature – Commercial (0°C ≤ TA ≤ +70°C) • Package – 204-pin DIMM (halogen-free) • Frequency/CAS latency – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) Marking None Z -1G6 -1G4 -1G1 Speed Grade -1G6 -1G4 -1G1 -1G0 -80B Industry Nomenclature PC3-12800 PC3-10600 PC3-8500 PC3-8500 PC3-6400 – – – – CL = 11 CL = 10 CL = 9 1333 1333 1333 1333 1600 – – – – – – Data Rate (MT/s) CL = 8 1066 1066 1066 1066 – CL = 7 1066 1066 1066 – – CL = 6 CL = 5 800 800 800 800 800 667 667 667 667 667 tRCD (ns) 13.125 13.125 13.125 15 15 tRP (ns) 13.125 13.125 13.125 15 15 tRC (ns) 48.125 49.125 50.625 52.5 52.5 PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device configuration Column address Module rank address 1GB 8K 16K A[13:0] 8 BA[2:0] 2GB 8K 32K A[14:0] 8 BA[2:0] 4GB 8K 64K A[15:0] 8 BA[2:0] 1Gb (128 Meg x 8) 2Gb (256 Meg x 8) 4Gb (512 Meg x 8) 1K A[9:0] 1 S0# 1K A[9:0] 1 S0# 1K A[9:0] 1 S0# Table 3: Part Numbers and Timing Parameters – 1GB Modules Base device: MT41J128M8,1 1Gb DDR3 SDRAM Part Number2 MT8JTF12864HZ-1G6__ MT8JTF12864HZ-1G4__ MT8JTF12864HZ-1G1__ Module Density 1GB 1GB 1GB Configuration 128 Meg x 64 128 Meg x 64 128 Meg x 64 Module Bandwidth 12.8 GB/s 10.6 GB/s 8.5 GB/s Memory Clock/ Data Rate 1.25ns/1600 MT/s 1.5ns/1333 MT/s 1.87ns/1066 MT/s Clock Cycles (CL-tRCD-tRP) 11-11-11 9-9-9 7-7-7 Table 4: Part Numbers and Timing Parameters – 2GB Modules Base device: MT41J256M8,1 2Gb DDR3 SDRAM Part Number2 MT8JTF25664HZ-1G6__ MT8JTF25664HZ-1G4__ MT8JTF25664HZ-1G1__ Module Density 2GB 2GB 2GB Configuration 256 Meg x 64 256 Meg x 64 256 Meg x 64 Module Bandwidth 12.8 GB/s 10.6 GB/s 8.5 GB/s Memory Clock/ Data Rate 1.25ns/1600 MT/s 1.5ns/1333 MT/s 1.87ns/1066 MT/s Clock Cycles (CL-tRCD-tRP) 11-11-11 9-9-9 7-7-7 Table 5: Part Numbers and Timing Parameters – 4GB Modules Base device: MT41J512M8,1 4Gb DDR3 SDRAM Part Number2 MT8JTF51264HZ-1G6__ MT8JTF51264HZ-1G4__ MT8JTF51264HZ-1G1__ Module Density 4GB 4GB 4GB Configuration 512 Meg x 64 512 Meg x 64 512 Meg x 64 Module Bandwidth 12.8 GB/s 10.6 GB/s 8.5 GB/s Memory Clock/ Data Rate 1.25ns/1600 MT/s 1.5ns/1333 MT/s 1.87ns/1066 MT/s Clock Cycles (CL-tRCD-tRP) 11-11-11 9-9-9 7-7-7 Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT8JTF51264HZ-1G6E1. PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Pin Assignments Pin Assignments Table 6: Pin Assignments 204-Pin DDR3 SODIMM Front 204-Pin DDR3 SODIMM Back VREFDQ DQ42 DQ43 VSS DQ48 DQ49 VSS VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS VDD A10 BA0 VDD WE# CAS# VDD A13 NC VDD NC VSS DQ32 DQ33 VSS Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT – – 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 – – 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 VSS DQ4 DQ5 VSS VDD BA1 RAS# VDD S0# ODT0 VDD NC NC VDD VREFCA DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS Pin Symbol Pin Symbol Pin Symbol Pin Symbol 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 VSS DQ28 DQ29 VSS DQ3# DQ3 VSS DQ30 DQ31 VSS NC VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 – – 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 DQS7# DQS7 VSS DQ62 DQ63 VSS NF SDA SCL VTT – – VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 DQS5# DQS5 VSS PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 7: Pin Descriptions Symbol Ax Type Input BAx Input CKx, CKx# CKEx DMx Input Input Input ODTx Input Par_In RAS#, CAS#, WE# Input Input RESET# Input (LVCMOS) Sx# SAx SCL CBx DQx DQSx, DQSx# Input Input Input I/O I/O I/O Description Address inputs: Provide the row address for ACTIVE commands, and the column ad- dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui- try and clocks on the DRAM. Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write ac- cess. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. On-die termination: Enables (registered HIGH) and disables (registered LOW) termi- nation resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial- ized as though a normal power-up was executed. Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad- dress range on the I2C bus. Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi- cation to and from the temperature sensor/SPD EEPROM on the I2C bus. Check bits: Used for system error detection and correction. Data input/output: Bidirectional data bus. Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Pin Descriptions Table 7: Pin Descriptions (Continued) Symbol SDA TDQSx, TDQSx# Err_Out# EVENT# VDD VDDSPD VREFCA VREFDQ VSS VTT NC NF Type I/O Output Output (open drain) Output (open drain) Supply Supply Supply Supply Supply Supply – – Description Serial data: Used to transfer addresses and data into and out of the temperature sen- sor/SPD EEPROM on the I2C bus. Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event:The EVENT# pin is asserted by the temperature sensor when criti- cal temperature thresholds have been exceeded. Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the module VDD. Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. Reference voltage: Control, command, and address VDD/2. Reference voltage: DQ, DM VDD/2. Ground. Termination voltage: Used for control, command, and address VDD/2. No connect: These pins are not connected on the module. No function: These pins are connected within the module, but provide no functional- ity. PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM DQ Map DQ Map Table 8: Component-to-Module DQ Map Component Reference Number U1 U3 U6 U8 Component Module Pin DQ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Module DQ Number 2 1 6 5 7 0 3 4 34 36 38 33 35 32 39 37 61 62 57 58 60 59 56 63 29 26 25 31 24 30 28 27 15 7 16 6 18 5 17 4 141 130 140 131 143 129 142 132 182 192 183 191 180 193 181 194 58 67 59 70 57 68 56 69 Component Reference Number U2 U4 U7 U9 Component Module Pin DQ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Module DQ Number 22 17 18 21 23 16 19 20 50 53 54 49 55 48 51 52 45 42 44 46 40 47 41 43 9 10 13 11 12 15 8 14 50 41 51 42 52 39 53 40 175 166 174 165 176 163 177 164 148 157 146 158 147 160 149 159 23 33 24 35 22 36 21 34 PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S0# DQS0# DQS0 DM0 DQS1# DQS1 DM1 DQS2# DQS2 DM2 DQS3# DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS DM CS# DQS DQS# U1 DM CS# DQS DQS# U9 DM CS# DQS DQS# U2 DM CS# DQS DQS# U8 DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQS4# DQS4 DM4 DQS5# DQS5 DM5 DQS6# DQS6 DM6 DQS7# DQS7 DM7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VSS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 VSS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VSS DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DM CS# DQS DQS# U3 U7 DM CS# DQS DQS# U5 SCL SPD EEPROM A1 A2 WP A0 SDA VSS SA0 SA1 VSS BA[2:0]: DDR3 SDRAM A[15/14/13:0]: DDR3 SDRAM RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM CKE0: DDR3 SDRAM ODT0: DDR3 SDRAM RESET#: DDR3 SDRAM DDR3 SDRAM x 8 BA[2:0] A[15/14/13:0] RAS# CAS# WE# CKE0 ODT0 RESET# CK0 CK0# CK1 CK1# Clock, control, command, and address line terminations: DM CS# DQS DQS# CKE0, A[15/14/13:0], RAS#, CAS#, WE#, S0#, ODT0, BA[2:0] U4 DM CS# DQS DQS# U6 CK CK# VDDSPD V DD VTT VREFCA VREFDQ VSS DDR3 SDRAM DDR3 SDRAM VTT VDD SPD EEPROM DDR3 SDRAM Control, command, and address termination DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

General Description 1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3 SODIMM General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod- ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod- ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen- tially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod- ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter- nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, con- trol, command, and address pin on each DRAM is connected to a single trace and ter- minated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig- nals can be easily accounted for by using the write-leveling feature of DDR3. Fly-By Topology Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, per- manently disabling hardware write protection. For further information refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect." PDF: 09005aef8441a29e jtf8c128_256_512x64hz.pdf - Rev. G 5/13 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.

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