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Tensilica Xtensa指令集架构手册.pdf
Xtensa® Instruction Set Architecture (ISA)
Contents
List of Figures
List of Tables
Preface
Changes from the Previous Version
1. Introduction
1.1 What Problem is Tensilica Solving?
1.1.1 Adding Architectural Enhancements
1.1.2 Creating Custom Processor Configurations
1.1.3 Mapping the Architecture into Hardware
1.1.4 Development and Verification Tools
1.2 The Xtensa Instruction Set Architecture
1.2.1 Configurability
1.2.2 Extensibility
1.2.2.1 State Extensions
1.2.2.2 Register File Extensions
1.2.2.3 Instruction Extensions
1.2.2.4 Coprocessor Extensions
1.2.3 Time-to-Market
1.2.4 Code Density
1.2.5 Low Implementation Cost
1.2.6 Low-Power
1.2.7 Performance
1.2.8 Pipelines
1.3 The Xtensa Processor Generator
1.3.1 Processor Configuration
1.3.2 System-Specific Instructions-The TIE Language
2. Notation
2.1 Bit and Byte Order
2.2 Expressions
2.3 Unsigned Semantics
2.4 Case
2.5 Statements
2.6 Instruction Fields
3. Core Architecture
3.1 Overview of the Core Architecture
3.2 Processor-Configuration Parameters
3.3 Registers
3.3.1 General (AR) Registers
3.3.2 Shifts and the Shift Amount Register (SAR)
3.3.3 Reading and Writing the Special Registers
3.4 Data Formats and Alignment
3.5 Memory
3.5.1 Memory Addressing
3.5.2 Addressing Modes
3.5.3 Program Counter
3.5.4 Instruction Fetch
3.5.4.1 Little-Endian Fetch Semantics
3.5.4.2 Big-Endian Fetch Semantics
3.6 Reset
3.7 Exceptions and Interrupts
3.8 Instruction Summary
3.8.1 Load Instructions
3.8.2 Store Instructions
3.8.3 Memory Access Ordering
3.8.4 Jump and Call Instructions
3.8.5 Conditional Branch Instructions
3.8.6 Move Instructions
3.8.7 Arithmetic Instructions
3.8.8 Bitwise Logical Instructions
3.8.9 Shift Instructions
3.8.10 Processor Control Instructions
4. Architectural Options
4.1 Overview of Options
4.2 Core Architecture
4.3 Options for Additional Instructions
4.3.1 Code Density Option
4.3.1.1 Code Density Option Architectural Additions
4.3.1.2 Branches
4.3.2 Loop Option
4.3.2.1 Loop Option Architectural Additions
4.3.2.2 Restrictions on Loops
4.3.2.3 Loops Disabled During Exceptions
4.3.2.4 Loopback Semantics
4.3.3 Extended L32R Option
4.3.3.1 Extended L32R Option Architectural Additions
4.3.3.2 The Literal Base Register
4.3.4 16-bit Integer Multiply Option
4.3.4.1 16-bit Integer Multiply Option Architectural Additions
4.3.5 32-bit Integer Multiply Option
4.3.5.1 32-bit Integer Multiply Option Architectural Additions
4.3.6 32-bit Integer Divide Option
4.3.6.1 32-bit Integer Divide Option Architectural Additions
4.3.7 MAC16 Option
4.3.7.1 MAC16 Option Architectural Additions
4.3.7.2 Use With CLAMPS Instruction
4.3.8 Miscellaneous Operations Option
4.3.8.1 Miscellaneous Operations Option Architectural Additions
4.3.9 Coprocessor Option
4.3.9.1 Coprocessor Option Architectural Additions
4.3.9.2 Coprocessor Context Switch
4.3.10 Boolean Option
4.3.10.1 Boolean Option Architectural Additions
4.3.10.2 Booleans
4.3.11 Floating-Point Coprocessor Option
4.3.11.1 Floating-Point Coprocessor Option Architectural Additions
4.3.11.2 Floating-Point Representation
4.3.11.3 Floating-Point State
4.3.11.4 Floating-Point Exceptions
4.3.11.5 Floating-Point Instructions
4.3.12 Multiprocessor Synchronization Option
4.3.12.1 Memory Access Ordering
4.3.12.2 Multiprocessor Synchronization Option Architectural Additions
4.3.12.3 Inter-Processor Communication with the L32AI and S32RI Instructions
4.3.13 Conditional Store Option
4.3.13.1 Conditional Store Option Architectural Additions
4.3.13.2 Exclusive Access with the S32C1I Instruction
4.3.13.3 Use Models for the S32C1I Instruction
4.3.13.4 The Atomic Operation Control Register (ATOMCTL) under the Conditional Store Option
4.3.13.5 Memory Ordering and the S32C1I Instruction
4.4 Options for Interrupts and Exceptions
4.4.1 Exception Option
4.4.1.1 Exception Option Architectural Additions
4.4.1.2 Exception Causes under the Exception Option
4.4.1.3 The Miscellaneous Program State Register (PS) under the Exception Option
4.4.1.4 Value of Variables under the Exception Option
4.4.1.5 The Exception Cause Register (EXCCAUSE) under the Exception Option
4.4.1.6 The Exception Virtual Address Register (EXCVADDR) under the Exception Option
4.4.1.7 The Exception Program Counter (EPC) under the Exception Option
4.4.1.8 The Double Exception Program Counter (DEPC) under the Exception Option
4.4.1.9 The Exception Save Register (EXCSAVE) under the Exception Option
4.4.1.10 Handling of Exceptional Conditions under the Exception Option
4.4.1.11 Exception Priority under the Exception Option
4.4.2 Relocatable Vector Option
4.4.2.1 Relocatable Vector Option Architectural Additions
4.4.3 Unaligned Exception Option
4.4.3.1 Unaligned Exception Option Architectural Additions
4.4.4 Interrupt Option
4.4.4.1 Interrupt Option Architectural Additions
4.4.4.2 Specifying Interrupts
4.4.4.3 The Level-1 Interrupt Process
4.4.4.4 Use of Interrupt Instructions
4.4.5 High-Priority Interrupt Option
4.4.5.1 High-Priority Interrupt Option Architectural Additions
4.4.5.2 Specifying High-Priority Interrupts
4.4.5.3 The High-Priority Interrupt Process
4.4.5.4 Checking for Interrupts
4.4.6 Timer Interrupt Option
4.4.6.1 Timer Interrupt Option Architectural Additions
4.4.6.2 Clock Counting and Comparison
4.5 Options for Local Memory
4.5.1 General Cache Option Features
4.5.1.1 Cache Terminology
4.5.1.2 Cache Tag Format
4.5.1.3 Cache Prefetch
4.5.2 Instruction Cache Option
4.5.2.1 Instruction Cache Option Architectural Additions
4.5.3 Instruction Cache Test Option
4.5.3.1 Instruction Cache Test Option Architectural Additions
4.5.4 Instruction Cache Index Lock Option
4.5.4.1 Instruction Cache Index Lock Option Architectural Additions
4.5.5 Data Cache Option
4.5.5.1 Data Cache Option Architectural Additions
4.5.6 Data Cache Test Option
4.5.6.1 Data Cache Test Option Architectural Additions
4.5.7 Data Cache Index Lock Option
4.5.7.1 Data Cache Index Lock Option Architectural Additions
4.5.8 General RAM/ROM Option Features
4.5.9 Instruction RAM Option
4.5.9.1 Instruction RAM Option Architectural Additions
4.5.10 Instruction ROM Option
4.5.10.1 Instruction ROM Option Architectural Additions
4.5.11 Data RAM Option
4.5.11.1 Data RAM Option Architectural Additions
4.5.12 Data ROM Option
4.5.12.1 Data ROM Option Architectural Additions
4.5.13 XLMI Option
4.5.13.1 XLMI Option Architectural Additions
4.5.14 Hardware Alignment Option
4.5.15 Memory ECC/Parity Option
4.5.15.1 Memory ECC/Parity Option Architectural Additions
4.5.15.2 Memory Error Information Registers
4.5.15.3 The Exception Registers
4.5.15.4 Memory Error Semantics
4.6 Options for Memory Protection and Translation
4.6.1 Overview of Memory Management Concepts
4.6.1.1 Overview of Memory Translation
4.6.1.2 Overview of Memory Protection
4.6.1.3 Overview of Attributes
4.6.2 The Memory Access Process
4.6.2.1 Choose the TLB
4.6.2.2 Lookup in the TLB
4.6.2.3 Check the Access Rights
4.6.2.4 Direct the Access to Local Memory
4.6.2.5 Direct the Access to PIF
4.6.2.6 Direct the Access to Cache
4.6.3 Region Protection Option
4.6.3.1 Region Protection Option Architectural Additions
4.6.3.2 Formats for Accessing Region Protection Option TLB Entries
4.6.3.3 Region Protection Option Memory Attributes
4.6.4 Region Translation Option
4.6.4.1 Region Translation Option Architectural Additions
4.6.4.2 Region Translation Option Formats for Accessing TLB Entries
4.6.4.3 Region Translation Option Memory Attributes
4.6.5 MMU Option
4.6.5.1 MMU Option Architectural Additions
4.6.5.2 MMU Option Register Formats
4.6.5.3 The Structure of the MMU Option TLBs
4.6.5.4 The MMU Option Memory Map
4.6.5.5 Formats for Writing MMU Option TLB Entries
4.6.5.6 Formats for Reading MMU Option TLB Entries
4.6.5.7 Formats for Probing MMU Option TLB Entries
4.6.5.8 Format for Invalidating MMU Option TLB Entries
4.6.5.9 MMU Option Auto-Refill TLB Ways and PTE Format
4.6.5.10 MMU Option Memory Attributes
4.6.5.11 MMU Option Operation Semantics
4.7 Options for Other Purposes
4.7.1 Windowed Register Option
4.7.1.1 Windowed Register Option Architectural Additions
4.7.1.2 Managing Physical Registers
4.7.1.3 Window Overflow Check
4.7.1.4 Call, Entry, and Return Mechanism
4.7.1.5 Windowed Procedure-Call Protocol
4.7.1.6 Window Overflow and Underflow to and from the Program Stack
4.7.2 Processor Interface Option
4.7.2.1 Processor Interface Option Architectural Additions
4.7.3 Miscellaneous Special Registers Option
4.7.3.1 Miscellaneous Special Registers Option Architectural Additions
4.7.4 Thread Pointer Option
4.7.4.1 Thread Pointer Option Architectural Additions
4.7.5 Processor ID Option
4.7.5.1 Processor ID Option Architectural Additions
4.7.6 Debug Option
4.7.6.1 Debug Option Architectural Additions
4.7.6.2 Debug Cause Register
4.7.6.3 Using Breakpoints
4.7.6.4 Debug Exceptions
4.7.6.5 Instruction Counting
4.7.6.6 Debug Registers
4.7.6.7 Debug Interrupts
4.7.6.8 The checkIcount Procedure
4.7.7 Trace Port Option
4.7.7.1 Trace Port Option Architectural Additions
5. Processor State
5.1 General Registers
5.2 Program Counter
5.3 Special Registers
5.3.1 Reading and Writing Special Registers
5.3.2 LOOP Special Registers
5.3.3 MAC16 Special Registers
5.3.4 Other Unprivileged Special Registers
5.3.5 Processor Status Special Register
5.3.6 Windowed Register Option Special Registers
5.3.7 Memory Management Special Registers
5.3.8 Exception Support Special Registers
5.3.9 Exception State Special Registers
5.3.10 Interrupt Special Registers
5.3.11 Timing Special Registers
5.3.12 Breakpoint Special Registers
5.3.13 Other Privileged Special Registers
5.4 User Registers
5.4.1 Reading and Writing User Registers
5.4.2 The List of User Registers
5.5 TLB Entries
5.6 Additional Register Files
5.7 Caches and Local Memories
6. Instruction Descriptions
ABS ar, at
ABS.S fr, fs
ADD ar, as, at
ADD.N ar, as, at
ADD.S fr, fs, ft
ADDI at, as, -128..127
ADDI.N ar, as, imm
ADDMI at, as, -32768..32512
ADDX2 ar, as, at
ADDX4 ar, as, at
ADDX8 ar, as, at
ALL4 bt, bs
ALL8 bt, bs
AND ar, as, at
ANDB br, bs, bt
ANDBC br, bs, bt
ANY4 bt, bs
ANY8 bt, bs
BALL as, at, label
BANY as, at, label
BBC as, at, label
BBCI as, 0..31, label
BBCI.L as, 0..31, label
BBS as, at, label
BBSI as, 0..31, label
BBSI.L as, 0..31, label
BEQ as, at, label
BEQI as, imm, label
BEQZ as, label
BEQZ.N as, label
BF bs, label
BGE as, at, label
BGEI as, imm, label
BGEU as, at, label
BGEUI as, imm, label
BGEZ as, label
BLT as, at, label
BLTI as, imm, label
BLTU as, at, label
BLTUI as, imm, label
BLTZ as, label
BNALL as, at, label
BNE as, at, label
BNEI as, imm, label
BNEZ as, label
BNEZ.N as, label
BNONE as, at, label
BREAK 0..15, 0..15
BREAK.N 0..15
BT bs, label
CALL0 label
CALL4 label
CALL8 label
CALL12 label
CALLX0 as
CALLX4 as
CALLX8 as
CALLX12 as
CEIL.S ar, fs, 0..15
CLAMPS ar, as, 7..22
DHI as, 0..1020
DHU as, 0..240
DHWB as, 0..1020
DHWBI as, 0..1020
DII as, 0..1020
DIU as, 0..240
DIWB as, 0..240
DIWBI as, 0..240
DPFL as, 0..240
DPFR as, 0..1020
DPFRO as, 0..1020
DPFW as, 0..1020
DPFWO as, 0..1020
DSYNC
ENTRY as, 0..32760
ESYNC
EXCW
EXTUI ar, at, shiftimm, maskimm
EXTW
FLOAT.S fr, as, 0..15
FLOOR.S ar, fs, 0..15
IDTLB as
IHI as, 0..1020
IHU as, 0..240
III as, 0..1020
IITLB as
IIU as, 0..240
ILL
ILL.N
IPF as, 0..1020
IPFL as, 0..240
ISYNC
J label
J.L label, an
JX as
L8UI at, as, 0..255
L16SI at, as, 0..510
L16UI at, as, 0..510
L32AI at, as, 0..1020
L32E at, as, -64..-4
L32I at, as, 0..1020
L32I.N at, as, 0..60
L32R at, label
LDCT at, as
LDDEC mw, as
LDINC mw, as
LICT at, as
LICW at, as
LOOP as, label
LOOPGTZ as, label
LOOPNEZ as, label
LSI ft, as, 0..1020
LSIU ft, as, 0..1020
LSX fr, as, at
LSXU fr, as, at
MADD.S fr, fs, ft
MAX ar, as, at
MAXU ar, as, at
MEMW
MIN ar, as, at
MINU ar, as, at
MOV ar, as
MOV.N at, as
MOV.S fr, fs
MOVEQZ ar, as, at
MOVEQZ.S fr, fs, at
MOVF ar, as, bt
MOVF.S fr, fs, bt
MOVGEZ ar, as, at
MOVGEZ.S fr, fs, at
MOVI at, -2048..2047
MOVI.N as, -32..95
MOVLTZ ar, as, at
MOVLTZ.S fr, fs, at
MOVNEZ ar, as, at
MOVNEZ.S fr, fs, at
MOVSP at, as
MOVT ar, as, bt
MOVT.S fr, fs, bt
MSUB.S fr, fs, ft
MUL.AA.* as, at
MUL.AD.* as, my
MUL.DA.* mx, at
MUL.DD.* mx, my
MUL.S fr, fs, ft
MUL16S ar, as, at
MUL16U ar, as, at
MULA.AA.* as, at
MULA.AD.* as, my
MULA.DA.* mx, at
MULA.DA.*.LDDEC mw, as, mx, at
MULA.DA.*.LDINC mw, as, mx, at
MULA.DD.* mx, my
MULA.DD.*.LDDEC mw, as, mx, my
MULA.DD.*.LDINC mw, as, mx, my
MULL ar, as, at
MULS.AA.* as, at
MULS.AD.* as, my
MULS.DA.* mx, at
MULS.DD.* mx, my
MULSH ar, as, at
MULUH ar, as, at
NEG ar, at
NEG.S fr, fs
NOP
NOP.N
NSA at, as
NSAU at, as
OEQ.S br, fs, ft
OLE.S br, fs, ft
OLT.S br, fs, ft
OR ar, as, at
ORB br, bs, bt
ORBC br, bs, bt
PDTLB at, as
PITLB at, as
QUOS ar, as, at
QUOU ar, as, at
RDTLB0 at, as
RDTLB1 at, as
REMS ar, as, at
REMU ar, as, at
RER at, as
RET
RET.N
RETW
RETW.N
RFDD
RFDE
RFDO
RFE
RFI 0..15
RFME
RFR ar, fs
RFUE
RFWO
RFWU
RITLB0 at, as
RITLB1 at, as
ROTW -8..7
ROUND.S ar, fs, 0..15
RSIL at, 0..15
RSR.* at
RSR at, *
RSR at, 0..255
RSYNC
RUR.* ar
RUR ar, *
S8I at, as, 0..255
S16I at, as, 0..510
S32C1I at, as, 0..1020
S32E at, as, -64..-4
S32I at, as, 0..1020
S32I.N at, as, 0..60
S32RI at, as, 0..1020
SDCT at, as
SEXT ar, as, 7..22
SICT at, as
SICW at, as
SIMCALL
SLL ar, as
SLLI ar, as, 1..31
SRA ar, at
SRAI ar, at, 0..31
SRC ar, as, at
SRL ar, at
SRLI ar, at, 0..15
SSA8B as
SSA8L as
SSAI 0..31
SSI ft, as, 0..1020
SSIU ft, as, 0..1020
SSL as
SSR as
SSX fr, as, at
SSXU fr, as, at
SUB ar, as, at
SUB.S fr, fs, ft
SUBX2 ar, as, at
SUBX4 ar, as, at
SUBX8 ar, as, at
SYSCALL
TRUNC.S ar, fs, 0..15
UEQ.S br, fs, ft
UFLOAT.S fr, as, 0..15
ULE.S br, fs, ft
ULT.S br, fs, ft
UMUL.AA.* as, at
UN.S br, fs, ft
UTRUNC.S ar, fs, 0..15
WAITI 0..15
WDTLB at, as
WER at, as
WFR fr, as
WITLB at, as
WSR.* at
WSR at, *
WSR at, 0..255
WUR.* at
WUR at,*
XOR ar, as, at
XORB br, bs, bt
XSR.* at
XSR at, *
XSR at, 0..255
7. Instruction Formats and Opcodes
7.1 Formats
7.1.1 RRR
7.1.2 RRI4
7.1.3 RRI8
7.1.4 RI16
7.1.5 RSR
7.1.6 CALL
7.1.7 CALLX
7.1.8 BRI8
7.1.9 BRI12
7.1.10 RRRN
7.1.11 RI7
7.1.12 RI6
7.2 Instruction Fields
7.3 Opcode Encodings
7.3.1 Opcode Maps
7.3.2 CUST0 and CUST1 Opcode Encodings
7.3.3 Cache-Option Opcode Encodings (Implementation-Specific)
8. Using the Xtensa Architecture
8.1 The Windowed Register and CALL0 ABIs
8.1.1 Windowed Register Usage and Stack Layout
8.1.2 CALL0 Register Usage and Stack Layout
8.1.3 Data Types and Alignment
8.1.4 Argument Passing
8.1.5 Return Values
8.1.6 Variable Arguments
8.1.7 Other Register Conventions
8.1.8 Nested Functions
8.1.9 Stack Initialization
8.2 Other Conventions
8.2.1 Break Instruction Operands
8.2.2 System Calls
8.3 Assembly Code
8.3.1 Assembler Replacements and the Underscore Form
8.3.2 Instruction Idioms
8.3.3 Example: A FIR Filter with MAC16 Option
8.4 Performance
8.4.1 Processor Performance Terminology and Modeling
8.4.2 Xtensa Processor Family
A. Differences Between Old and Current Hardware
A.1 Added Instructions
A.2 Xtensa Exception Architecture 1
A.2.1 Differences in the PS Register
A.2.2 Exception Semantics
A.2.3 Checking ICOUNT
A.2.4 The BREAK and BREAK.N Instructions
A.2.5 The RETW and RETW.N Instructions
A.2.6 The RFDE Instruction
A.2.7 The RFE Instruction
A.2.8 The RFUE Instruction
RFUE
A.2.9 The RFWO and RFWU Instructions
A.2.10 Exception Virtual Address Register
A.2.11 Double Exceptions
A.2.12 Use of the RSIL Instruction
A.2.13 Writeback Cache
A.2.14 The Cache Attribute Register
A.3 New Exception Cause Values
A.4 ICOUNTLEVEL
A.5 MMU Option Memory Attributes
A.6 Special Register Read and Write
A.7 MMU Modification
A.8 Reduction of SYNC Instruction Requirements
Index
Xtensa®
Instruction Set Architecture (ISA)
Reference Manual
For All Xtensa Processor Cores
Tensilica, Inc.
3255-6 Scott Blvd.
Santa Clara, CA 95054
(408) 986-8000
fax (408) 986-8919
www.tensilica.com
© 2010 Tensilica, Inc.
Printed in the United States of America
All Rights Reserved
This publication is provided “AS IS.” Tensilica, Inc. (hereafter “Tensilica”) does not make any warranty of any kind, either ex-
pressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
Information in this document is provided solely to enable system and software developers to use Tensilica processors. Unless
specifically set forth herein, there are no express or implied patent, copyright or any other intellectual property rights or licens-
es granted hereunder to design or fabricate Tensilica integrated circuits or integrated circuits based on the information in this
document. Tensilica does not warrant that the contents of this publication, whether individually or as one or more groups,
meets your requirements or that the publication is error-free. This publication could include technical inaccuracies or typo-
graphical errors. Changes may be made to the information herein, and these changes may be incorporated in new editions of
this publication.
Tensilica and Xtensa are registered trademarks of Tensilica, Inc. The following terms are trademarks of Tensilica, Inc.: FLIX,
OSKit, Sea of Processors, TurboXim, Vectra, Xenergy, Xplorer, and XPRES. All other trademarks and registered trademarks
are the property of their respective companies.
Issue Date: 4/2010
RC-2010.1 Release
PD-09-0801-10-01
Tensilica, Inc.
3255-6 Scott Blvd.
Santa Clara, CA 95054
(408) 986-8000
fax (408) 986-8919
www.tensilica.com
Contents
Contents
1.
Introduction ...................................................................................................................1
1.1 What Problem is Tensilica Solving?.............................................................................1
1.1.1 Adding Architectural Enhancements ..................................................................1
1.1.2 Creating Custom Processor Configurations ........................................................4
1.1.3 Mapping the Architecture into Hardware.............................................................4
1.1.4 Development and Verification Tools ...................................................................5
1.2 The Xtensa Instruction Set Architecture.......................................................................5
1.2.1 Configurability .................................................................................................7
1.2.2 Extensibility.....................................................................................................8
1.2.2.1 State Extensions .....................................................................................9
1.2.2.2 Register File Extensions ..........................................................................9
1.2.2.3 Instruction Extensions..............................................................................9
1.2.2.4 Coprocessor Extensions ..........................................................................9
1.2.3 Time-to-Market ................................................................................................9
1.2.4 Code Density ................................................................................................10
1.2.5 Low Implementation Cost ...............................................................................10
1.2.6 Low-Power.................................................................................................... 11
1.2.7 Performance ................................................................................................. 11
1.2.8 Pipelines.......................................................................................................12
1.3 The Xtensa Processor Generator..............................................................................13
1.3.1 Processor Configuration .................................................................................13
1.3.2 System-Specific Instructions—The TIE Language .............................................13
2. Notation.......................................................................................................................17
2.1 Bit and Byte Order ..................................................................................................17
2.2 Expressions ...........................................................................................................19
2.3 Unsigned Semantics ...............................................................................................20
2.4 Case .....................................................................................................................20
2.5 Statements.............................................................................................................21
2.6 Instruction Fields.....................................................................................................21
3. Core Architecture .........................................................................................................23
3.1 Overview of the Core Architecture ............................................................................23
3.2 Processor-Configuration Parameters.........................................................................23
3.3 Registers ...............................................................................................................24
3.3.1 General (AR) Registers...................................................................................24
3.3.2 Shifts and the Shift Amount Register (SAR).......................................................25
3.3.3 Reading and Writing the Special Registers .......................................................26
3.4 Data Formats and Alignment....................................................................................26
3.5 Memory .................................................................................................................27
3.5.1 Memory Addressing .......................................................................................27
3.5.2 Addressing Modes .........................................................................................28
3.5.3 Program Counter ...........................................................................................29
3.5.4 Instruction Fetch............................................................................................29
3.5.4.1 Little-Endian Fetch Semantics ................................................................29
Xtensa Instruction Set Architecture (ISA) Reference Manual
iii
Contents
3.5.4.2 Big-Endian Fetch Semantics...................................................................31
3.6 Reset.....................................................................................................................32
3.7 Exceptions and Interrupts ........................................................................................32
3.8 Instruction Summary ...............................................................................................33
3.8.1 Load Instructions ...........................................................................................33
3.8.2 Store Instructions...........................................................................................36
3.8.3 Memory Access Ordering ...............................................................................39
3.8.4 Jump and Call Instructions..............................................................................40
3.8.5 Conditional Branch Instructions .......................................................................40
3.8.6 Move Instructions ..........................................................................................42
3.8.7 Arithmetic Instructions ....................................................................................43
3.8.8 Bitwise Logical Instructions.............................................................................44
3.8.9 Shift Instructions............................................................................................44
3.8.10 Processor Control Instructions.......................................................................45
4. Architectural Options....................................................................................................47
4.1 Overview of Options................................................................................................47
4.2 Core Architecture....................................................................................................50
4.3 Options for Additional Instructions.............................................................................53
4.3.1 Code Density Option......................................................................................53
4.3.1.1 Code Density Option Architectural Additions ............................................53
4.3.1.2 Branches..............................................................................................54
4.3.2 Loop Option ..................................................................................................54
4.3.2.1 Loop Option Architectural Additions.........................................................55
4.3.2.2 Restrictions on Loops ............................................................................55
4.3.2.3 Loops Disabled During Exceptions ..........................................................56
4.3.2.4 Loopback Semantics .............................................................................56
4.3.3 Extended L32R Option ...................................................................................56
4.3.3.1 Extended L32R Option Architectural Additions..........................................56
4.3.3.2 The Literal Base Register.......................................................................57
4.3.4 16-bit Integer Multiply Option ..........................................................................57
4.3.4.1 16-bit Integer Multiply Option Architectural Additions.................................58
4.3.5 32-bit Integer Multiply Option ..........................................................................58
4.3.5.1 32-bit Integer Multiply Option Architectural Additions.................................58
4.3.6 32-bit Integer Divide Option ............................................................................59
4.3.6.1 32-bit Integer Divide Option Architectural Additions...................................59
4.3.7 MAC16 Option...............................................................................................60
4.3.7.1 MAC16 Option Architectural Additions .....................................................60
4.3.7.2 Use With CLAMPS Instruction ................................................................62
4.3.8 Miscellaneous Operations Option ....................................................................62
4.3.8.1 Miscellaneous Operations Option Architectural Additions...........................62
4.3.9 Coprocessor Option .......................................................................................63
4.3.9.1 Coprocessor Option Architectural Additions .............................................64
4.3.9.2 Coprocessor Context Switch...................................................................64
4.3.10 Boolean Option............................................................................................65
4.3.10.1 Boolean Option Architectural Additions ..................................................65
4.3.10.2 Booleans ............................................................................................66
4.3.11 Floating-Point Coprocessor Option.................................................................67
4.3.11.1 Floating-Point Coprocessor Option Architectural Additions ....................... 67
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4.3.11.2 Floating-Point Representation ...............................................................69
4.3.11.3 Floating-Point State..............................................................................69
4.3.11.4 Floating-Point Exceptions .....................................................................71
4.3.11.5 Floating-Point Instructions ....................................................................71
4.3.12 Multiprocessor Synchronization Option...........................................................74
4.3.12.1 Memory Access Ordering .....................................................................74
4.3.12.2 Multiprocessor Synchronization Option Architectural Additions .................75
4.3.12.3 Inter-Processor Communication with the L32AI and S32RI Instructions ...76
4.3.13 Conditional Store Option...............................................................................77
4.3.13.1 Conditional Store Option Architectural Additions .....................................77
4.3.13.2 Exclusive Access with the S32C1I Instruction ........................................78
4.3.13.3 Use Models for the S32C1I Instruction ..................................................79
4.3.13.4 The Atomic Operation Control Register (ATOMCTL) under the Conditional
Store Option ....................................................................................................80
4.3.13.5 Memory Ordering and the S32C1I Instruction ........................................81
4.4 Options for Interrupts and Exceptions........................................................................82
4.4.1 Exception Option ...........................................................................................82
4.4.1.1 Exception Option Architectural Additions..................................................83
4.4.1.2 Exception Causes under the Exception Option .........................................85
4.4.1.3 The Miscellaneous Program State Register (PS) under the Exception Option...
87
4.4.1.4 Value of Variables under the Exception Option .........................................88
4.4.1.5 The Exception Cause Register (EXCCAUSE) under the Exception Option.....89
4.4.1.6 The Exception Virtual Address Register (EXCVADDR) under the Exception
Option.............................................................................................................91
4.4.1.7 The Exception Program Counter (EPC) under the Exception Option ............91
4.4.1.8 The Double Exception Program Counter (DEPC) under the Exception Option...
92
4.4.1.9 The Exception Save Register (EXCSAVE) under the Exception Option.........92
4.4.1.10 Handling of Exceptional Conditions under the Exception Option ...............93
4.4.1.11 Exception Priority under the Exception Option.........................................96
4.4.2 Relocatable Vector Option ..............................................................................98
4.4.2.1 Relocatable Vector Option Architectural Additions.....................................99
4.4.3 Unaligned Exception Option............................................................................99
4.4.3.1 Unaligned Exception Option Architectural Additions ................................100
4.4.4 Interrupt Option ...........................................................................................100
4.4.4.1 Interrupt Option Architectural Additions..................................................101
4.4.4.2 Specifying Interrupts ............................................................................102
4.4.4.3 The Level-1 Interrupt Process...............................................................105
4.4.4.4 Use of Interrupt Instructions..................................................................106
4.4.5 High-Priority Interrupt Option.........................................................................106
4.4.5.1 High-Priority Interrupt Option Architectural Additions ...............................106
4.4.5.2 Specifying High-Priority Interrupts .........................................................108
4.4.5.3 The High-Priority Interrupt Process........................................................108
4.4.5.4 Checking for Interrupts.........................................................................109
4.4.6 Timer Interrupt Option .................................................................................. 110
4.4.6.1 Timer Interrupt Option Architectural Additions......................................... 110
4.4.6.2 Clock Counting and Comparison........................................................... 111
4.5 Options for Local Memory...................................................................................... 111
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4.5.1 General Cache Option Features.....................................................................111
4.5.1.1 Cache Terminology.............................................................................. 112
4.5.1.2 Cache Tag Format............................................................................... 112
4.5.1.3 Cache Prefetch ................................................................................... 113
4.5.2 Instruction Cache Option .............................................................................. 115
4.5.2.1 Instruction Cache Option Architectural Additions..................................... 115
4.5.3 Instruction Cache Test Option ....................................................................... 116
4.5.3.1 Instruction Cache Test Option Architectural Additions.............................. 116
4.5.4 Instruction Cache Index Lock Option.............................................................. 117
4.5.4.1 Instruction Cache Index Lock Option Architectural Additions .................... 117
4.5.5 Data Cache Option ...................................................................................... 118
4.5.5.1 Data Cache Option Architectural Additions............................................. 119
4.5.6 Data Cache Test Option ...............................................................................121
4.5.6.1 Data Cache Test Option Architectural Additions ......................................121
4.5.7 Data Cache Index Lock Option......................................................................122
4.5.7.1 Data Cache Index Lock Option Architectural Additions ............................122
4.5.8 General RAM/ROM Option Features..............................................................123
4.5.9 Instruction RAM Option ................................................................................124
4.5.9.1 Instruction RAM Option Architectural Additions.......................................124
4.5.10 Instruction ROM Option ..............................................................................125
4.5.10.1 Instruction ROM Option Architectural Additions.....................................125
4.5.11 Data RAM Option.......................................................................................126
4.5.11.1 Data RAM Option Architectural Additions .............................................126
4.5.12 Data ROM Option ......................................................................................126
4.5.12.1 Data ROM Option Architectural Additions.............................................127
4.5.13 XLMI Option ..............................................................................................127
4.5.13.1 XLMI Option Architectural Additions ....................................................127
4.5.14 Hardware Alignment Option ........................................................................128
4.5.15 Memory ECC/Parity Option.........................................................................128
4.5.15.1 Memory ECC/Parity Option Architectural Additions ...............................129
4.5.15.2 Memory Error Information Registers ....................................................130
4.5.15.3 The Exception Registers ....................................................................137
4.5.15.4 Memory Error Semantics....................................................................137
4.6 Options for Memory Protection and Translation ........................................................138
4.6.1 Overview of Memory Management Concepts..................................................139
4.6.1.1 Overview of Memory Translation...........................................................139
4.6.1.2 Overview of Memory Protection ............................................................142
4.6.1.3 Overview of Attributes..........................................................................144
4.6.2 The Memory Access Process........................................................................145
4.6.2.1 Choose the TLB ..................................................................................146
4.6.2.2 Lookup in the TLB ...............................................................................147
4.6.2.3 Check the Access Rights .....................................................................148
4.6.2.4 Direct the Access to Local Memory .......................................................148
4.6.2.5 Direct the Access to PIF.......................................................................150
4.6.2.6 Direct the Access to Cache ..................................................................150
4.6.3 Region Protection Option..............................................................................150
4.6.3.1 Region Protection Option Architectural Additions ....................................151
4.6.3.2 Formats for Accessing Region Protection Option TLB Entries ..................152
4.6.3.3 Region Protection Option Memory Attributes ..........................................154
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4.6.4 Region Translation Option ............................................................................156
4.6.4.1 Region Translation Option Architectural Additions...................................156
4.6.4.2 Region Translation Option Formats for Accessing TLB Entries .................156
4.6.4.3 Region Translation Option Memory Attributes.........................................158
4.6.5 MMU Option................................................................................................158
4.6.5.1 MMU Option Architectural Additions ......................................................159
4.6.5.2 MMU Option Register Formats..............................................................161
PTEVADDR ............................................................................................161
RASID....................................................................................................161
ITLBCFG ................................................................................................162
DTLBCFG...............................................................................................162
4.6.5.3 The Structure of the MMU Option TLBs .................................................163
4.6.5.4 The MMU Option Memory Map .............................................................164
4.6.5.5 Formats for Writing MMU Option TLB Entries .........................................165
4.6.5.6 Formats for Reading MMU Option TLB Entries .......................................168
4.6.5.7 Formats for Probing MMU Option TLB Entries ........................................171
4.6.5.8 Format for Invalidating MMU Option TLB Entries ....................................172
4.6.5.9 MMU Option Auto-Refill TLB Ways and PTE Format ...............................174
4.6.5.10 MMU Option Memory Attributes ..........................................................175
4.6.5.11 MMU Option Operation Semantics.......................................................178
4.7 Options for Other Purposes....................................................................................179
4.7.1 Windowed Register Option ...........................................................................180
4.7.1.1 Windowed Register Option Architectural Additions..................................181
4.7.1.2 Managing Physical Registers................................................................183
4.7.1.3 Window Overflow Check ......................................................................184
4.7.1.4 Call, Entry, and Return Mechanism .......................................................186
4.7.1.5 Windowed Procedure-Call Protocol .......................................................187
4.7.1.6 Window Overflow and Underflow to and from the Program Stack..............192
4.7.2 Processor Interface Option ...........................................................................194
4.7.2.1 Processor Interface Option Architectural Additions..................................195
4.7.3 Miscellaneous Special Registers Option .........................................................195
4.7.3.1 Miscellaneous Special Registers Option Architectural Additions ...............195
4.7.4 Thread Pointer Option ..................................................................................196
4.7.4.1 Thread Pointer Option Architectural Additions ........................................196
4.7.5 Processor ID Option.....................................................................................196
4.7.5.1 Processor ID Option Architectural Additions ...........................................196
4.7.6 Debug Option..............................................................................................197
4.7.6.1 Debug Option Architectural Additions ....................................................197
4.7.6.2 Debug Cause Register.........................................................................198
4.7.6.3 Using Breakpoints ...............................................................................199
4.7.6.4 Debug Exceptions ...............................................................................201
4.7.6.5 Instruction Counting.............................................................................201
4.7.6.6 Debug Registers .................................................................................202
4.7.6.7 Debug Interrupts .................................................................................203
4.7.6.8 The checkIcount Procedure..............................................................203
4.7.7 Trace Port Option ........................................................................................203
4.7.7.1 Trace Port Option Architectural Additions...............................................204
5. Processor State..........................................................................................................205
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Contents
6.
7.
5.1 General Registers.................................................................................................208
5.2 Program Counter ..................................................................................................208
5.3 Special Registers..................................................................................................208
5.3.1 Reading and Writing Special Registers........................................................... 211
5.3.2 LOOP Special Registers...............................................................................212
5.3.3 MAC16 Special Registers .............................................................................213
5.3.4 Other Unprivileged Special Registers.............................................................215
5.3.5 Processor Status Special Register .................................................................216
5.3.6 Windowed Register Option Special Registers .................................................221
5.3.7 Memory Management Special Registers ........................................................221
5.3.8 Exception Support Special Registers .............................................................223
5.3.9 Exception State Special Registers .................................................................226
5.3.10 Interrupt Special Registers ..........................................................................229
5.3.11 Timing Special Registers.............................................................................231
5.3.12 Breakpoint Special Registers.......................................................................233
5.3.13 Other Privileged Special Registers...............................................................235
5.4 User Registers......................................................................................................237
5.4.1 Reading and Writing User Registers ..............................................................237
5.4.2 The List of User Registers ............................................................................238
5.5 TLB Entries ..........................................................................................................239
5.6 Additional Register Files ........................................................................................240
5.7 Caches and Local Memories ..................................................................................240
Instruction Descriptions..............................................................................................243
Instruction Formats and Opcodes ................................................................................569
7.1 Formats ...............................................................................................................569
7.1.1 RRR...........................................................................................................569
7.1.2 RRI4 ..........................................................................................................569
7.1.3 RRI8 ..........................................................................................................570
7.1.4 RI16...........................................................................................................570
7.1.5 RSR...........................................................................................................570
7.1.6 CALL..........................................................................................................571
7.1.7 CALLX........................................................................................................571
7.1.8 BRI8...........................................................................................................571
7.1.9 BRI12.........................................................................................................572
7.1.10 RRRN.......................................................................................................572
7.1.11 RI7 ...........................................................................................................572
7.1.12 RI6...........................................................................................................573
7.2 Instruction Fields...................................................................................................573
7.3 Opcode Encodings................................................................................................574
7.3.1 Opcode Maps..............................................................................................575
7.3.2 CUST0 and CUST1 Opcode Encodings .........................................................586
7.3.3 Cache-Option Opcode Encodings (Implementation-Specific) ............................586
8. Using the Xtensa Architecture .....................................................................................587
8.1 The Windowed Register and CALL0 ABIs................................................................587
8.1.1 Windowed Register Usage and Stack Layout..................................................587
8.1.2 CALL0 Register Usage and Stack Layout .......................................................589
8.1.3 Data Types and Alignment............................................................................589
8.1.4 Argument Passing .......................................................................................590
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