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RTL8198数据手册.pdf
A Table of Contents
1. General Description
2. Features
3. Block Diagram
4. Pin Assignments
5. Pin Descriptions
5.1. Configuration Upon Power On Strapping
5.2. GMAC Pin Mode Description
5.3. Shared I/O Pin Mapping
5.4. Memory Map
6. Memory Controller
6.1. SDR DRAM Control Interface
6.2. DDR DRAM Controller
6.3. SPI Flash Controller
6.4. Software Register Definitions
7. Peripheral and MISC Control
7.1. Interrupt Control
7.2. Timer Control
7.3. GPIO Control
7.4. GPIO Shared Pin Configured Mapping List
8. Green Ethernet
8.1. Cable Length Power Saving
8.2. Link Down Power Saving
8.3. Energy Efficient Ethernet (EEE)
9. Ethernet Switch Core
9.1. Global Port Control Register
9.2. Per-port Configuration Register
9.3. Switch MSIC Control Register
9.4. Address Lookup Engine Control Register
9.4.1. Aging Timer Control Register
9.4.2. Module Switch Control Register
10. USB 2.0 Host Interface
10.1. Open Host Controller Interface (OHCI) OperationalRegisters
10.2. EHCI Capability and Operational Registers
11. UART
11.1. Features
11.2. Interface Pins
11.3. UART Control Register
11.4. Baud Rate
12. Non-Flash Booting Interface (NFBI)
12.1. Block Diagram
12.2. NFBI Frame Format
12.3. NFBI Register Address Mapping
12.4. PHY Identifier Registers
12.5. Command Register
12.6. Address Registers
12.7. Data Register
12.8. System Status Register
12.9. RTL8198 Internal CPU NFBI Control Register
13. PCI Express Bus Interface
13.1. PCI Express Transmitter
13.2. PCI Express Receiver
13.3. PCI Express Address Mapping
13.4. PCI Express Host mode
14. DC Specifications
14.1. Operating Conditions
14.2. Total Power Consumption
14.3. SDR DRAM Bus DC Parameters
14.4. DDR DRAM Bus DC Parameters
14.5. Flash Bus DC Parameters
14.6. USB v1.1 DC Parameters
14.7. USB v2.0 DC Parameters
14.8. UART DC Parameters
14.9. GPIO DC Parameters
14.10. JTAG DC Parameters
14.11. MII DC Parameters
14.12. GMII DC Parameters
14.13. RGMII DC Parameters
14.14. Reset DC Parameters
14.15. LED DC Parameters
15. AC Specifications
15.1. Clock Signal Timing
15.2. Bus Signal Timing
15.3. PCI Express Bus Parameters
16. Thermal Characteristics
16.1. Thermal Operating Range
16.2. Thermal Parameters
17. Mechanical Dimensions
18. Ordering Information
B Table of Contents
1. VLAN Table
1.1. VLAN Table (4K-Entry)
1.2. Table Access
1.3. SWTA (Direct Access)
1.4. Table Write
1.5. *Table Entry Bit Allocation
2. CPU Interface (NIC)
2.1. Switch Core and RISC Interface
2.2. Switch Core Driver Overview
2.3. NIC Driver
2.4. Tx Registers
2.5. Tx Descriptor Format
2.6. *Packet Header and mbuf Header Format
2.7. CPU Interface Register (Base Address: 0xB801-0000)
C Table of Contents
1. VLAN Table
1.1. VLAN Table (4K-Entry)
1.2. Table Access
1.3. SWTA (Direct Access)
1.4. Table Write
1.5. *Table Entry Bit Allocation
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IEEE 802.11n GIGABIT ETHERNET
AP/ROUTER NETWORK PROCESSOR
Rev. 0.91a
25 October 2010
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8198-GR
Confidential for ⼴
PRELIMINARY DATASHEET
(CONFIDENTIAL: Development Partners Only)
RTL8198
Datasheet
COPYRIGHT
©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
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TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek 11n AP/Routers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Confidential for ⼴
IEEE 802.11n Gigabit Ethernet AP/Router Network Processor
Summary
Preliminary release.
Revision
0.91a
Release Date
2010/10/25
ii
Track ID: JATR-2265-11 Rev. 0.91
Table of Contents
RTL8198
Datasheet
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5.
5.3.
5.4.
6.1.
6.2.
6.3.
6.4.
4.1.
5.1.
5.2.
1. GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
2.
3.
BLOCK DIAGRAM...........................................................................................................................................................5
PIN ASSIGNMENTS .........................................................................................................................................................6
4.
PACKAGE IDENTIFICATION...........................................................................................................................................7
PIN DESCRIPTIONS.........................................................................................................................................................7
CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................14
GMAC PIN MODE DESCRIPTION ...............................................................................................................................15
5.2.1. MAC Interface MII/GMII/RGMII Mode Pin Sharing Mappings..........................................................................15
5.2.2. GMII/RGMII Interface Pin Descriptions..............................................................................................................15
5.2.3. MII MAC Mode Interface Pin Descriptions .........................................................................................................16
5.2.4. MII PHY Mode Interface Pin Descriptions ..........................................................................................................16
SHARED I/O PIN MAPPING .........................................................................................................................................17
MEMORY MAP ...........................................................................................................................................................18
6. MEMORY CONTROLLER............................................................................................................................................21
SDR DRAM CONTROL INTERFACE ...........................................................................................................................21
6.1.1. Features................................................................................................................................................................21
6.1.2. Bank2 and Bank3..................................................................................................................................................21
DDR DRAM CONTROLLER .......................................................................................................................................22
6.2.1. Features................................................................................................................................................................22
SPI FLASH CONTROLLER ...........................................................................................................................................22
6.3.1. Features................................................................................................................................................................22
6.3.2. Pin Mode and Definition of Serial and Dual I/O..................................................................................................22
SOFTWARE REGISTER DEFINITIONS ...........................................................................................................................23
6.4.1. Memory Control Register (MCR) (0xB800_1000) ...............................................................................................23
6.4.2. DRAM Configuration Register (DCR) (0xB800_1004)........................................................................................24
6.4.3. DRAM Timing Register (DTR) (0xB800_1008)....................................................................................................25
6.4.4. DDR DRAM Calibration Register (DDCR) (0xB800_1050)................................................................................26
6.4.5.
SPI Flash Configuration Register (SFCR) (0xB800_1200)..................................................................................27
6.4.6.
SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204).............................................................................27
SPI Flash Control & Status Register (SFCSR) (0xB800_1208)...........................................................................28
6.4.7.
6.4.8.
SPI Flash Data Register (SFDR) (0xB800_120C) ...............................................................................................29
6.4.9.
SPI Flash Data Register 2 (SFDR2) (0xB800_1210)...........................................................................................29
PERIPHERAL AND MISC CONTROL ........................................................................................................................30
INTERRUPT CONTROL.................................................................................................................................................30
7.1.1.
Interrupt Control Register Address Mapping.......................................................................................................30
7.1.2. Global Interrupt Mask Register............................................................................................................................30
7.1.3. Global Interrupt Status Register...........................................................................................................................31
Interrupt Routing Register 0.................................................................................................................................32
7.1.4.
7.1.5.
Interrupt Routing Register 1.................................................................................................................................32
7.1.6.
Interrupt Routing Register 2.................................................................................................................................32
7.1.7.
Interrupt Routing Register 3.................................................................................................................................33
TIMER CONTROL........................................................................................................................................................34
7.2.1. Timer Control Register Address Mapping............................................................................................................34
7.2.2. Timer/Counter 0 Data Register ............................................................................................................................34
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IEEE 802.11n Gigabit Ethernet AP/Router Network Processor
7.
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7.2.
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7.3.
7.4.
9.
RTL8198
Datasheet
7.2.3. Timer/Counter 1 Data Register ............................................................................................................................34
7.2.4. Timer/Counter 0 Counter Register.......................................................................................................................34
7.2.5. Timer/Counter 1 Counter Register.......................................................................................................................35
7.2.6. Timer/Counter Control Register...........................................................................................................................35
7.2.7. Timer/Counter Interrupt Register.........................................................................................................................35
7.2.8. Clock Division Base Register ...............................................................................................................................36
7.2.9. Watchdog Control Register ..................................................................................................................................36
GPIO CONTROL.........................................................................................................................................................37
7.3.1. GPIO Register Set (0xB800_3500).......................................................................................................................37
7.3.2. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)............................................................38
7.3.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800-3508)...........................................................38
7.3.4. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C) ..........................................................................38
7.3.5. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510) ...........................................................39
7.3.6. Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514) ..........................................................................39
7.3.7. Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518).........................................................................40
7.3.8. GPIO Port E, F, G, H Control Register (PEFGH_CNR) (0xB800_351C)...........................................................40
7.3.9. GPIO Port E, F, G, H Direction Register (PEFGH_DIR) (0xB800_3524) .........................................................41
7.3.10.
Port E, F, G, H Data Register (PEFGH_DAT) (0xB800_3528)......................................................................41
Port E, F, G, H Interrupt Status Register (PEFGH_ISR) (0xB800-352C) ......................................................42
7.3.11.
7.3.12.
Port E, F Interrupt Mask Register (PEF_IMR) (0xB800_3530) .....................................................................42
7.3.13.
Port G, H Interrupt Mask Register (PGH_IMR) (0xB800_3534)....................................................................42
GPIO SHARED PIN CONFIGURED MAPPING LIST........................................................................................................44
Shared Pin Register (PIN_MUX_SEL,0xB800_0040~0xB800_0043h) ...............................................................44
7.4.1.
Shared Pin Register (PIN_MUX_SEL_2,0xB800_0044~0xB800_0047h) ...........................................................45
7.4.2.
8. GREEN ETHERNET.......................................................................................................................................................46
CABLE LENGTH POWER SAVING ................................................................................................................................46
LINK DOWN POWER SAVING......................................................................................................................................46
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................46
ETHERNET SWITCH CORE ........................................................................................................................................48
GLOBAL PORT CONTROL REGISTER...........................................................................................................................48
9.1.1. MAC Configuration Register................................................................................................................................48
Description :....................................................................................................................................................48
9.1.1.1
9.1.2. Port Mirror Control Register ...............................................................................................................................49
Port Mirroring Control Register .....................................................................................................................49
9.1.2.1
9.1.3. Frame Filtering Control Register.........................................................................................................................50
9.1.3.1
Broadcast Storm Control Register...................................................................................................................50
9.1.3.2
Checksum Control Register .............................................................................................................................51
PER-PORT CONFIGURATION REGISTER.......................................................................................................................52
9.2.1. Port Interface Type Configuration Register.........................................................................................................52
9.2.2. Port Configuration Register .................................................................................................................................53
9.2.3. Port Status Register..............................................................................................................................................57
SWITCH MSIC CONTROL REGISTER...........................................................................................................................58
9.3.1. Chip Version ID Register .....................................................................................................................................58
9.3.2.
System Initial and Reset Register .........................................................................................................................58
ADDRESS LOOKUP ENGINE CONTROL REGISTER........................................................................................................61
9.4.1. Aging Timer Control Register ..............................................................................................................................61
9.4.2. Module Switch Control Register...........................................................................................................................62
USB 2.0 HOST INTERFACE .....................................................................................................................................64
10.1. OPEN HOST CONTROLLER INTERFACE (OHCI) OPERATIONAL REGISTERS ................................................................64
Open Host Controller Interface (OHCI) Operational Registers .....................................................................64
Control and Status Partition............................................................................................................................65
Memory Pointer Partition................................................................................................................................70
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Track ID: JATR-2265-11 Rev. 0.91
8.1.
8.2.
8.3.
9.1.
10.1.1.
10.1.2.
10.1.3.
9.2.
9.3.
9.4.
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10.1.4.
10.1.5.
10.2.1.
10.2.2.
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Datasheet
Frame Counter Partition .................................................................................................................................72
Root Hub Partition ..........................................................................................................................................74
EHCI CAPABILITY AND OPERATIONAL REGISTERS....................................................................................................80
Capability Registers.........................................................................................................................................80
Operational Registers......................................................................................................................................81
UART ............................................................................................................................................................................92
FEATURES ..................................................................................................................................................................92
11.1.
INTERFACE PINS.........................................................................................................................................................92
11.2.
11.3. UART CONTROL REGISTER.......................................................................................................................................92
UART Control Register Address Mapping ......................................................................................................92
11.3.1.
UART Receiver Buffer Register (DLAB=0).....................................................................................................93
11.3.2.
UART Transmitter Holding Register (DLAB=0).............................................................................................93
11.3.3.
UART Divisor Latch LSB (DLAB=1) ..............................................................................................................93
11.3.4.
UART Divisor Latch MSB (DLAB=1) .............................................................................................................93
11.3.5.
UART Interrupt Enable Register (DLAB=0) ...................................................................................................94
11.3.6.
UART Interrupt Identification Register ...........................................................................................................94
11.3.7.
UART FIFO Control Register..........................................................................................................................94
11.3.8.
11.3.9.
UART Line Control Register............................................................................................................................95
11.3.10. UART Modem Control Register.......................................................................................................................95
11.3.11. UART Line Status Register ..............................................................................................................................95
11.3.12. UART Modem Status Register .........................................................................................................................96
11.4. BAUD RATE ...............................................................................................................................................................97
NON-FLASH BOOTING INTERFACE (NFBI).......................................................................................................98
12.1. BLOCK DIAGRAM.......................................................................................................................................................98
12.2. NFBI FRAME FORMAT...............................................................................................................................................99
12.3. NFBI REGISTER ADDRESS MAPPING .........................................................................................................................99
12.4.
PHY IDENTIFIER REGISTERS....................................................................................................................................100
12.5. COMMAND REGISTER...............................................................................................................................................100
12.6. ADDRESS REGISTERS ...............................................................................................................................................101
12.7. DATA REGISTER.......................................................................................................................................................102
Command and Status Register.......................................................................................................................102
12.8.
SYSTEM STATUS REGISTER......................................................................................................................................103
Interrupt Mask Register.................................................................................................................................103
Interrupt Status Register................................................................................................................................104
12.9. RTL8198 INTERNAL CPU NFBI CONTROL REGISTER .............................................................................................105
Receive Command and Send Status Register.................................................................................................105
Interrupt Mask and Interrupt Status Register On NFBI ................................................................................106
PCI EXPRESS BUS INTERFACE...........................................................................................................................107
PCI EXPRESS TRANSMITTER ....................................................................................................................................107
PCI EXPRESS RECEIVER...........................................................................................................................................107
PCI EXPRESS ADDRESS MAPPING............................................................................................................................107
PCI EXPRESS HOST MODE........................................................................................................................................108
PCIE Host Mode Extended Register Address Mapping.................................................................................108
PCIE MDIO Register.....................................................................................................................................108
PCIE Interrupt Status Register......................................................................................................................109
PCIE Power Control Register .......................................................................................................................109
PCIE IP Configuration Register....................................................................................................................110
PCIE SRAM BIST Check Register .................................................................................................................110
DC SPECIFICATIONS.............................................................................................................................................111
14.1. OPERATING CONDITIONS .........................................................................................................................................111
14.2.
TOTAL POWER CONSUMPTION .................................................................................................................................111
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13.
13.1.
13.2.
13.3.
13.4.
12.7.1.
12.8.1.
12.8.2.
12.9.1.
12.9.2.
13.4.1.
13.4.2.
13.4.3.
13.4.4.
13.4.5.
13.4.6.
15.
15.1.1.
15.1.2.
15.1.3.
15.1.4.
15.2.1.
15.2.2.
15.2.3.
15.2.4.
15.2.5.
15.2.6.
15.2.7.
15.2.8.
15.2.9.
15.2.10.
15.3.1.
15.3.2.
15.3.3.
RTL8198
Datasheet
14.3.
SDR DRAM BUS DC PARAMETERS ........................................................................................................................112
14.4. DDR DRAM BUS DC PARAMETERS .......................................................................................................................112
14.5.
FLASH BUS DC PARAMETERS ..................................................................................................................................112
14.6. USB V1.1 DC PARAMETERS ....................................................................................................................................113
14.7. USB V2.0 DC PARAMETERS ....................................................................................................................................113
14.8. UART DC PARAMETERS .........................................................................................................................................113
14.9. GPIO DC PARAMETERS...........................................................................................................................................114
14.10.
JTAG DC PARAMETERS......................................................................................................................................114
14.11.
MII DC PARAMETERS .........................................................................................................................................114
GMII DC PARAMETERS ......................................................................................................................................115
14.12.
RGMII DC PARAMETERS....................................................................................................................................115
14.13.
14.14.
RESET DC PARAMETERS .....................................................................................................................................115
14.15.
LED DC PARAMETERS........................................................................................................................................116
AC SPECIFICATIONS.............................................................................................................................................117
15.1. CLOCK SIGNAL TIMING............................................................................................................................................117
SDR DRAM Clock Timing .............................................................................................................................118
MII Clock Timing...........................................................................................................................................119
GMII Clock Timing........................................................................................................................................120
RGMII Clock Timing .....................................................................................................................................121
15.2. BUS SIGNAL TIMING ................................................................................................................................................122
SDR DRAM Bus.............................................................................................................................................122
DDR DRAM Bus............................................................................................................................................124
Serial Flash Interface Output Timing............................................................................................................125
Serial Flash Interface Intput Timing..............................................................................................................126
MII Interface..................................................................................................................................................126
GMII Timing Characteristics.........................................................................................................................128
RGMII Timing Characteristics ......................................................................................................................129
JTAG Boundary Scan ....................................................................................................................................130
Power Sequence.............................................................................................................................................131
Power Configuration Timing.........................................................................................................................131
PCI EXPRESS BUS PARAMETERS..............................................................................................................................132
Differential Transmitter Parameters .............................................................................................................132
Differential Receiver Parameters ..................................................................................................................133
REFCLK Parameters.....................................................................................................................................133
THERMAL CHARACTERISTICS .........................................................................................................................138
THERMAL OPERATING RANGE .................................................................................................................................139
THERMAL PARAMETERS...........................................................................................................................................139
MECHANICAL DIMENSIONS...............................................................................................................................140
17.1. MECHANICAL DIMENSIONS NOTES ..........................................................................................................................140
ORDERING INFORMATION.................................................................................................................................141
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16.1.
16.2.
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List of Tables
TABLE 1. PIN DESCRIPTIONS .......................................................................................................................................................7
TABLE 2. CONFIGURATION UPON POWER ON STRAPPING.........................................................................................................14
TABLE 3. MAC INTERFACE MII/RGMII MODE PIN SHARING MAPPINGS .................................................................................15
TABLE 4. GMII/RGMII INTERFACE PIN DESCRIPTIONS............................................................................................................15
TABLE 5. MII MAC MODE INTERFACE PIN DESCRIPTIONS.......................................................................................................16
TABLE 6. MII PHY MODE INTERFACE PIN DESCRIPTIONS ........................................................................................................16
TABLE 7. SHARED I/O PIN MAPPING .........................................................................................................................................17
TABLE 8.
MEMORY MAP ......................................................................................................................................................18
TABLE 9. MEMORY CONTROL REGISTER (MCR) (0XB800_1000) ............................................................................................23
TABLE 10. DRAM CONFIGURATION REGISTER (DCR) (0XB800_1004)...................................................................................24
TABLE 11. DRAM TIMING REGISTER (DTR) (0XB800_1008) ...................................................................................................25
TABLE 12. DDR DRAM CALIBRATION REGISTER (DDCR) (0XB800_1050).............................................................................26
TABLE 13. SPI FLASH CONFIGURATION REGISTER (SFCR) (0XB800_1200)..............................................................................27
TABLE 14. SPI FLASH CONFIGURATION REGISTER 2 (SPCR2) (0XB800_1204).........................................................................27
TABLE 15. SPI FLASH CONTROL & STATUS REGISTER (SFCSR) (0XB800_1208) .....................................................................28
TABLE 16. SPI FLASH DATA REGISTER (SFDR) (0XB800_120C)..............................................................................................29
TABLE 17. SPI FLASH DATA REGISTER 2 (SFDR2) (0XB800_1210)..........................................................................................29
TABLE 18.
INTERRUPT CONTROL REGISTER ADDRESS MAPPING (0XB800_3000) .................................................................30
TABLE 19.
GLOBAL INTERRUPT MASK REGISTER (GIMR) (0XB800_3000)...........................................................................30
GLOBAL INTERRUPT STATUS REGISTER (GISR) (0XB800_3004) .........................................................................31
TABLE 20.
INTERRUPT ROUTING REGISTER 0 (IRR0) (0XB800_3008)...................................................................................32
TABLE 21.
TABLE 22.
INTERRUPT ROUTING REGISTER 1 (IRR1) (0XB800_300C) ..................................................................................32
TABLE 23.
INTERRUPT ROUTING REGISTER 2 (IRR2) (0XB800_3010)...................................................................................32
INTERRUPT ROUTING REGISTER 3 (IRR3) (0XB800_3014)...................................................................................33
TABLE 24.
TIMER CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_3100) ..............................................................34
TABLE 25.
TABLE 26.
TIMER/COUNTER 0 DATA REGISTER (0XB800_3100) ...........................................................................................34
TABLE 27.
TIMER/COUNTER 1 DATA REGISTER (0XB800_3104) ...........................................................................................34
TABLE 28.
TIMER/COUNTER 0 COUNTER REGISTER (0XB800_3108).....................................................................................34
TIMER/COUNTER 1 COUNTER REGISTER (0XB800_310C) ....................................................................................35
TABLE 29.
TABLE 30.
TIMER/COUNTER CONTROL REGISTER (0XB800_3110)........................................................................................35
TABLE 31.
TIMER/COUNTER INTERRUPT REGISTER (0XB800_3114)......................................................................................35
TABLE 32.
CLOCK DIVISION BASE REGISTER (0XB800_3118)...............................................................................................36
TABLE 33. WATCHDOG CONTROL REGISTER (0XB800_311C)...............................................................................................36
TABLE 34. GPIO REGISTER SET (0XB800_3500) .......................................................................................................................37
TABLE 35. GPIO PORT A, B, C, D CONTROL REGISTER (PABCD_CNR) (0XB800_3500) ........................................................38
TABLE 36. GPIO PORT A, B, C, D DIRECTION REGISTER (PABCD_DIR) (0XB800_3508)........................................................38
TABLE 37. PORT A, B, C, D DATA REGISTER (PABCD_DAT) (0XB800_350C)........................................................................38
TABLE 38. PORT A, B, C, D INTERRUPT STATUS REGISTER (PABCD_ISR) (0XB800_3510).....................................................39
TABLE 39. PORT A, B INTERRUPT MASK REGISTER (PAB_IMR) (0XB800_3514).....................................................................39
TABLE 40. PORT C, D INTERRUPT MASK REGISTER (PCD_IMR) (0XB800_3518).....................................................................40
TABLE 41. GPIO PORT E, F, G, H CONTROL REGISTER (PEFGH_CNR) (0XB800_351C).........................................................40
TABLE 42. GPIO PORT E, F, G, H DIRECTION REGISTER (PEFGH_DIR) (0XB800_3524).........................................................41
TABLE 43. PORT E, F, G, H DATA REGISTER (PEFGH_DAT) (0XB800_3528)..........................................................................41
TABLE 44. PORT E, F, G, H INTERRUPT STATUS REGISTER (PEFGH_ISR) (0XB800_352C)......................................................42
TABLE 45. PORT E, F INTERRUPT MASK REGISTER (PEF_IMR) (0XB800_3530).......................................................................42
TABLE 46. PORT G, H INTERRUPT MASK REGISTER (PGH_IMR) (0XB800_3534) ....................................................................42
TABLE 47. SHARED PIN REGISTER (PIN_MUX_SEL,0XB800_0040~0XB800_0043H).............................................................44
TABLE 48. SHARED PIN REGISTER (PIN_MUX_SEL_2,0XB800_0044~0XB800_0047H).........................................................45
TABLE 49. MAC CONFIGURATION REGISTER (0XBB80-4000)...................................................................................................48
TABLE 50. PORT MIRROR CONTROL REGISTER (0XBB80-400C)............................................................................................50
TABLE 51. BROADCAST STORM CONTROL REGISTER (0XBB80-4044) ...................................................................................50
TABLE 52. CHECKSUM CONTROL REGISTER (0XBB80-4048) ..................................................................................................51
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Datasheet
TABLE 53. PORT INTERFACE TYPE CONTROL REGISTER (0XBB804100)....................................................................................53
TABLE 54. PORT CONFIGURATION REGISTER OF PORT N [N= 0~4] ........................................................................................53
TABLE 55. PORT STATUS REGISTER OF PORT N (N=0~4) ...........................................................................................................57
TABLE 56. CHIP VERSION ID REGISTER (0XBB80-4200)......................................................................................................58
TABLE 57. SWITCH SYSTEM INITIAL REGISTER (0XBB80-4204 ) ...............................................................................................58
TABLE 58. CHIP REVISION MANAGEMENT REGISTER 0 (0X BB80-4208) ...................................................................................59
TABLE 59. COUNTER VALUE AND TIMING MEANING TRANSLATION..........................................................................................61
TABLE 60. TABLE ENTRY AGING CONTROL REGISTER (0X BB80-4400)................................................................................62
TABLE 61. MODULE SWITCH CONTROL REGISTER (0X BB80-4410).......................................................................................62
OHCI OPERATIONAL REGISTER SET (0XB802_0000)...........................................................................................64
TABLE 62.
HCREVISION REGISTER (0XB802_0000)...............................................................................................................65
TABLE 63.
TABLE 64.
HCCONTROL REGISTER (0XB802_0004)...............................................................................................................65
TABLE 65.
HCCOMMANDSTATUS REGISTER (0XB802_0008) ................................................................................................67
TABLE 66.
HCINTERRUPTSTATUS REGISTER (0XB802_000C) ...............................................................................................68
HCINTERRUPTENABLE REGISTER (0XB802_0010) ...............................................................................................69
TABLE 67.
TABLE 68.
HCINTERRUPTDISABLE REGISTER (0XB802_0014) ..............................................................................................69
TABLE 69.
HCHCCA REGISTER (0XB802_0018) ...................................................................................................................70
TABLE 70.
HCPERIODCURRENTED REGISTER (0XB802_001C).............................................................................................70
HCCONTROLHEADED REGISTER (0XB802_0020)................................................................................................70
TABLE 71.
HCCONTROLCURRENTED REGISTER (0XB802_0024)..........................................................................................71
TABLE 72.
TABLE 73.
HCBULKHEADED REGISTER (0XB802_0028) ......................................................................................................71
TABLE 74.
HCBULKCURRENTED REGISTER (0XB802_002C)................................................................................................71
HCDONEHEAD REGISTER (0XB802_0030) ...........................................................................................................72
TABLE 75.
HCFMINTERVAL REGISTER (0XB802_0034).........................................................................................................72
TABLE 76.
TABLE 77.
HCFMREMAINING REGISTER (0XB802_0038) ......................................................................................................73
TABLE 78.
HCFMNUMBER REGISTER (0XB802_003C) ..........................................................................................................73
TABLE 79.
HCPERIODICSTART REGISTER (0XB802_0040).....................................................................................................73
HCLSTHRESHOLD REGISTER (0XB802_0044) ......................................................................................................74
TABLE 80.
TABLE 81.
HCRHDESCRIPTORA REGISTER (0XB802_0048) ..................................................................................................74
TABLE 82.
HCRHDESCRIPTORB REGISTER (0XB802_004C)..................................................................................................75
TABLE 83.
HCRHSTATUS REGISTER (0XB802_0050).............................................................................................................76
HCRHSTATUS REGISTER (0XB802_0054, 0058)...................................................................................................77
TABLE 84.
EHCI CAPABILITY REGISTER SET (0XB802_1000)...............................................................................................80
TABLE 85.
TABLE 86.
CAPLENGTH REGISTER (0XB802_1000)............................................................................................................80
TABLE 87.
HCIVERSION REGISTER (0XB802_1002) ...........................................................................................................80
HCSPARAMS REGISTER (0XB802_1004) ...........................................................................................................80
TABLE 88.
HCCPARAMS REGISTER (0XB802_1008)...........................................................................................................81
TABLE 89.
TABLE 90.
HCSP-PORTROUTE REGISTER (0XB802_100C)................................................................................................81
TABLE 91.
EHCI OPERATIONAL REGISTER SET (BASE: 0XB802_1010).................................................................................81
TABLE 92.
USBCMD REGISTER (0XB802_1010) ..................................................................................................................82
USBSTS REGISTER (0XB802_1014).....................................................................................................................83
TABLE 93.
TABLE 94.
USBINTR REGISTER (0XB802_1018) ..................................................................................................................85
TABLE 95.
FRINDEX REGISTER (0XB802_101C) .................................................................................................................85
TABLE 96.
CTRLDSSEGMENT REGISTER (0XB802_1020) .................................................................................................86
PERIODICLISTBASE REGISTER (0XB802_1024) ..............................................................................................86
TABLE 97.
TABLE 98.
ASYNCLISTBASE REGISTER (0XB802_1024) ...................................................................................................86
TABLE 99.
CONFIGFLAG REGISTER (0XB802_1050)..........................................................................................................86
TABLE 100. PORTSC REGISTER (0XB802_1054) ....................................................................................................................87
TABLE 101. UART CONTROL INTERFACE PINS ........................................................................................................................92
TABLE 102. UART CONTROL REGISTER ADDRESS MAPPING (BASE: 0XB800_2000)..............................................................92
TABLE 103. UART RECEIVER BUFFER REGISTER (DLAB=0) (0XB800_2100, 0XB800_2000) ...............................................93
TABLE 104. UART TRANSMITTER HOLDING REGISTER (DLAB=0) (0XB800_2100,0XB800_2000).......................................93
TABLE 105. UART DIVISOR LATCH LSB (DLAB=1) (0XB800_2100, ,0XB800_2000)...........................................................93
TABLE 106. UART DIVISOR LATCH MSB (DLAB=1) (0XB800_2104,0XB800_2004) ...........................................................93
TABLE 107. UART INTERRUPT ENABLE REGISTER (DLAB=0) (0XB800_2104,0XB800_2004)..............................................94
Confidential for ⼴
IEEE 802.11n Gigabit Ethernet AP/Router Network Processor
viii
Track ID: JATR-2265-11 Rev. 0.91
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