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dwc pcie user.pdf
SolvNet
DesignWare
Contents
Preface
Product Description
User Guide Organization
Related Documentation
Reference Documentation
Web Resources
Customer Support
1 Product Overview
1.1 General Product Description
1.1.1 Verification Environment Overview
1.1.2 coreConsultant Overview
1.2 Standards
1.3 Applications
2 Configuring the Core
2.1 Design Flow
2.2 Setting up your Environment
2.3 Creating a Workspace
2.4 Configuring the Core
2.5 Simulating the Core
2.5.1 Running the Simulation
2.5.2 Checking Simulation Status and Results
2.6 Synthesizing the Core
2.6.1 Synthesizing the Core for an ASIC
2.6.1.1 Performing ASIC Synthesis
2.6.1.2 Checking ASIC Synthesis Results
2.6.2 Synthesizing the Core for an FPGA
2.6.2.1 Performing FPGA Synthesis
2.6.2.2 Checking FPGA Synthesis Results
2.7 Formal Equivalence Checking using Formality
2.8 Inserting Design-For-Test using Design Compiler
2.9 Running ATPG using Tetramax
2.10 Running STA using PrimeTime
2.11 Creating Optional Views and Reports
2.12 Exporting a Core From coreConsultant to Your Chip Design Database
2.12.1 Generating a Sample Core Instantiation
2.12.2 Exporting and Simulating the RTL Code
2.12.3 Synthesizing to a Device Outside of coreConsultant
2.12.4 Exporting Formality, DFT and ATPG Scripts
2.13 Additional Information (UTE)
3 Integrating the Core with the PHY or Application RTL or Verification IP
3.1 Integrating the Core with the PHY
3.1.1 Overview
3.1.2 Integrating the PCIe Core and Synopsys PHYs
3.1.2.1 Integrating an Internal Synopsys UP3 Gen1 PHY
3.1.2.2 Integrating an External Synopsys UP3 Gen1 PHY
3.1.2.3 Integrating an Internal Synopsys UP5 Gen2 PHY
3.1.2.4 Integrating an External Synopsys UP5 Gen2 PHY
3.1.2.5 Integrating an External Synopsys SSP Gen1 PHY
3.1.2.6 Integrating an External Synopsys SSP Gen2 PHY
3.1.2.7 Integrating an External Synopsys M-PHY
3.1.3 Integrating the PCIe Core and Third-party PHYs
3.1.3.1 Integrating an Example PIPE PHY
3.1.3.2 Integrating an Example RMMI M-PHY
3.1.3.3 Integrating an NXP PX PHY
3.1.3.4 Integrating a Custom PIPE PHY
3.1.3.5 Integrating a Custom M-PHY
3.1.3.6 Integrating a Xilinx Virtex-5 GTP/GTX PHY
3.1.3.7 Integrating a Xilinx Virtex-6 GTX PHY
3.1.3.8 Integrating a Xilinx Virtex-7 GTX PHY
3.1.3.9 Integrating an IBM Gen3 PHY
3.1.4 Bifurcation Guidelines
3.1.4.1 Bifurcation Overview
3.1.4.2 Bifurcation Implementation Requirements
3.1.4.3 Examples of Connecting a PCS to the Core for Bifurcation
3.1.4.4 Bifurcation FAQ
3.2 Integrating with your Application RTL
3.2.1 Instantiating the Core RTL in Your Design
3.2.2 Connecting the Reset I/O Interface
3.2.3 Connecting the Clock I/O Interface
3.2.4 Connecting the RAM I/O Interface
3.2.5 Connecting the Application I/O Interfaces
3.2.6 Design Example
3.3 Integrating the Core and VIP using VTB
3.3.1 Limitations
3.3.2 Setting Up and Running the VTB
4 Programming
A: Selecting PCI Express IP for Your Design
A.1 PCI Express Overview
A.1.1 PCI Express System Example: PC Motherboard Based System
A.1.2 PCI Express System Example: Chip-to-Chip System
A.1.3 PCI Express Protocol Stack
A.1.4 PCI Express Links
A.1.5 Digital IP to PHY Interface (PIPE)
A.2 Selecting PCI Express IP for Your Application
A.2.1 Selecting the Lane Width
A.2.2 Selecting Mixed-Signal PCI Express IP (PHY)
A.2.3 Selecting Digital PCI Express IP Types
A.2.3.1 Digital IP for Basic Applications
A.2.3.2 Digital IP for Advanced Applications: Overview
A.2.3.3 Digital IP: Upstream vs. Downstream Differences
A.2.3.4 Digital IP: Configuration Registers Differences
A.2.3.5 Digital IP: Configuration Transaction Differences
A.2.3.6 Digital IP: Interrupt and Error Message Differences
A.3 Implementing PCI Express in Your Design
A.4 Summary
B: Configuration Guide
B.1 Client Interfaces Configuration Guide (without AHB/AXI Bridge)
B.2 FPGA Configuration Guide
C: Additional Information (coreConsultant)
C.1 Troubleshooting
C.1.1 Specify Configuration Activity
C.1.2 Create Gate-Level Netlist Activity
C.2 Creating a Batch Script
C.3 Help Information
C.4 Workspace Directory Structure Overview
C.5 Dumping Debug Information When Problems Occur
DesignWare Cores
PCI Express Controller
User Guide
Dual Mode Port (DM) Core
Root Complex Port (RC) Core
Endpoint Port (EP) Core
Switch Port (SW) Core
Version 4.21a
December 2013
PCI Express User Guide
Copyright Notice and Proprietary Information Notice
Copyright © 2013 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information
that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Synopsys, Inc.
700 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
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PCI Express User Guide
Contents
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.2 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chapter 2
Configuring the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2 Setting up your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.3 Creating a Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4 Configuring the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.5 Simulating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.6 Synthesizing the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.7 Formal Equivalence Checking using Formality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.8 Inserting Design-For-Test using Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.9 Running ATPG using Tetramax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.10 Running STA using PrimeTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.11 Creating Optional Views and Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.12 Exporting a Core From coreConsultant to Your Chip Design Database . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.13 Additional Information (UTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Chapter 3
Integrating the Core with the PHY or Application RTL or Verification IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.1 Integrating the Core with the PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.2 Integrating with your Application RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
3.3 Integrating the Core and VIP using VTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Chapter 4
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Appendix A
Selecting PCI Express IP for Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.1 PCI Express Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
A.2 Selecting PCI Express IP for Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
A.3 Implementing PCI Express in Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Appendix B
Configuration Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
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B.1 Client Interfaces Configuration Guide (without AHB/AXI Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
B.2 FPGA Configuration Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Appendix C
Additional Information (coreConsultant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
C.1 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
C.2 Creating a Batch Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
C.3 Help Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
C.4 Workspace Directory Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
C.5 Dumping Debug Information When Problems Occur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
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Preface
This preface contains the following sections
■
■
■
■
■
“Product Description”
“User Guide Organization”
“Related Documentation” on page 6
“Reference Documentation” on page 6
“Customer Support” on page 7
Product Description
This document describes the Synopsys DesignWare Cores for PCI Express (PCIe) which provides a solution
to implement a PCI Express Port for a Root Complex, Endpoint or Switch application. The cores are
compliant with the PCI Express 3.0 specification. For a complete overview of the core features, see the
Product Overview chapter of the Databook. The DesignWare Cores for PCI Express include the following
products:
■ PCI Express Dual Mode (DM) core
■ PCI Express Root Complex Port (RC) core
■ PCI Express Endpoint Port (EP) core
■ PCI Express Switch Port (SW) core
User Guide Organization
The chapters of this user guide are organized as follows:
■ Chapter 1, “Product Overview,” introduces the core features, supported standards, and architecture.
■ Chapter 2, “Configuring the Core,” provides an overview of the step-by-step process you use to
configure, synthesize, simulate, and export the core using the Synopsys coreConsultant tool.
■ Chapter 3, “Integrating the Core with the PHY or Application RTL or Verification IP,” describes
instantiating and integrating the core into a design.
■ Chapter 4, “Programming,” describes software programming of the core.
■ A:, “Selecting PCI Express IP for Your Design”, provides a very brief introduction to the PCI Express
protocol and explains how selecting the right digital and mixed-signal IP can accelerate the
implementation of PCI Express functionality in your designs.
■ B:, “Configuration Guide”, provides a quick reference to highlight the impact of some of the key
configuration parameters in your design.
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■ C:, “Additional Information (coreConsultant)”, provides miscellaneous information related to
coreConsultant such as writing a batch script, accessing help information, and workspace directory
contents.
Related Documentation
After installing the core, the DWC PCI Express documents can be found under:
$DESIGNWARE_HOME/iip/DWC_pcie_/latest/doc. See also the DesignWare Cores PCI Express
Documentation Overview.
Reference Documentation
This user guide assumes familiarity with the basic terminology and concepts outlined in the PCI Express
Base 3.0 Specification, revision 1.0 available from http://www.pcisig.com.
Web Resources
■ DesignWare IP product information: http://www.designware.com
■ Your custom DesignWare IP page: http://www.mydesignware.com
■ Documentation through SolvNet: http://solvnet.synopsys.com (Synopsys password required)
■
Synopsys Common Licensing (SCL): http://www.synopsys.com/keys
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Preface
Customer Support
To obtain support for your product:
■
First, prepare the following debug information, if applicable:
❑
❑
For environment setup problems or failures with configuration, simulation, or synthesis that
occur within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file
/debug.tar.gz.
For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD)
■
Identify the hierarchy path to the DesignWare instance
■
Identify the timestamp of any signals or locations in the waveforms that are not understood. Then,
contact Support Center, with a description of your question and supplying the previous information,
using one of the following methods:
❑
For fastest response, use the SolvNet website. When you fill in your information as explained later,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product 1 entry is critical for correct routing.
Go to http://solvnet.synopsys.com/EnterACall and click on the link to enter a call.
Provide the requested information, including:
■ Customer Tracking Number: Enter your project name. Use the same name for cases related
to the same project.
Product: DesignWare Cores
Sub Product 1: PCI Express
Product Version: 4.21a (for example)
Problem Type:
Issue Severity:
Problem Title: Provide a brief summary of the issue or list the error message you have
encountered
Problem Description: For simulation issues, include the timestamp of any signals or locations
in waveforms that are not understood
■
■
■
■
■
■
■
After creating the case, attach any debug files you created in the previous step.
❑ Or, send an e-mail message to support_center@synopsys.com (your email is queued and then, on
a first-come, first-served basis, manually routed to the correct support engineer):
■
■
Include the Product name, Sub Product name, and Tool Version number in your e-mail (as
identified earlier) so it can be routed correctly.
For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created in the previous step.
❑ Or, telephone your local support center:
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PCI Express User Guide
■ North America: Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through
Friday.
■ All other countries: http://www.synopsys.com/Support/GlobalSupportCenters
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