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IEEE_UPF_1801-2018_DE.pdf
IEEE Standard for Design and
Verification of Low-Power, Energy-
Aware Electronic Systems
IEEE Computer Society
Sponsored by the
Design Automation Standards Committee
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
IEEE Std 1801™-2018
(Revision of
IEEE Std 1801-2015)
IEEE Std 1801™-2018
(Revision of
IEEE Std 1801-2015)
IEEE Standard for Design and
Verification of Low-Power, Energy-
Aware Electronic Systems
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
Approved 27 September 2018
IEEE-SA Standards Board
Abstract: A method is provided for specifying power intent for an electronic design, for use in
verification of the structure and behavior of the design in the context of a given power-
management architecture, and for driving implementation of that power-management architecture.
The method supports incremental refinement of power intent specifications required for IP-based
design flows.
Keywords: corruption semantics, IEEE 1801™, interface specification, IP reuse, isolation, level-
shifting, power-aware design, power domains, power intent, power modes, power states,
progressive design refinement, retention, retention strategies
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2018 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 29 March 2019. Printed in the United States of America.
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by The Institute of Electrical and Electronics
Engineers, Incorporated.
PDF:
Print:
ISBN 978-1-5044-5258-8
ISBN 978-1-5044-5259-5
STD23378
STDPD23378
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Participants
At the time this IEEE standard was completed, the P1801 Working Group had the following membership:
Paul Bailey
Madhur Bhargava
Conor Byrne
Louis Cardillo
Shir-Shen Chang
Gabriel Chidolue
William Crocco
Daniel Cross
John Decker
Shaun Durnan
John Biggs, Chair
David Cheng, Vice Chair
Jon Worthington, Secretary
Jean Fei
Jerry Frenkil
Phil Giangarra
Alan Gibbons
Amol Herlekar
Joe Hupcey
Fred Jen
Rick Koster
Don Mills
Lawrence Neukom
Joshua Ong
Desinghu Pundi Srinivasan
Shreedhar Ramachandra
Judith Richardson
Frederic Saint-Preux
Guido Schlothane
Mohammed Shareef
Rajpal Singh
Ramya Sri Murugesan
Amit Srivastava
Tejan Thakore
The following members of the entity balloting committee voted on this standard. Balloters may have voted
for approval, disapproval, or abstention.
Accellera Systems Initiative, Inc.
Advanced Micro Devices (AMD)
ARM, Ltd.
Cadence Design Systems, Inc.
Intel Corporation
Japan Electronics and Information Technology
Industries Association (JEITA)
NVIDIA Corporation
Qualcomm Incorporated
Siemens Corporation
STMicroelectronics
Synopsys, Inc.
Verific Design Automation, Inc.
When the IEEE-SA Standards Board approved this standard on 27 September 2018, it had the following
membership:
Jean-Philippe Faure, Chair
Vacant Position, Vice Chair
John D. Kulick, Past Chair
Konstantinos Karachalios, Secretary
Michael Janezic
Thomas Koshy
Joseph L. Koepfinger*
Kevin Lu
Daleep Mohla
Damir Novosel
Ronald C. Petersen
Annette D. Reilly
Robby Robson
Dorothy Stanley
Adrian Stephens
Mehmet Ulema
Phil Wennblom
Howard Wolfman
Yu Yuan
Chuck Adams
Masayuki Ariyoshi
Ted Burse
Stephen Dukes
Doug Edwards
J. Travis Griffith
Gary Hoffman
*Member Emeritus
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
IEEE Std 1801-2018
Introduction
This introduction is not part of IEEE Std 1801-2018™, IEEE Standard for Design and Verification of Low-Power,
Energy-Aware Electronic Systems.
The purpose of this standard is to provide portable, low-power design specifications that can be used with a
variety of commercial products throughout an electronic system design, analysis, verification, and
implementation flow.
When the electronic design automation (EDA) industry began creating standards for use in specifying,
simulating, and implementing functional specifications of digital electronic circuits in the 1980s, the
primary design constraint was the transistor area necessary to implement the required functionality in the
prevailing process technology at that time. Power considerations were simple and easily assumed for the
design as power consumption was not a major consideration and most chips operated on a single voltage
for all functionality. Therefore, hardware description languages (HDLs) such as VHDL (IEC 61691-1-1/
IEEE Std 1076™1) and SystemVerilog (IEEE Std 1800™2) provided a rich set of capabilities necessary for
capturing the functional specification of electronic systems, but no capabilities for capturing the power
architecture (how each element of the system is to be powered).
As the process technology for manufacturing electronic circuits continued to advance, power (as a design
constraint) continually increased in importance. Even above the 90 nm process node size, dynamic power
consumption became an important design constraint as the functional size of designs increased power
consumption at the same time battery-operated mobile systems, such as cell phones and laptop computers,
became a significant driver of the electronics industry. Techniques for reducing dynamic power
consumption—the amount of power consumed to transition a node from a 0 to 1 state or vice versa—
became commonplace. Although these techniques affected the design methodology, the changes were
relatively easy to accommodate within the existing HDL-based design flow, as these techniques were
primarily focused on managing the clocking for the design (more clock domains operating at different
frequencies and gating of clocks when logic in a clock domain is not needed for the active operational
mode). Multi-voltage power-management methods were also developed. These methods did not directly
impact the functionality of the design, requiring only level-shifters between different voltage domains.
Multi-voltage power domains could be verified in existing design flows with additional, straightforward
extensions to the methodology.
With process technologies below 90 nm, static power consumption has become a prominent and, in many
cases, dominant design constraint. Due to the physics of the smaller process nodes, power is leaked from
transistors even when the circuitry is quiescent (no toggling of nodes from 0 to 1 or vice versa). New
design techniques have been developed to manage static power consumption. Power gating or power shut-
off turns off power for a set of logic elements. Back-bias techniques are used to raise the voltage threshold
at which a transistor can change its state. While back bias slows the performance of the transistor, it greatly
reduces leakage. These techniques are often combined with multi-voltages and require additional
functionality: power-management controllers, isolation cells that logically and/or electrically isolate a
shutdown power domain from “powered-up” domains, level-shifters that translate signal voltages from one
domain to another, and retention registers to facilitate fast transition from a power-off state to a power-on
state for a domain.
The Unified Power Format (UPF) was developed to enable modeling of these new power-management
techniques and to facilitate automation of design, verification, and implementation tools that must account
for power-management aspects of a design. The initial version of UPF, developed by the Accellera Systems
Initiative, focused primarily on modeling power distribution and its effects on the behavior of a system. In
1 The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers,
Incorporated.
2 IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).
Copyright © 2018 IEEE. All rights reserved.
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