logo资料库

On-chip Network.pdf

发布时间：2022-06-14 发布人：admin 分类：说明书 资料大小：2.83M 资料格式：pdf 举报 版权申诉
第1页 / 共141页
第2页 / 共141页
第3页 / 共141页
第4页 / 共141页
第5页 / 共141页
第6页 / 共141页
第7页 / 共141页
第8页 / 共141页
资料共141页，剩余部分请下载后查看
    Acknowledgments
    Introduction
    The Advent of the Multi-core Era
    Communication Demands of Multi-Core Architectures
    On-chip vs. Off-Chip Networks
    Network Basics: A Quick Primer
    Evolution to On-Chip Networks
    On-Chip Network Building Blocks
    Performance and Cost
    Commercial On-Chip Network Chips
    This Book
    Interface with System Architecture
    Shared Memory Networks in Chip Multiprocessors
    Impact of Coherence Protocol on Network Performance
    Coherence Protocol Requirements for the On-Chip Network
    Protocol-Level Network Deadlock
    Impact of Cache Hierarchy Implementation on Network Performance
    Home Node and Memory Controller Design Issues
    Miss and Transaction Status Holding Registers
    Synthesized NoCs in MPSoCs
    The Role of Application Characterization in NoC Design
    Design Requirements for On-Chip Network
    NoC Synthesis
    NoC Network Interface Standards
    Bibliographic Notes
    Case Studies
    Brief State-of-the-Art Survey
    Topology
    Metrics for Comparing Topologies
    Direct Topologies: Rings, Meshes and Tori
    Indirect Topologies: Butterflies, Clos Networks and Fat Trees
    Irregular Topologies
    Splitting and Merging
    Topology Synthesis Algorithm Example
    Layout and Implementation
    Concentrators
    Implication of Abstract Metrics on On-Chip Implementation
    Bibliographic Notes
    Case Studies
    Brief State-of-the-Art Survey
    Routing
    Types of Routing Algorithms
    Deadlock Avoidance
    Deterministic Dimension-Ordered Routing
    Oblivious Routing
    Adaptive Routing
    Adaptive Turn Model Routing
    Implementation
    Source Routing
    Node Table-Based Routing
    Combinational Circuits
    Adaptive Routing
    Routing on Irregular Topologies
    Bibliographic Notes
    Case Studies
    Brief State-of-the-Art Survey
    Flow Control
    Messages, Packets, Flits and Phits
    Message-Based Flow Control
    Circuit Switching
    Packet-Based Flow Control
    Store and Forward
    Cut-Through
    Flit-Based Flow Control
    Wormhole
    Virtual Channels
    Deadlock-Free Flow Control
    Escape VCs
    Buffer Backpressure
    Implementation
    Buffer Sizing for Turnaround Time
    Reverse Signaling Wires
    Flow Control Implementation in MPSoCs
    Bibliographic Notes
    Case Studies
    Brief State-of-the-Art Survey
    Router Microarchitecture
    Virtual Channel Router Microarchitecture
    Pipeline
    Pipeline Implementation
    Pipeline Optimizations
    Buffer Organization
    Switch Design
    Crossbar Designs
    Crossbar Speedup
    Crossbar Slicing
    Allocators and Arbiters
    Round-Robin Arbiter
    Matrix Arbiter
    Separable Allocator
    Wavefront Allocator
    Allocator Organization
    Implementation
    Router Floorplanning
    Buffer Implementation
    Bibliographic Notes
    Case Studies
    Brief State-of-the-Art Survey
    Conclusions
    Gap Between State-of-the-Art and Ideal
    Definition of Ideal Interconnect Fabric
    Definition of State-of-the-Art
    Network Power-Delay-Throughput Gap
    Key Research Challenges
    Low-Power On-Chip Networks
    Beyond Conventional Interconnects
    Resilient On-Chip Networks
    NoC Infrastructures
    On-Chip Network Benchmarks
    On-Chip Networks Conferences
    Bibliographic Notes
    Bibliography
    Biography
    On-Chip Networks
    Synthesis Lectures on Computer Architecture Editor Mark Hill, University of Wisconsin, Madison Synthesis Lectures on Computer Architecture publishes 50 to 150 page publications on topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. On-Chip Networks Natalie Enright Jerger and Li-Shiuan Peh 2009 The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It Bruce Jacob 2009 Fault Tolerant Computer Architecture Daniel J. Sorin 2009 The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines Luiz André Barroso, Urs Hölzle 2009 Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras, Margaret Martonosi 2008 Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency Kunle Olukotun, Lance Hammond, James Laudon 2007 Transactional Memory James R. Larus, Ravi Rajwar 2006 Quantum Computing for Computer Architects Tzvetan S. Metodi, Frederic T. Chong 2006
    Copyright © 2009 by Morgan & Claypool All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations in printed reviews, without the prior permission of the publisher. On-Chip Networks Natalie Enright Jerger and Li-Shiuan Peh www.morganclaypool.com ISBN: 9781598295849 ISBN: 9781598295856 paperback ebook DOI 10.2200/S00209ED1V01Y200907CAC008 A Publication in the Morgan & Claypool Publishers series SYNTHESIS LECTURES ON COMPUTER ARCHITECTURE Lecture #8 Series Editor: Mark Hill, University of Wisconsin, Madison Series ISSN Synthesis Lectures on Computer Architecture Print 1935-3235 Electronic 1935-3243
    On-Chip Networks Natalie Enright Jerger University of Toronto Li-Shiuan Peh Princeton University SYNTHESIS LECTURES ON COMPUTER ARCHITECTURE #8 CM& Morgan & cLaypool publishers
    ABSTRACT With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. KEYWORDS interconnection networks, topology, routing, flow control, computer architecture, mul- tiprocessor system on chip
    To our families for their encouragement and patience through the writing of this book: Chris Chin-Kai, Kea-Roy, and Keari
    分享到：
    赞 收藏

    相关推荐

    资料库

    开发技术

    共收录19306份资料，累计14个分类，关注成员有19位，主要包括：Actionscript,Javascript,PHP,VB,Perl,Delphi,Python,C#,C,Java,C++,Web开发,硬件开发,其它

    热门标签

    Actionscript Javascript PHP VB Perl Delphi Python C# C Java C++ Web开发 硬件开发 其它

    最新资料