DDR3的so dimm规范书.pdf

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JEDEC Standard No. 21C Page 4.20.21-1 4.20.21 - 204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-S0-DIMM Design Specification DDR3 SDRAM 72b-SO-DIMM Design Specification Revision 1.0 August 2012 Revision 1.0 Release 22

JEDED Standard No. 21C Page 4.20.21-2 Contents 1. Product Description ........................................................................................................................... 3 2. Environmental Requirements ............................................................................................................ 4 3. Pinout and Description ...................................................................................................................... 5 4. Component Details ............................................................................................................................. 9 5. DIMM Wiring Details ........................................................................................................................... 19 5.1 Signal Groups ..................................................................................................................................... 19 5.2 General Net Structure Routing Guidelines.......................................................................................... 19 5.3 Signal referencing guideline................................................................................................................ 19 5.4 Differential Clock Net Structures......................................................................................................... 20 5.5 Test Points.......................................................................................................................................... 20 5.6 Test Point Location ............................................................................................................................. 20 5.7 Explanation of Net Structure Diagrams............................................................................................... 21 5.8 Net Structure Example........................................................................................................................ 21 6. On DIMM Thermal Sensor................................................................................................................... 22 7. Serial Presence Detect Definition ..................................................................................................... 23 8. DDR3 DIMM Label Format .................................................................................................................. 25 9. DIMM Mechanical Specifications ...................................................................................................... 27 Raw Card A .................................................................................................................................. Annex A Raw Card B .................................................................................................................................... Annex B Raw Card C ....................................................................................................................................Annex C Raw Card D ...................................................................................................................................Annex D Release 22 Revision 1.0

JEDEC Standard No. 21C Page 4.20.21-3 1 Product Description This specification defines the electrical and mechanical requirements for 204-pin, EP3(1.5 Volt) EP3L(1.35 Volt) EP3U(1.25 Volt), 72 bit-wide, Double Data Rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (DDR3 SDRAM 72b-SO-DIMMs). These 72b-SO-DIMMs are intended for use as main memory when installed in embedded systems such as telecommunications I/O cards. EP3x-6400/EP3x-8500/EP3x-10600/EP3x-12800/EP3x- 14900/EP3x-17000 refers to the JEDEC standard DIMM naming convention in which EP3x-6400/EP3x-8500/EP3x- 10600/EP3x-12800/EP3x-14900/EP3x-17000 indicates a 204-pin DIMM running at 400/533/666/800/931/1063 MHz clock speed and offering 6400/8500/10600/12800/14900/17000 MB/s bandwidth on the primary data bus. Reference design examples are included which provide an initial basis for 72b-SO-DIMM designs which may be unbuffered (72b-SO-DIMM), registered (72b-SO-RDIMM), or clocked (72b-SO-CDIMM). Modifications to these reference designs may be required to meet all system timing, signal integrity, and thermal requirements for EP3x- 6400/EP3x-8500/EP3x-10600/EP3x-12800/EP3x-14900/EP3x-17000 support. All DIMM implementations must use simulations and lab verification to ensure proper timing requirements and signal integrity in the design. Table 1 — Product Family Attributes DIMM organization x72 ECC DIMM dimensions : height (nom.) x width (nom.) x thickness (max.) / MO-number, 30.0 mm x 67.6 mm x Max3.80 mm / MO-268 Pin count SDRAMs supported Ranks supported per DIMM Capacity Serial PD Voltage options Interface 204 512 Mb, 1 Gb, 2 Gb, 4 Gb, 8 Gb 1, 2, 4 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB Consistent with JC 45 1.5/1.35/1.25 volt (VDD), 3.3 volt (VDDSPD) 1.5/1.35/1.25 volt signal switching based on reference voltage at VDD/2. See DRAM specification for more detail. Revision 1.0 Release 22

JEDED Standard No. 21C Page 4.20.21-4 2 Environmental Requirements DDR3 SDRAM 72b-SO-DIMMs are intended for use in telecommunications environments that have limited capacity for heating and air conditioning. Table 2 — Environmental Parameters Symbol TOPR HOPR TSTG HSTG PBAR Parameter Operating temperature Operating humidity (relative) Storage temperature Storage humidity (without condensation) Barometric pressure (operating & storage) Rating See Note 10 to 90 -50 to +100 5 to 95 105 to 69 Units Notes 3 Note Note Note % °C % K Pascal Note, Note Note 1 Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Note 2 Up to 9850 ft. Note 3 The designer must meet the case temperature specifications for individual module components. Release 22 Revision 1.0

3 Pinout and Description Table 3 — Pin Description JEDEC Standard No. 21C Page 4.20.21-5 Description Num- ber 2 64 8 9 9 9 1 1 xx xx 1 1 2 1 204 Pin Name Description CK0_t CK0_c CK1_t Clock Input, positive line Clock Input, negative line Clock Input, positive line CK1_c CKE[1:0] Clock Input, negative line Clock Enables RAS_n Row Address Strobe CAS_n WE_n Column Address Strobe Write Enable S_n[3:0] Chip Selects A[9:0],A11, A[15:13] Address Inputs A10/AP Address Input/Autoprecharge A12/BC_n Address Input/Burst chop BA[2:0] SDRAM Bank Addresses Num- ber 1 1 1 1 2 1 1 1 4 14 1 1 3 Serial Presence Detect (SPD) Clock Input 1 SCL SDA SPD Data Input/Output SA[1:0] SPD Address Inputs 1 2 Pin Name ODT[1:0] DQ[63:0] CB[7:0] On Die Termination Inputs Data Input/Output Data check bits Input/Output DQS_t[8:0] DQS_c[8:0] Data strobes, negative line Data strobes DM[8:0] Data Masks / Data strobes, Termination data strobes EVENT_n Reserved for optional hardware temperature sensing RESET_n Register and SDRAM control pin VDD VSS VREFDQ VREFCA VTT Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage Par_In Parity bit for the Address and Control bus 1 VDDSPD SPD Power Err_Out_n Parity error found on the Address and Control bus 1 Total Symbol Type Table 4 — Registered DIMM Input/Output Functional Description Polarity Function CK0_t CK0_c CK1_t CK1_c IN IN IN IN Positive Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM). Negative Edge Positive Edge Negative Edge Negative line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAMs on rank 0 (72b-SO-DIMM). Positive line of a secondary differential pair of system clock inputs. Terminated but not used on 72b- SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs. Negative line of a secondary differential pair of system clock inputs. Terminated but not used on 72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 of 72b-SO-DIMMs. Revision 1.0 Release 22

JEDED Standard No. 21C Page 4.20.21-6 Table 4 — Registered DIMM Input/Output Functional Description (Cont’d) Symbol Type Polarity Function CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). Connected to the registering clock driver on 72b-SO-RDIMMs, connected to DRAMs on 72b-SO- CDIMMs and 72b-SO-DIMMs. Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs. For 72b- SO-RDIMMs, other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. On-Die Termination control signals. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO- DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs. When sampled at the positive rising edge of the clock, CAS_n, RAS_n, and WE_n define the operation to be executed by the SDRAM. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO- DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs. Active High Active Low Active High Active Low Supply Reference voltage for DQ0-DQ63 and CB0-CB7. CKE[1:0] IN S_n[3:0] IN IN IN ODT[1:0] RAS_n, CAS_n, WE_n VREFDQ VREFCA Supply Reference voltage for A0-A15, BA0-BA2, RAS_n, CAS_n, WE_n, S0_n, S1_n, CKE0, CKE1, Par_In, ODT0 and ODT1. BA[2:0] IN — A[15:13, 12/BC_n,11, 10/AP,9:0] IN — Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also provide the op-code during Mode Register Set commands. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs. DQ[63:0], CB[7:0] DM[8:0] VDD, VSS VTT I/O IN Supply Supply DQS_t[17:0] I/O DQS_c[17:0] I/O Positive Edge Negative Edge — Data and Check Bit Input/Output pins Active High Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets. Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. SA[1:0] SDA SCL IN I/O IN — — — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup. Release 22 Revision 1.0

JEDEC Standard No. 21C Page 4.20.21-7 Table 4 — Registered DIMM Input/Output Functional Description (Cont’d) Symbol Type Polarity Function EVENT_n OUT (open drain) Active Low This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT_n pin on TS/SPD part. VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. RESET_n IN Par_In IN Err_Out_n OUT (open drain) The RESET_n pin is connected to the RESET_n pin on the register (72b-SO-RDIMM) and to the RESET_n pin on the SDRAMs (all modules). When low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock). Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even). Not used on 72b-SO-DIMMs or 72b-SO-CDIMMs. Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out_n bus line to VDD on the system planar to act as a pull up. Not used on 72b-SO-DIMMs or 72b-SO- CDIMMs. Table 5 — DDR3 204-pin 72b-SO-DIMM Pinout Pin # Front Side Pin # 1 VREFDQ 2 3 4 5 6 8 7 VSS DQ0 DQ1 Back Side VSS DQ4 DQ5 VSS 9 11 VSS DM0 10 12 DQS0_c DQS0_t Pin # 53 55 57 59 61 63 Front Side VSS DQ24 DQ25 DM3 VSS DQ26 Pin # 54 56 58 60 62 64 Back Side DQ28 DQ29 VSS DQS3_c DQS3_t Pin # 103 105 107 109 111 Front Side A3 A1 A0 VDD CK0_t VSS 113 CK0_c Pin # 104 106 108 110 112 114 Back Side A4 A2 BA1 VDD Par_In, NC, CK1_t Err_Out_n, NC, CK1_c Pin # 155 157 159 161 163 Front Side VSS DM5 DQ42 DQ43 VSS 165 DQ48 Pin # 156 158 160 162 164 166 VSS DQS8_c DQS8_t RESET_n VREFCA 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 VDD A10/AP DQ30 DQ31 VSS CB4 DQ2 DQ3 VSS DQ8 DQ9 VSS VSS DQ10 DQ11 VSS DQ16 DQ17 VSS 65 67 69 71 DQ27 VSS CB0 CB1 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS DQ14 DQ15 VSS DQ20 DQ21 DM2 VSS DQ22 DQ23 VSS BA0 WE_n VDD CAS_n S0_n S1_n VDD DQ32 DQ33 VSS 13 15 17 19 21 23 25 DQS1_c 27 DQS1_t 29 31 33 35 37 39 41 43 DQS2_c 45 DQS2_t VSS 47 DQ18 49 51 DQ19 Terminology: * Active low signals are indicated by the suffix “_n” * Positive line of differential pairs are indicated by the suffix “_t” * Complementary inputs of differential pairs are indicated by the suffix “_c” See Notes on following page for differences of 72b-SO-RDIMMs, 72b-SO-CDIMMs, and 72b-SO-DIMMs 73 75 77 79 81 83 85 87 89 91 93 95 A12/BC_n 97 99 101 VDD S3_n S2_n RAS_n VDD ODT0 ODT1 A13 VDD DQ36 DQ37 VSS DM4 DQ38 DQ39 VSS DQ44 DQ45 VSS 66 68 70 72 Key 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 CB5 DM8 VSS CB6 CB7 VDD A15 A14 A9 VDD A11 A7 A6 VDD VSS CB2 CB3 VDD CKE0 CKE1 BA2 VDD A8 A5 VDD DQS4_c DQS4_t VSS DQ34 DQ35 VSS DQ40 DQ41 DQ49 VSS 168 167 170 169 172 171 DQS6_c 174 173 DQS6_t 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 197 198 199 VDDSPD 200 202 201 203 204 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 DQ58 DQ59 VSS SA0 SA1 VTT DQS5_c Back Side DQS5_t VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7_c DQS7_t VSS DQ62 DQ63 VSS EVENT_n SDA SCL VTT Revision 1.0 Release 22

Table 6 — Pinout Comparison Based on Module Type 72b-SO-RDIMM Notes Signal CK0_c Connected to CK_t and CK_c CK0_t Par_In inputs on registering clock driver 72B-SO-CDIMM Notes Signal CK0_c Connected to CK_t and CK_c CK0_t CK1_c inputs on PLL ErrOut_n Connected to the registering clock driver CK1_t and CK1_c are termi- nated but not used CK1_t 72B-SO-DIMM Notes SDRAMs Signal CK0_c Connected to rank 0 CK0_t CK1_c Connected to rank 1 SDRAMs on 2 rank DIMMs, terminated but not used on 1 rank DIMMs Used for 2 rank DIMMs, not connected on 1 rank DIMMs CK1_t JEDED Standard No. 21C Page 4.20.21-8 Pin # 89 87 88 90 121 S1_n Connected to the registering clock driver S1_n Used for dual-rank 72b-SO- CDIMMs, not connected on single-rank 72b-SO-CDIMMs S1_n Connected to the registering clock driver on dual- and quad- rank DIMMs; NC on single-rank DIMMs Connected to the register on 4 rank DIMMs, not connected on 1 or 2 rank DIMMs Connected to the register on 2 and 4 rank DIMMs; NC on 1 rank DIMMs Connected to the registering clock driver 114 ODT1, NC 126 S2_n, NC 119 117 130 101 CKE1 A15 A14 A13 125 S3_n, NC Connected to the register on 4 rank DIMMs, not connected on 1 or 2 rank DIMMs NC = no internal connection ODT1, NC Used for dual-rank DIMMs, not connected on single-rank DIMMs ODT1, NC Used for dual-rank DIMMs, not connected on single-rank DIMMs NC Not used NC Not used CKE1, NC Used for 2 rank DIMMs, not connected on 1 rank DIMMs A15, NC Depending on device density, A14 may not be connected to SDRAMs. However, these sig- nals are terminated. A15 not routed on some Raw Cards A13 Used for 2 rank DIMMs, not connected on 1 rank DIMMs CKE1, NC A15, NC Depending on device density, may not be con- nected to SDRAMs. However, these signals are terminated. A15 not routed on some Raw Cards A14 A13 NC Not used NC Not used Release 22 Revision 1.0

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