MIPS®架构程序员卷IA:介绍MIPS32®
建筑
文件编号:MD00082
修订版6.01 2014年8
月20日
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和商标均为其各自所有者的财产。该文件只能被分配取决于适用的不公开或许可协议与条款 MIPS。
MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
内容
第1章:关于本手册............................................ .................................................. .................. 12
1.1:印刷惯例.............................................. .................................................. ....................... 13
1.1.1:斜体文字............................................ .................................................. ............................................ 13
1.1.2:粗体文字............................................ .................................................. ............................................ 13
1.1.3:快递文本............................................ .................................................. ....................................... 13
1.1.4:彩色文字............................................ .................................................. ....................................... 13
1.2:不可预测和UNDEFINED ............................................. .................................................. ........ 13
1.2.1:不可预测............................................. .................................................. ............................ 13
1.2.2:未定义............................................. .................................................. ..................................... 14
1.2.3:不稳定............................................. .................................................. ....................................... 14
1.3:在伪符号特殊符号........................................... .................................................. .... 15
1.4:符号为注册现场辅助........................................... .................................................. ....... 18
1.5:欲了解更多信息............................................. .................................................. .................................. 20
第2章:在MIPS®架构概述......................................... ....................................... 21
2.1:历史考察.............................................. .................................................. ................................ 21
2.2:在MIPS®架构的组件.......................................... .................................................. ........ 22
2.2.1:MIPS指令集架构(ISA)....................................... .................................................. .. 22
2.2.2:MIPS特许资源架构(PRA)....................................... ......................................... 22
2.2.3:MIPS模块和专用扩展(的ASE)..................................... ....................... 23
2.2.4:MIPS用户定义指令(UDIS)....................................... .................................................. ... 23
2.3:体系结构的演变............................................ .................................................. ........................ 23
2.3.1:MIPS我MIPS通过架构V ........................................ .................................................. .... 24
2.3.2:MIPS32架构第2版.......................................... .................................................. ........... 25
2.3.3:MIPS32架构发布2.5+ ......................................... .................................................. ..... 26
2.3.4:MIPS32版本3架构(MIPSr3™)...................................... .............................................. 26
2.3.5:MIPS32架构发布5 .......................................... .................................................. ........... 27
2.3.6:MIPS32架构版本6 .......................................... .................................................. ........... 28
2.4:符合和子集............................................. .................................................. ........................ 30
2.4.1:非特权架构的子集........................................ ............................................... 30
2.4.2:特权架构子集.......................................... .................................................. ... 32
第3章:模块和特定应用扩展.......................................... ..................... 35
3.1:可选组件的说明............................................ .................................................. ........... 35
3.2:应用特定指令............................................. .................................................. ................. 36
3.2.1:MIPS16e™特定应用扩展......................................... ............................................ 37
3.2.2:MDMX™特定应用扩展......................................... ................................................ 37
3.2.3:MIPS-3D®特定应用扩展....................................... ............................................... 37
3.2.4:SmartMIPS®特定应用扩展......................................... ......................................... 37
3.2.5:MIPS®DSP模块.......................................... .................................................. ........................... 37
3.2.6:MIPS®MT模块.......................................... .................................................. .............................. 37
3.2.7:MIPS®MCU特定应用扩展........................................ .......................................... 37
3.2.8:MIPS®虚拟化模块.......................................... .................................................. .............. 38
3.2.9:MIPS®SIMD架构模块......................................... .................................................. ....... 38
第4章:CPU编程模型............................................ .................................................. .... 39
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4.1:CPU数据格式............................................. .................................................. ..................................... 39
4.2:协处理器(CP0-CP3).......................................... .................................................. .............................. 39
4.3:CPU寄存器.............................................. .................................................. ........................................... 40
4.3.1:CPU通用寄存器......................................... .................................................. .......... 40
4.3.2:CPU特殊用途寄存器......................................... .................................................. ........... 40
4.4:字节顺序和字节序............................................ .................................................. .................... 43
4.4.1:大端顺序.......................................... .................................................. ................................. 43
4.4.2:little-endian顺序.......................................... .................................................. ............................... 43
4.4.3:MIPS位字节顺序........................................... .................................................. .......................... 43
4.5:内存对齐.............................................. .................................................. ..................................... 44
4.5.1:解决对齐约束........................................... .................................................. ...... 44
4.5.2:未对齐的加载和存储指令(在第6版中删除)................................... ................. 45
4.6:内存存取类型............................................. .................................................. ............................... 45
4.6.1:非缓存内存访问........................................... .................................................. ................. 46
4.6.2:缓存内存访问........................................... .................................................. ..................... 46
4.6.3:使用高速缓存加速内存访问.......................................... ............................................... 46
4.7:实现特定的访问类型........................................... .................................................. ........ 47
4.8:可缓存和一致性属性和接入类型......................................... .............................. 47
4.9:混合接入类型............................................. .................................................. .................................. 48
4.10:取指令.............................................. .................................................. ...................................... 48
4.10.1:指令字段............................................ .................................................. .............................. 48
4.10.2:MIPS32和MIPS64指令布置和字节序....................................... ................ 48
4.10.3:取指使用高速缓存的存取无副作用..................................... .............. 49
4.10.4:取指使用高速缓存的访问有副作用的..................................... ................... 50
4.10.5:取指使用高速缓冲存取......................................... ........................................... 50
4.10.6:取指令和异常.......................................... .................................................. ... 50
4.10.6.1:对教学的精确异常模型获取........................................ ......................... 50
4.10.6.2:取指令分支延迟槽和故宫插槽........................... 51例外
4.10.7:自修改代码.......................................... .................................................. ............................. 51
第5章:CPU指令集............................................ .................................................. ............. 52
5.1:CPU装载和存储指令........................................... .................................................. ................. 52
5.1.1:加载和存储类型......................................... .................................................. ................... 52
5.1.2:加载和存储访问类型......................................... .................................................. .............. 53
5.1.3:CPU加载和存储指令的名单....................................... .................................................. 53
5.1.3.1:PC相对荷载(版本6)...................................... .................................................. ....... 55
5.1.4:加载和存储用于原子更新....................................... ............................................. 55
5.1.5:协处理器加载和存储.......................................... .................................................. ............ 55
5.2:计算指令.............................................. .................................................. ........................ 56
5.2.1:ALU立即和三操作数指令....................................... ..................................... 57
5.2.2:ALU双操作数指令......................................... .................................................. ............. 58
5.2.3:移位指令............................................ .................................................. ................................. 58
5.2.4:宽度加倍乘法和除法指令(在版本6中移除).................................. .... 59
5.2.5:宽度相同乘法和除法指令(第6版)................................... ............................ 60
5.3:跳转和转移指令............................................ .................................................. ..................... 61
5.3.1:跳转和转移指令的类型........................................ .................................................. 61
5.3.2:科延迟槽和转移很可能会与紧凑分行和
故宫插槽................................................ .................................................. ........................................ 61
5.3.2.1:在延迟槽控制转移指令和禁止插槽..................................... ..... 62
5.3.2.2:异常和延迟和故宫插槽........................................ .................................... 62
5.3.2.3:延迟槽和故宫插槽性能注意事项....................................... ....... 62
5.3.2.4:与延迟槽的例子故宫插槽....................................... ................................ 63
5.3.2.5:科弃用可能的说明......................................... ..................................... 64
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5.3.3:跳转和转移指令.......................................... .................................................. .............. 64
5.3.3.1:第6个紧凑型分支和跳转指令....................................... ........................ 64
5.3.3.2:延迟转移指令........................................... .................................................. ...... 66
5.4:地址计算和大的恒定说明(第6版)...................................... .................. 67
5.5:其他指令.............................................. .................................................. ........................ 68
5.5.1:指令序列化(SYNC和SYNCI)....................................... ............................................. 68
5.5.2:异常说明............................................ .................................................. ........................ 69
5.5.3:条件移动指令........................................... .................................................. ............. 70
5.5.4:预取指令............................................ .................................................. .......................... 70
5.5.5:NOP指令............................................ .................................................. ................................ 71
5.6:协处理器指令.............................................. .................................................. ........................... 71
5.6.1:什么协处理器待办事项........................................... .................................................. ....................... 71
5.6.2:系统控制协处理器0(CP0)....................................... .................................................. ..... 72
5.6.3:浮点协处理器1(CP1)....................................... .................................................. ....... 72
5.6.3.1:协处理器装载和存储指令......................................... ..................................... 72
5.7:CPU指令格式............................................. .................................................. ............................ 73
5.7.1:高级指令编码(第6版)....................................... ........................................... 73
5.7.2:CPU指令字段格式.......................................... .................................................. ............. 74
第6章:FPU编程模型............................................ .................................................. .... 77
6.1:启用浮点协处理器........................................... .................................................. ..... 77
6.2:IEEE标准754 ............................................. .................................................. ..................................... 77
6.3:FPU数据类型............................................. .................................................. ......................................... 78
6.3.1:浮点格式........................................... .................................................. ........................ 78
6.3.1.1:标准化和非标准化的数字.......................................... ...................................... 81
6.3.1.2:保留使用操作数值,无穷大和NaN ....................................... ................................. 81
6.3.1.3:超越无限........................................... .................................................. .................... 81
6.3.1.4:信令非数(SNAN)....................................... .................................................. .... 81
6.3.1.5:静默非数(QNAN)....................................... .................................................. ........... 82
6.3.1.6:配对单例外.......................................... .................................................. ........... 83
6.3.1.7:配对单条件码......................................... .................................................. ... 83
6.3.2:定点格式........................................... .................................................. ............................ 83
6.4:浮点寄存器............................................. .................................................. ............................. 84
6.4.1:FPU注册模型........................................... .................................................. .......................... 84
6.4.2:二进制数据传输(32位和64位).................................. .................................................. .... 86
6.4.3:FPR中并格式化操作数布局......................................... .................................................. 87 ..
6.5:浮点控制寄存器(FcR)的......................................... .................................................. ........ 87
6.5.1:浮点执行注册(FIR,CP1控制寄存器0)................................. ......... 87
6.5.2:用户浮点寄存器模式控制(UFR,CP1控制寄存器1)
(第5版专用)............................................. .................................................. ......................................... 90
6.5.3:用户否定的FP注册模式控制(UNFR,CP1控制寄存器4)
(删除在版本6)............................................ .................................................. .............................. 91
6.5.4:浮点控制和状态寄存器(FCSR,CP1控制寄存器31)................................ 92
6.5.5:浮点条件码寄存器(FCCR,CP1控制寄存器25)(发行版6)........................... .................................................. ..............................................
.... ........... 96
6.5.6:浮点异常寄存器(FEXR,CP1控制寄存器26).................................. .......... 96
6.5.7:浮点使能寄存器(FENR,CP1控制寄存器28).................................. ............... 97
6.6:格式和浮点数据的大小......................................... .................................................. ...... 97
6.6.1:值的格式用于FP寄存器....................................... .................................................. 97
6.6.2:浮点数据的大小......................................... .................................................. .................. 98
6.7:FPU异常.............................................. .................................................. ......................................... 98
6.7.1:精确异常
模式........................................... .................................................. ..................... 98
6.7.2:异常情况............................................ .................................................. ......................... 99
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MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
6.7.2.1:无效的操作异常........................................... .................................................. ..... 100
6.7.2.2:除零异常.......................................... .................................................. ....... 100
6.7.2.3:溢异常............................................ .................................................. ............... 101
6.7.2.4:交替冲洗到零下溢处理........................................ ................................. 101
6.7.2.5:溢出异常............................................ .................................................. ................ 102
6.7.2.6:不精确异常............................................ .................................................. .................. 102
6.7.2.7:未实现操作异常........................................... ........................................ 102
第7章:FPU指令集............................................ .................................................. ............ 104
7.1:二进制兼容性.............................................. .................................................. ................................. 104
7.2:FPU指令.............................................. .................................................. ...................................... 104
7.2.1:数据传输指令........................................... .................................................. ................. 105
7.2.1.1:数据对齐的加载,存储,并且移动..................................... ................................. 105
7.2.1.2:使用的寻址在数据传输指令........................................ ............................ 105
7.2.2:算术指令............................................ .................................................. ...................... 107
7.2.2.1:FPU IEEE算术指令.......................................... ............................................... 107
7.2.2.2:FPU非IEEE近似算术指令...................................... ....................... 107
7.2.2.3:FPU乘加指令......................................... .................................................. .... 108
7.2.2.4:FPU融合乘法 - 累加指令(版本6).................................... ............... 109
7.2.2.5:浮点比较指令.......................................... ...................................... 109
7.2.3:转换指令............................................ .................................................. .................... 110
7.2.4:格式化操作数数值传送指令........................................ ........................................ 111
7.2.5:FPU条件转移指令。.................................................. .......................................... 113
7.2.6:其他指令(已删除在版本6)...................................... ............................... 114
7.3:为FPU指令的有效操作........................................... .................................................. .......... 115
7.4:FPU指令格式............................................. .................................................. ........................... 117
附录A:流水线结构............................................. .................................................. ..... 122
A.1:流水线级和执行速率......................................... .................................................. .......... 122
A.2:平行管道............................................ .................................................. ........................................ 122
A.3:超流水线............................................. .................................................. ........................................... 123
A.4:超标量流水线............................................ .................................................. ................................. 123
附录B:未对齐的存储器访问............................................ ......................................... 126
B.1:术语............................................. .................................................. ............................................. 126
B.2:硬件或是软件支持未对齐的内存访问...................................... ............ 127
B.3:检测未对齐支持........................................... .................................................. .................... 129
B.4:未对齐的语义............................................ .................................................. ............................... 129
B.4.1:未对齐的基本规则:单线程原子,但不是多线程................................ 129
B.4.2:权限和未对齐的内存访问......................................... ................................... 129
B.4.3:未对齐的存储器访问过去记忆的结束...................................... .......................... 131
B.4.4:TLB和未对齐的内存访问......................................... .............................................. 131
B.4.5:存储器类型和未对齐的存储器访问........................................ ............................... 132
B.4.6:Misaligneds,内存排序和连贯性....................................... .................................... 133
B.4.6.1:Misaligneds是单线程原子...................................... .......................................... 133
B.4.6.2:Misaligneds并不多处理器/多线程原子..................................... .................. 134
B.4.6.3:Misaligneds和多内存排序....................................... ....................... 135
B.5:伪............................................. .................................................. ............................................. 135
B.5.1:伪区分真正从实际上未对齐.......................................对齐136 ..
B.5.2:其实对齐............................................ .................................................. ............................... 136
B.5.3:字节交换............................................ .................................................. ................................. 136
B.5.4:伪表达大多数一般不对齐的语义........................................ ............. 137
MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
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B.5.5:实施例的伪代码的可能实施......................................... ............................ 138
B.5.5.1:实施例逐字节的伪代码..................................... ................................................ 138
B.5.5.2:实施例的伪代码处理拆分和非拆分单独................................... .... 139
B.6:错位和MSA向量存储器访问........................................ ......................................... 139
B.6.1:语义............................................. .................................................. ....................................... 139
B.6.2:为伪MSA存储操作与错位....................................... ................ 140
附录C:修订历史............................................. .................................................. ............ 143
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MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
数据
图2.1:MIPS架构演进............................................ .................................................. ................... 24
图3.1:MIPS ISA的,的ASE,和模块........................................ .................................................. ................. 36
图4.1:CPU寄存器的MIPS32 ........................................... .................................................. ...................... 42
图4.2:big-endian字节序.......................................... .................................................. ......................... 43
图4.3:little-endian字节序.......................................... .................................................. ....................... 43
图4.4大端数据在双字格式........................................ .................................................. ..... 44
图4.5:小端数据在双字格式........................................ .................................................. ... 44
图4.6:大端不对齐的字寻址......................................... .................................................. ... 45
图4.7:小端不对齐的字寻址......................................... .................................................. 45
图4.8:两条指令在64位宽,小端内存放置................................. ......................... 49
图4.9:两个指令在64位宽,大端内存放置................................. ............................ 49
图5.1:寄存器(R型)的CPU指令格式...................................... .................................................. ... 74
图5.2:立即(i型)的CPU指令格式(版本6).................................. ................................. 74
图5.3:立即(i型)Imm16 CPU指令格式..................................... ........................................ 74
图5.4:立即(i型)Off21 CPU指令格式(版本6)................................. ........................... 75
图5.5:立即(i型)Off26 CPU指令格式(版本6)................................. ........................... 75
图5.6:立即(i型)Off11 CPU指令格式(版本6)................................. ........................... 75
图5.7:立即(i型)Off9 CPU指令格式(版本6)................................. ............................. 75
图5.8:跳转(J-型)CPU指令格式...................................... .................................................. ........ 75
图6.1:单精度浮点格式(S)...................................... .................................................. ... 80
图6.2:双精度浮点格式(d)...................................... .................................................. 80
图6.3:配对单浮点格式(PS)...................................... .................................................. ..... 80
图6.4:字定点格式(W)....... .................................................. ..................... 83
图6.5:长字定点格式(L)........................................ .................................................. ............... 83
图6.6:FPU字加载并移动到操作....................................... .................................................. 86 ..
图6.7:FPU双字加载和移动到操作....................................... ........................................... 86
图6.8:单浮点或Word定点操作数在FPR .................................... ....................... 87
图6.9:双浮点或长字定点操作数在FPR .................................... ................ 87
图6.10:配对单浮点操作数在FPR(在版本6中移除)................................ ........ 87
图6.11:FIR寄存器格式............................................ .................................................. ............................ 88
图6.12:UFR寄存器格式(发行版6)...................................... .................................................. ....... 91
图6.13:UNFR寄存器格式(发行版6)...................................... .................................................. ..... 91
图6.14:FCSR寄存器格式............................................ .................................................. ........................ 92
图6.15:FCCR寄存器格式............................................ .................................................. ........................ 96
图6.16:FEXR寄存器格式............................................ .................................................. ......................... 96
图6.17:FENR寄存器格式............................................ .................................................. ........................ 97
图7.1:I型(即时)FPU指令格式...................................... ................................................. 119
图7.2:R型(注册)FPU指令格式...................................... .................................................. 119
图7.3:注册,立即FPU指令格式......................................... ............................................. 119
图7.4:条件码,立即FPU指令格式(在版本6中移除).................................. 119
图7.5:格式化FPU比较指令格式(在版本6中移除).................................... .......... 119
图7.6:FP注册移动,条件指令格式(已删除在版本6) 2 .................................... 119图7.7:四注册格式化算术FPU指令格式(在版本6中删除) 2 .................... 119图7.8:
图7.6:FP注册移动,条件指令格式(已删除在版本6) 2 .................................... 119图7.7:四注册格式化算术FPU指令格式(在版本6中删除) 2 .................... 119图7.8:
图7.6:FP注册移动,条件指令格式(已删除在版本6) 2 .................................... 119图7.7:四注册格式化算术FPU指令格式(在版本6中删除) 2 .................... 119图7.8:
图7.6:FP注册移动,条件指令格式(已删除在版本6) 2 .................................... 119图7.7:四注册格式化算术FPU指令格式(在版本6中删除) 2 .................... 119图7.8:
图7.6:FP注册移动,条件指令格式(已删除在版本6) 2 .................................... 119图7.7:四注册格式化算术FPU指令格式(在版本6中删除) 2 .................... 119图7.8:
寄存器索引FPU指令格式(在版本6中移除)................................... .................... 120
图7.9:注册索引提示FPU指令格式(在版本6删除)................................... ............ 120
图7.10:条件代码,注册整数FPU指令格式(6版中删除) 3 ...................... 120图A.1:一深单完成指令流水线.................................... ......................................... 122
图7.10:条件代码,注册整数FPU指令格式(6版中删除) 3 ...................... 120图A.1:一深单完成指令流水线.................................... ......................................... 122
图7.10:条件代码,注册整数FPU指令格式(6版中删除) 3 ...................... 120图A.1:一深单完成指令流水线.................................... ......................................... 122
MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
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