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AR8035 Data Sheet.pdf
1 Introduction
1.1 Features
1.2 Functional block diagram
2 Pin Descriptions
2.1 Pinout diagram
2.2 Pin descriptions
2.3 Power-on strapping
2.3.1 Mode definition
3 Function Description
3.1 Transmit functions
3.2 Receive functions
3.2.1 Decoder modes
3.2.2 Analog-to-Digital converter
3.2.3 Echo canceller
3.2.4 NEXT canceller
3.2.5 Baseline wander canceller
3.2.6 Digital adaptive equalizer
3.2.7 Auto-negotiation
3.2.8 Smartspeed
3.2.9 Automatic MDI/MDIX crossover
3.2.10 Polarity correction
3.3 Loopback modes
3.3.1 Digital loopback
3.3.2 External cable loopback
3.3.3 Remote PHY loopback
3.4 Cable diagnostic test
3.5 LED interface
3.6 Power supplies
3.7 Management interface
3.8 Green ETHOS feature
3.8.1 Low power modes
3.8.2 Short cable power mode
3.8.3 Hibernation mode
3.9 IEEE 802.3az
3.10 SmartEEE
3.11 Wake-on-LAN
4 Electrical Characteristics
4.1 Absolute maximum ratings
4.2 Recommended operating conditions
4.3 RGMII characteristics
4.4 MDIO timing
4.5 MDIO/MDC DC characteristic
4.6 Clock characteristics
4.7 Power pin current consumption
4.8 Typical power consumption parameters
4.9 Power-on sequence, reset and clock
4.9.1 Power-on sequence
4.9.2 Reset and clock timing
4.10 Digital pin design guide
5 Registers
5.1 Register bit type
5.2 MII registers
5.2.1 Control register
5.2.2 Status register
5.2.3 PHY identifier 1 register
5.2.4 PHY identifier 2 register
5.2.5 Auto-negotiation advertisement register
5.2.6 Auto-negotiation link partner ability register
5.2.7 Auto-negotiation expansion register
5.2.8 Auto-negotiation next page transmit register
5.2.9 Auto-negotiation link partner next page register
5.2.10 1000BASE-T control register
5.2.11 1000BASE-T status register
5.2.12 MMD access control register
5.2.13 MMD access data register
5.2.14 Extended status register
5.2.15 PHY specific function control register
5.2.16 PHY specific status register
5.2.17 Interrupt enable register
5.2.18 Interrupt status register
5.2.19 Smart speed register
5.2.20 Cable diagnostic test control register
5.2.21 LED control register
5.2.22 Manual LED override register
5.2.23 Cable diagnostic test status register
5.2.24 Debug port — address offset register
5.2.25 Debug port — dataport register
5.3 Debug registers
5.3.1 Analog test control register
5.3.2 SerDes test and system mode control register
5.3.3 Hibernate control register
5.3.4 100BASE-TX test mode select register
5.3.5 External loopback selection register
5.3.6 10BASE-Tetest mode select register
5.3.7 PHY control debug register 0
5.3.8 Power saving control register
5.3.9 Green feature configure 2 register
5.4 MDIO interface registers
5.4.1 MMD3 — PCS control register
5.4.2 MMD3 — PCS status register
5.4.3 MMD3 — EEE capability register
5.4.4 MMD3 — EEE wake error counter register
5.4.5 MMD3 — Cld control 3 register
5.4.6 MMD3 — AZ control 2 register
5.4.7 MMD3 — PTP1588 control register
5.4.8 MMD3 — Internal MAC address 1 register
5.4.9 MMD3 — Internal MAC address 2 register
5.4.10 MMD3 — Internal MAC address 3 register
5.4.11 MMD3 — RemotePHY loopback register
5.4.12 MMD3 — SmartEEE control 1 register
5.4.13 MMD3 — SmartEEE control 2 register
5.4.14 MMD3 — SmartEEE control 3 register
5.4.15 MMD7 — Auto-negotiation control register
5.4.16 MMD7 — EEE advertisement register
5.4.17 MMD7 — EEE LP advertisement register
5.4.18 MMD7 — EEE ability auto-negotiation result register
5.4.19 MMD7 — CLK_25M clock select register
6 Package Dimensions
7 Ordering Information
8 Top-side Marking
NOTICE
Effective October 1, 2012, QUALCOMM Incorporated completed a corporate reorganization in
which the assets of certain of its businesses and groups, as well as the stock of certain of its
direct and indirect subsidiaries, were contributed to Qualcomm Technologies, Inc. (QTI), a wholly-
owned subsidiary of QUALCOMM Incorporated that was created for purposes of the
reorganization.
Qualcomm Technology Licensing (QTL), the Company’s patent licensing business, continues
to be operated by QUALCOMM Incorporated, which continues to own the vast majority of the
Company’s patent portfolio. Substantially all of the Company’s products and services businesses,
including QCT, as well as substantially all of the Company’s engineering, research and
development functions, are now operated by QTI and its direct and indirect subsidiaries1. Neither
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rights under or to any patents owned by QUALCOMM Incorporated.
No use of this website and/or documentation, including but not limited to the downloading of
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Any copyright notice referencing QUALCOMM Incorporated, Qualcomm Incorporated,
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reference, and shall be read to reference, QTI.
1 The products and services businesses, and the engineering, research and development groups, which are now operated by QTI and its
subsidiaries include, but are not limited to, QCT, Qualcomm Mobile & Computing (QMC), Qualcomm Atheros (QCA), Qualcomm Internet
Services (QIS), Qualcomm Government Technologies (QGOV), Corporate Research & Development, Qualcomm Corporate Engineering
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Global Market Development (GMD), Global Business Operations (GBO), Qualcomm Ventures, Qualcomm Life (QLife), Quest, Qualcomm
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Qualcomm iSkoot, Qualcomm Poole and Xiam.
AR8035 Integrated 10/100/1000 Mbps
Ethernet Transceiver
Data Sheet
80-Y0618-3 Rev A
October 25, 2012
Confidential and Proprietary - Qualcomm Atheros, Inc.
Restricted Distribution. Not to be distributed to anyone who is not an employee of either Qualcomm or a subsidiary
of Qualcomm without the express approval of Qualcomm’s Configuration Management.
Not to be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the
express written permission of Qualcomm Atheros, Inc.
QUALCOMM is a registered trademark of QUALCOMM Incorporated. ATHEROS is a registered trademark of
Qualcomm Atheros, Inc. All other registered and unregistered trademarks are the property of Qualcomm
Incorporated, Qualcomm Atheros, Inc. or their respective owners and used with permission. Registered marks owned
by Qualcomm Incorporated and Qualcomm Atheros, Inc. are registered in the United States of America and may be
registered in other countries.
This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion
contrary to U.S. and international law is strictly prohibited.
Qualcomm Atheros, Inc.
1700 Technology Drive
San Jose, CA 95110-1383
U.S.A.
Copyright © 2011-2012 Qualcomm Atheros, Inc.
All rights reserved.
Revision history
Revision
1.0
2.0
Date
April 2011
November 2011
Description
Initial release
Electrical Characteristics
3.2 Recommended Operation Conditions: delete DVDDL/AVDDL,
ΨJA; add VDDH_REG, ΨJT, AVDDL/DVDDL (industrial and
commercial); add thermal conditions
3.6 change title from MDIO DC Characteristics to MDIO/MDC DC...;
change VIH min value and VIL max value
3.7 table 3-14: change Jitterpk-pk max value to 100
3.11 Digital pin design guide (new)
Registers
4.2.3 Status Register – Copper page, change bit[8] reset value to
always 1
4.3.4 Hib control and auto-neg test register: change bit[12], [6:5] to
reserved
4.3.5 External loopback selection, change bit[0] to R/W
4.3.7 Power saving control (new)
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
2
Confidential and Proprietary - Qualcomm Atheros, Inc.
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Data Sheet
Revision
Date
A
October 2012
Description
System change from SharePoint to Agile. Based on SharePoint
document system MKG-15827.
Introduction
Update Features
Update figure functional block diagram
Pin Description
Update Table Mode definition
Update Table Signal to pin descriptions
Function Descriptioin
Update Auto-negotiation
Update Function Wake on LAN
Electrical Characteristics
Absolute maximum ratings: add symbol Vmin
Update RGMII characteristics:
Table RGMII DC characteristics — 2.5/3/3V I/O supply: add GND -
0.3 to Min of symbol VIL
Table RGMII DC characteristics — 1.8V I/O supply: add 2.1 to Max
for symbol VIH, add GND - 0.3 to Min for symbol VIL, and add 1.9
to Max for symbol VOH
Table RGMII DC characteristics — 1.5V I/O supply: add 1.8 to Max
for symbol VIH, add GND - 0.3 to Min for symbol VIL, and add 1.57
to Max for symbol VOH
Update RGMII characteristics and AC timing diagrams
MDIO timing: change Min from 10 to 0, add Typ 4, and remove Max of
symbol tmdelay in Table MDIO AC characteristic
Clock characteristics: remove symbol Fs and Fo in table
Recommended crystal parameters
Power pin current consumption: update the voltage range from “3.3V
±10%” to “3.3V ±5%” for symbol AVDD33 in table Power pin
consumption
Update Registers
Add a note to table Register summary
Control register
Status register
Auto-negotiation advertisement register
1000BASE-T status register
Extended status register
Function control register
Smart speed register: add bit[8]: GIGA_DIS_QUAL
Remove registers Auto-negotiation status, Auto-negotiation XNP
transmit, Auto-negotiation XNP transmit1, Auto-negotiation XNP
transmit2, Auto-negotiation LP XNP ability, Auto-negotiation LP XNP
ability1, Auto-negotiation LP XNP ability2
Add registers PHY control debug register 0, Green feature configure
2, AZ control2, Cld control3,
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
3
Confidential and Proprietary - Qualcomm Atheros, Inc.
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-on strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 Mode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1
2.2
2.3
3.1
3.2
3 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Transmit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Receive functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Decoder modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Analog-to-Digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Echo canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 NEXT canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 Baseline wander canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.6 Digital adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.7 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.8 Smartspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.9 Automatic MDI/MDIX crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.10 Polarity correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Loopback modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.1 Digital loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.2 External cable loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.3 Remote PHY loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cable diagnostic test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
LED interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5
3.6
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7 Management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.8 Green ETHOS feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8.2 Short cable power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
4
Confidential and Proprietary - Qualcomm Atheros, Inc.
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Data Sheet
Contents
3.8.3 Hibernation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9
IEEE 802.3az . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 SmartEEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 Wake-on-LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3
RGMII characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4 MDIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5 MDIO/MDC DC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6
Power pin current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.7
Typical power consumption parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.8
4.9
Power-on sequence, reset and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.9.1 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.9.2 Reset and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.10 Digital pin design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1
Register bit type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 MII registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.1 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2.2 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.2.3 PHY identifier 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.4 PHY identifier 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.5 Auto-negotiation advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2.6 Auto-negotiation link partner ability register . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.7 Auto-negotiation expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.8 Auto-negotiation next page transmit register . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.9 Auto-negotiation link partner next page register . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.10 1000BASE-T control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.11 1000BASE-T status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2.12 MMD access control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2.13 MMD access data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2.14 Extended status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2.15 PHY specific function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2.16 PHY specific status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.17 Interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.18 Interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2.19 Smart speed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.20 Cable diagnostic test control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2.21 LED control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.22 Manual LED override register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
5
Confidential and Proprietary - Qualcomm Atheros, Inc.
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Data Sheet
Contents
5.2.23 Cable diagnostic test status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.24 Debug port — address offset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2.25 Debug port — dataport register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3 Debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.1 Analog test control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.2 SerDes test and system mode control register . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.3 Hibernate control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.4 100BASE-TX test mode select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.3.5 External loopback selection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.6 10BASE-Tetest mode select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.7 PHY control debug register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.8 Power saving control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.9 Green feature configure 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4 MDIO interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.4.1 MMD3 — PCS control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.4.2 MMD3 — PCS status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4.3 MMD3 — EEE capability register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4.4 MMD3 — EEE wake error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.4.5 MMD3 — Cld control 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.4.6 MMD3 — AZ control 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.4.7 MMD3 — PTP1588 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.4.8 MMD3 — Internal MAC address 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.4.9 MMD3 — Internal MAC address 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.10 MMD3 — Internal MAC address 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.11 MMD3 — RemotePHY loopback register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.12 MMD3 — SmartEEE control 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.4.13 MMD3 — SmartEEE control 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.4.14 MMD3 — SmartEEE control 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.4.15 MMD7 — Auto-negotiation control register . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.4.16 MMD7 — EEE advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.4.17 MMD7 — EEE LP advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4.18 MMD7 — EEE ability auto-negotiation result register . . . . . . . . . . . . . . . . . . 84
5.4.19 MMD7 — CLK_25M clock select register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8 Top-side Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
6
Confidential and Proprietary - Qualcomm Atheros, Inc.
AR8035 Integrated 10/100/1000 Mbps Ethernet Transceiver Data Sheet
Contents
Tables
Table 2-1 Signal to pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2-2 Power-on strapping pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-3 Mode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-1 AR8031, AR8033, and AR8035 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3-2 Transmit function encoder modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3-3 Receive function decoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3-4 Supported MDI pair combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3-5 Default LED status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3-6 Management interface frame fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 3-7 Management interface field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4-2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4-3 RGMII DC characteristics — 2.5/3.3V I/O supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4-4 RGMII DC characteristics — 1.8V I/O supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4-5 RGMII DC characteristics — 1.5 I/O supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4-6 RGMII AC characteristics — no internal delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4-7 RGMII AC characteristics — with internal delay added (default) . . . . . . . . . . . . . . . 37
Table 4-8 MDIO AC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4-9 MDIO/MDC DC characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4-10 Recommended crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-11 External clock input characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-12 CLK_25M output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 4-13 Power pin consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 4-14 Total system power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 4-15 Digital pin designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5-1 Register bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5-2 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5-3 Debug register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 5-4 MMD3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 5-5 MMD7 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 6-1 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 7-1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 8-1 Top-side markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
80-Y0618-3 Rev A
MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION
7
Confidential and Proprietary - Qualcomm Atheros, Inc.
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