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verilog 编写数码管循环显示器.docx
、实验内容与实验步骤
实验内容：通过编程在数码管上循环显示”HEUAC407”
实验步骤：1.寻找资料，根据实验目标修改程序。
2. 用实验室电脑软件新建工程，输入程序。
3. 根据提示错误调试程序。
4. 分配引脚 。
5. 观察开发板数码管状态，如未达到预计结果，再进
行修改
程序： module hello(HEX7,HEX6,HEX5,HEX4,
HEX3,HEX2,HEX1,HEX0,
CLOCK_50,KEY);
input CLOCK_50;
input [0:0]KEY;
output [7:0]HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,
HEX1,HEX0;
wire clk_1hz;
reg [3:0]cnt;
div u0(.o_clk(clk_1hz),
.rst_n(KEY),
.i_clk(CLOCK_50)
);
always @(posedge clk_1hz or negedge KEY)
begin
if(!KEY)
cnt<=4'b0;
else
begin
if(cnt==4'b0111)
cnt<=4'b0;
cnt<=cnt+1'b1;
else
end
end
seg7_h0 h0(.oseg(HEX7),
.idig(cnt)
);
seg7_h1 h1(.oseg(HEX6),
.idig(cnt)
);
seg7_h2 h2(.oseg(HEX5),
.idig(cnt)
);
seg7_h3 h3(.oseg(HEX4),
.idig(cnt)
);
seg7_h4 h4(.oseg(HEX3),
.idig(cnt)
);
seg7_h5 h5(.oseg(HEX2),
.idig(cnt)
);
seg7_h6 h6(.oseg(HEX1),
.idig(cnt)
);
seg7_h7 h7(.oseg(HEX0),
.idig(cnt)
);
endmodule
//divider
module div(
output reg o_clk,
rst_n,
input
input
i_clk
);
parameter N=50_000_000;
parameter M=24_999_999;
reg [25:0]cnt;
always @(posedge i_clk or negedge rst_n)
begin
if(!rst_n)
cnt<=26'b0;
else
begin
if(cnt==N-1)
else
cnt<=26'b0;
cnt<=cnt+26'b1;
end
end
always @(posedge i_clk or negedge rst_n)
begin
if(!rst_n)
o_clk<=0;
o_clk<=1;
o_clk<=0;
else
begin
if(cnt<=M)
else
end
end
endmodule
//seg7_lut
module seg7_h0
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h0: oseg = 7'b0001001; //H
4'h1: oseg = 7'b0000110; //E
4'h2: oseg = 7'b1000001; //U
4'h3: oseg = 7'b0001000; //A
4'h4: oseg = 7'b1000110; //C
4'h5: oseg = 7'b0011001; //4
4'h6: oseg = 7'b1000000; //0
4'h7: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
//seg7_lut
module seg7_h1
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h7: oseg = 7'b0001001; //H
4'h0: oseg = 7'b0000110; //E
4'h1: oseg = 7'b1000001; //U
4'h2: oseg = 7'b0001000; //A
4'h3: oseg = 7'b1000110; //C
4'h4: oseg = 7'b0011001; //4
4'h5: oseg = 7'b1000000; //0
4'h6: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h2
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h6: oseg = 7'b0001001; //H
4'h7: oseg = 7'b0000110; //E
4'h0: oseg = 7'b1000001; //U
4'h1: oseg = 7'b0001000; //A
4'h2: oseg = 7'b1000110; //C
4'h3: oseg = 7'b0011001; //4
4'h4: oseg = 7'b1000000; //0
4'h5: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h3
(
output reg [7:0] oseg,
[3:0] idig
input
);
always @ (idig)
begin
case (idig)
4'h5: oseg = 7'b0001001; //H
4'h6: oseg = 7'b0000110; //E
4'h7: oseg = 7'b1000001; //U
4'h0: oseg = 7'b0001000; //A
4'h1: oseg = 7'b1000110; //C
4'h2: oseg = 7'b0011001; //4
4'h3: oseg = 7'b1000000; //0
4'h4: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h4
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h4: oseg = 7'b0001001; //H
4'h5: oseg = 7'b0000110; //E
4'h6: oseg = 7'b1000001; //U
4'h7: oseg = 7'b0001000; //A
4'h0: oseg = 7'b1000110; //C
4'h1: oseg = 7'b0011001; //4
4'h2: oseg = 7'b1000000; //0
4'h3: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h5
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h3: oseg = 7'b0001001; //H
4'h4: oseg = 7'b0000110; //E
4'h5: oseg = 7'b1000001; //U
4'h6: oseg = 7'b0001000; //A
4'h7: oseg = 7'b1000110; //C
4'h0: oseg = 7'b0011001; //4
4'h1: oseg = 7'b1000000; //0
4'h2: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h6
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h2: oseg = 7'b0001001; //H
4'h3: oseg = 7'b0000110; //E
4'h4: oseg = 7'b1000001; //U
4'h5: oseg = 7'b0001000; //A
4'h6: oseg = 7'b1000110; //C
4'h7: oseg = 7'b0011001; //4
4'h0: oseg = 7'b1000000; //0
4'h1: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
module seg7_h7
(
output reg [7:0] oseg,
input
[3:0] idig
);
always @ (idig)
begin
case (idig)
4'h1: oseg = 7'b0001001; //H
4'h2: oseg = 7'b0000110; //E
4'h3: oseg = 7'b1000001; //U
4'h4: oseg = 7'b0001000; //A
4'h5: oseg = 7'b1000110; //C
4'h6: oseg = 7'b0011001; //4
4'h7: oseg = 7'b1000000; //0
4'h0: oseg = 7'b1011000; //7
default: oseg =7'b1111111;
endcase
end
endmodule
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