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DWC_ether_qos_databook.pdf

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    SolvNet
    DesignWare
    Documentation Overview
    Installation Guide
    Release Notes
    Databook
    User Guide
    Contents
    Revision History
    Preface
    1 Product Overview
    1.1 General Product Description
    1.1.1 System-Level Block Diagram
    1.1.2 Interfaces
    1.2 DWC_ether_qos Features
    1.2.1 Standard Compliance
    1.2.2 MAC Features
    1.2.2.1 MAC Tx and Rx Features
    1.2.2.2 MAC Tx Features
    1.2.2.3 MAC Rx Features
    1.2.3 Transaction Layer (MTL) Features
    1.2.3.1 MTL Tx and Rx Common Features
    1.2.3.2 MTL Tx Features
    1.2.3.3 MTL Rx Features
    1.2.4 DMA Block Features
    1.2.5 AHB Interface
    1.2.5.1 AHB Master Interface Features
    1.2.5.2 AHB Slave Interface Features
    1.2.6 AXI Interface
    1.2.6.1 AXI Master Interface Features
    1.2.6.2 AXI Slave Interface Features
    1.2.7 AMBA APB Slave Interface Features
    1.2.8 Audio and Video Features
    1.2.9 Data Center Bridging Features
    1.2.10 Time Sensitive Networking Features
    1.2.11 Generic Queuing Features
    1.2.12 Automotive Safety Features
    1.2.13 Monitoring, Testing, and Debugging Features
    1.3 DWC_ether_qos Configurations
    1.3.1 Configurable Features
    1.4 DWC_ether_qos Deliverables
    1.5 Related Synopsys Products
    2 Architecture
    2.1 CSR Slave Interface
    2.1.1 AHB Slave Interface
    2.1.1.1 AHB Slave Port Timing
    2.1.1.2 Interfacing AHB Slave Port with a Wider AMBA Bus
    2.1.2 AXI Slave Interface
    2.1.3 APB, APB3, and APB4 Slave Interface
    2.1.3.1 APB Port Timing
    2.1.3.2 APB3 Port Timing
    2.1.3.3 APB4 Port Timing
    2.1.4 MAC Control Interface
    2.1.4.1 MCI Port Timing
    2.2 Application Master Interface
    2.2.1 AHB Master Interface
    2.2.1.1 AHB Master Interface Features
    2.2.1.2 Burst Length Modes
    2.2.1.3 Aligning AHB Burst Transfers to An Address Value
    2.2.1.4 AHB Memory Read
    2.2.1.5 AHB Memory Write
    2.2.1.6 Early Burst Termination
    2.2.1.7 Error Response and Fatal Bus Error Interrupt
    2.2.1.8 Split or Retry Response
    2.2.1.9 Descriptor Write Back
    2.2.2 AXI Master Interface
    2.2.2.1 Burst Splitting and Burst Selection
    2.2.2.2 INCR Burst Type
    2.2.2.3 INCR_ALIGNED Burst Type
    2.2.2.4 Outstanding Transactions
    2.2.2.5 Priority of AXI Requests
    2.2.2.6 Bursts Reordering and Data Interleaving
    2.2.2.7 AXI-ID Translation
    2.2.2.8 Endianess Support
    2.2.2.9 Posted Writes
    2.2.2.10 Error Response Handling
    2.2.2.11 AXI Memory Read
    2.2.2.12 AXI Memory Write
    2.2.2.13 AXI Early Burst Termination
    2.2.3 AXI4 Master Interface
    2.2.4 AXI Low-Power Interface
    2.2.4.1 AXI System Initiated Low-Power Entry
    2.2.4.2 Automatic AXI Low-Power Entry
    2.2.4.3 Coming Out of Low-Power Mode
    2.3 DMA Controller
    2.3.1 DMA Application Bus Burst Access
    2.3.1.1 DMA Application Data Buffer Alignment
    2.3.1.2 DMA Buffer Size Calculations
    2.3.1.3 DMA Arbiter (EQOS-DMA and EQOS-AHB Configurations)
    2.3.1.4 DMA Start/Stop Control Through Sideband Signals
    2.3.2 Transmission
    2.3.2.1 Transmit DMA Operation: Default (Non-OSP) Mode
    2.3.2.2 DMA Transmit Operation: OSP Mode
    2.3.2.3 Transmit Packet Processing
    2.3.2.4 Transmit Polling Suspended
    2.3.2.5 DMA Transmit Channel Arbitration
    2.3.3 DMA Receive Operation
    2.3.3.1 Receive Descriptor Acquisition
    2.3.3.2 Receive Packet Processing
    2.3.4 Error Response to DMA
    2.3.5 DMA Native Interface
    2.3.5.1 Write Data Transfer
    2.3.5.2 Read Data Transfer
    2.3.5.3 Data Transfer With Error
    2.4 MAC Transaction Layer
    2.4.1 Transmit Path
    2.4.1.1 Transmit Control Word
    2.4.1.2 Transmit Operation
    2.4.1.3 Initialization Flow
    2.4.1.4 Data Flow Between DMA and MTL
    2.4.1.5 Transmit Status Word
    2.4.1.6 Transmit Path Timing
    2.4.2 Receive Path
    2.4.2.1 Receive Operation
    2.4.2.2 Threshold Mode
    2.4.2.3 Store-and-Forward Mode
    2.4.2.4 Multi-Packet Receive Operation
    2.4.2.5 Error Handling in Receive Operation
    2.4.2.6 Receive Status Word Format
    2.4.2.7 Receive Path Timing Diagrams
    2.4.3 Interfacing With External Two-Port RAMs
    2.4.3.1 Low-Power, Synchronous Two-Port SRAM Connection
    2.4.3.2 High-Speed, Synchronous Two-Port SRAM Connection
    2.4.4 SPRAM Interface
    2.4.4.1 Data Flow
    2.4.4.2 Application Clock Frequency Requirements for Memory Transfers
    2.4.4.3 SPRAM Timing
    2.5 MAC
    2.5.1 MAC Transmission
    2.5.1.1 Transmit Bus Interface Module
    2.5.1.2 Transmit Packet Controller Module
    2.5.1.3 Transmit Protocol Engine Module
    2.5.1.4 Transmit Module
    2.5.1.5 Transmit CRC Generator Module
    2.5.1.6 MAC Transmit Flow Control Module
    2.5.2 MAC Transmit Interface Protocol
    2.5.3 MAC Transmit Timing
    2.5.3.1 MAC Transmit Interface (MTI)
    2.5.3.2 MTI With Timestamp Feature
    2.5.3.3 Collision During Transmission
    2.5.3.4 Underflow During Transmission
    2.5.4 MAC Reception
    2.5.4.1 Receive Protocol Engine Module
    2.5.4.2 Receive CRC Module
    2.5.4.3 Receive Packet Controller Module
    2.5.4.4 Receive Flow Control Module
    2.5.4.5 Receive Bus Interface Unit Module
    2.5.4.6 Address Filtering Module
    2.5.5 MAC Receive Interface Protocol
    2.5.6 MAC Receive Timing
    2.5.6.1 MAC Receive Interface (MRI)
    2.5.6.2 Packet Reception With Timestamp Feature Enabled
    2.5.6.3 Packet Transmission and Reception
    2.6 Interrupts
    2.6.1 Interrupts from the MAC
    2.6.2 Interrupts from MTL
    2.6.3 Interrupts from DMA
    2.6.3.1 Periodic Scheduling of Transmit and Receive Interrupt
    2.6.3.2 Per Channel Transfer Complete Interrupt
    3 VLAN and Double VLAN Insertion, Deletion, Replacement and Tagging
    3.1 Double VLAN Processing
    3.1.1 Description of Double VLAN Processing
    3.1.1.1 Transmit Path
    3.1.1.2 Receive Path
    3.1.2 Double VLAN-Related Registers
    3.1.3 Enabling Double VLAN Processing
    3.2 Source Address and VLAN Insertion, Replacement, or Deletion
    3.2.1 Description of SA and VLAN Insertion, Replacement, or Deletion
    3.2.2 Enabling SA and VLAN Insertion, Replacement, or Deletion
    3.2.3 Programming Source Address Insertion or Replacement
    3.2.4 Programming VLAN Insertion, Replacement, or Deletion
    3.3 Queue/Channel Based VLAN Tag Insertion on Tx
    3.3.1 Accessing Queue/Channel Specific VLAN Tag Registers
    3.3.2 Enabling Queue/Channel Based VLAN Tag Insertion on Tx
    3.3.3 Programming Guidelines for Channel Based VLAN Tag Insertion
    4 Managing Buffers and Memories
    4.1 Introduction to Transmit and Receive FIFOs
    4.2 Description of Transmit and Receive FIFOs
    4.3 Transmit and Receive FIFO-Related Registers
    4.4 Configuring Transmit and Receive FIFO Details
    4.5 TCP/IP Header Buffer
    4.6 Accessing Memory In Slave/Debug Mode
    4.6.1 Enabling Memory Access in Slave/Debug Mode
    4.6.2 Sending or Receiving a Packet through a Slave Interface
    4.6.2.1 Transmitting Packets through a Slave Interface
    4.6.2.2 Receiving Packets through a Slave Interface
    4.6.3 Operating in Debug Mode
    4.6.3.1 Writing to FIFO Memory in Debug Mode
    4.6.3.2 Reading from FIFO Memory in Debug Mode
    5 Using PHY Interfaces
    5.1 Station Management Agent
    5.1.1 Introduction to Station Management Agent
    5.1.2 Functional Description of Station Management Agent
    5.1.2.1 GMII/MII Management Write Operation
    5.1.2.2 GMII/MII Management Read Operation
    5.1.2.3 Preamble Suppression
    5.1.2.4 Trailing Clocks and Back to Back transactions
    5.1.3 Interrupt for MDIO Transaction Completion
    5.1.4 Enabling Station Management Agent
    5.2 Physical Coding Sub-Layer (PCS)
    5.2.1 PCS Functions
    5.2.1.1 Transmit
    5.2.1.2 Receive
    5.2.1.3 Synchronization
    5.2.1.4 Auto-Negotiation
    5.2.1.5 PMA SerDes
    5.2.2 Comma Detection
    5.3 Reduced Gigabit Media Independent Interface
    5.3.1 Introduction to Reduced Gigabit Media Independent Interface (RGMII)
    5.3.2 Description of Reduced Gigabit Media Independent Interface (RGMII)
    5.3.3 RGMII Clocks
    5.3.4 Signal Conversion
    5.3.4.1 Transmit Data Conversion
    5.3.4.2 Transmit Control Signal Conversion
    5.3.4.3 Receive Data Conversion
    5.3.4.4 Receive Control Signal Conversion
    5.3.4.5 Receive Status Signal Conversion
    5.3.5 RGMII Transmit Timing
    5.3.6 RGMII Receive Timing
    5.3.7 Enabling Reduced Gigabit Media Independent Interface
    5.4 Reduced Media Independent Interface
    5.4.1 Introduction to Reduced Media Independent Interface
    5.4.2 Description of Reduced Media Independent Interface
    5.4.2.1 Transmit Bit Ordering
    5.4.2.2 RMII Transmit Timing Diagrams
    5.4.2.3 Receive Bit Ordering
    5.4.3 Enabling Reduced Media Independent Interface
    5.5 Serial Media Independent Interface
    5.5.1 Introduction to Serial Media Independent Interface
    5.5.2 Description of Serial Media Independent Interface
    5.5.3 SMII Timing
    5.5.3.1 100 Mbps Mode
    5.5.3.2 10 Mbps Mode
    5.5.4 Enabling Serial Media Independent Interface
    5.6 Reverse Media Independent Interface
    5.6.1 Introduction to Reverse Media Independent Interface
    5.6.2 Description of Reverse Media Independent Interface
    5.6.2.1 RevMII MAC Interface
    5.6.2.2 RevMII Controller
    5.6.3 RevMII Interrupts
    5.6.4 RevMII Registers
    5.6.4.1 RevMII Register Maps
    5.6.4.2 MAC_RevMII_PHY_Control
    5.6.4.3 MAC_RevMII_Common_Status
    5.6.4.4 MAC_RevMII_Common_Ext_Status
    5.6.4.5 MAC_RevMII_Interrupt_Status_Mask
    5.6.4.6 MAC_RevMII_Remote_PHY_Status
    5.6.5 Enabling Reverse Media Independent Interface
    5.7 Serial Gigabit Media Independent Interface
    5.7.1 Introduction to Serial Gigabit Media Independent Interface
    5.7.2 Description of Serial Gigabit Media Independent Interface
    5.7.2.1 Rate Adapter Layer (RAL)
    5.7.2.2 Physical Coding Sub-Layer (PCS)
    5.7.2.3 Serializer and Deserializer (SerDes) in the SGMII Block
    5.7.2.4 High-Speed I/O
    5.7.3 Enabling Serial Gigabit Media Independent Interface
    5.8 Reduced Ten-Bit Interface
    5.8.1 Introduction to Reduced Ten-Bit Interface
    5.8.2 Description of Reduced Ten-Bit Interface
    5.8.3 RTBI Transmit Timing
    5.8.4 Enabling Reduced Ten-Bit Interface
    5.9 Multiple PHY Interfaces
    6 Packet Filtering
    6.1 Packet Filtering Sequence
    6.2 Source Address or Destination Address Filtering
    6.2.1 Introduction to Source or Destination Address Filtering
    6.2.2 Enabling Additional MAC Address Registers
    6.2.3 Configuring Address Filter Hash Table
    6.2.4 Programming Different Types of Address Filtering
    6.2.4.1 Unicast Destination Address Filtering
    6.2.4.2 Multicast Destination Address Filtering
    6.2.4.3 Hash or Perfect Address Filtering
    6.2.4.4 Broadcast Address Filtering
    6.2.4.5 Unicast Source Address Filtering
    6.2.4.6 Inverse Filtering
    6.3 VLAN Filtering
    6.3.1 VLAN Tag Perfect Filtering
    6.3.2 VLAN Tag Hash Filtering
    6.3.2.1 Enabling VLAN Tag Hash Filtering
    6.4 VLAN Filter Fail Packets Queue
    6.5 Extended Receive VLAN Filtering and Routing
    6.5.1 Comparison Modes
    6.5.2 Filtering
    6.5.3 Filter Status
    6.5.4 Stripping
    6.5.5 Enabling Extended Receive VLAN Filtering
    6.5.6 Programming Guidelines for Extended VLAN Filtering and Routing on Receive
    6.6 Layer 3 and Layer 4 Filtering
    6.6.1 Introduction to Layer 3 and Layer 4 Filtering
    6.6.2 Description of Layer 3 and Layer 4 Filtering
    6.6.2.1 Layer 3 Filtering
    6.6.2.2 Layer 4 Filtering
    6.6.3 Layer 3 and Layer 4 Filters Registers
    6.6.4 Enabling Layer 3 and Layer 4 Filtering
    6.7 Flexible Receive Parser
    6.7.1 Overview of Flexible Receive Parser
    6.7.2 Description of Flexible Receive Parser
    6.7.2.1 Instruction Table Format of the Flexible Receive Parser
    6.7.2.2 Number of Valid Entries (NVE)
    6.7.2.3 Number of Parsable Entries (NPE)
    6.7.2.4 Frame Offset
    6.7.2.5 Frame Reject
    6.7.2.6 Out of Order Processing
    6.7.2.7 Ethernet Line Speed Dependency
    6.7.2.8 DMA Channel Selection
    6.7.2.9 Receive Queue Selection
    6.7.2.10 MAC Packet Filtering/Drop/Error Handling
    6.7.2.11 PAD Strip/CRC Strip Handling
    6.7.2.12 VLAN Strip Handling
    6.7.2.13 Multicast and Broadcast Support
    6.7.2.14 Pre-emption Support
    6.7.2.15 Software Access to the Flexible Receive Parser Memory
    6.7.2.16 Statistical Counters
    6.7.2.17 Changing the Instruction Table by Software
    6.7.2.18 Receive Cut-Through Functionality
    6.7.2.19 Receive Packet Drop Indication
    6.7.2.20 Runt Packet Handling
    6.7.2.21 Uncorrectable ECC Error Handling
    6.7.3 Enabling/Disabling the Flexible Receive Parser
    6.7.4 Signals Related to Flexible Receive Parser
    6.7.5 Registers Related to Flexible Receive Parser
    6.7.6 Programming Guidelines for Flexible Receive Parser
    7 IEEE 1588 Timestamp Support
    7.1 IEEE 1588 Timestamp Support
    7.1.1 Introduction to IEEE 1588 Timestamp Support
    7.1.2 Description of IEEE 1588 Timestamp Support
    7.1.2.1 Clock Types
    7.1.2.2 Delay Request-Response Mechanism
    7.1.2.3 Peer-to-Peer PTP Transparent Clock (P2P TC) Message Support
    7.1.2.4 Timestamp Correction
    7.1.2.5 Transmit Path Functions
    7.1.2.6 Receive Path Functions
    7.1.3 Enabling IEEE 1588 Timestamp Support
    7.1.4 Programming Guidelines for IEEE 1588 Timestamping (System Time Correction)
    7.2 IEEE 1588 System Time Source
    7.2.1 Introduction to IEEE 1588 System Time Source
    7.2.2 Description of IEEE 1588 System Time Source
    7.2.2.1 External Timestamp Input
    7.2.2.2 Internal Reference Time
    7.2.2.3 System Time Register Module
    7.2.3 Selecting IEEE 1588 Time Source Type
    7.3 Programming Guidelines for IEEE 1588 Timestamping (For Internal Timestamp Source Configuration)
    7.4 IEEE 1588 Higher Word Register
    7.4.1 Introduction to IEEE 1588 Higher Word Register
    7.4.2 Enabling IEEE 1588 Higher Word Register
    7.5 IEEE 1588 Auxillary Snapshot
    7.5.1 Overview of IEEE 1588 Auxillary Snapshot
    7.5.2 Description of IEEE 1588 Auxillary Snapshot
    7.5.3 Enabling IEEE 1588 Auxillary Snapshot
    7.6 Flexible Pulse-Per-Second Output
    7.6.1 Overview of Flexible Pulse-Per-Second Output
    7.6.2 Description of Flexible Pulse-Per-Second (PPS) Output
    7.6.2.1 PPS Start or Stop Time
    7.6.2.2 PPS Width and Interval
    7.6.3 Enabling Flexible Pulse-Per-Second Output
    7.7 Media Clock Generation and Recovery
    7.7.1 Overview of Media Clock Generation and Recovery
    7.7.2 Description of Media Clock Generation and Recovery
    7.7.2.1 Presentation Time Counter
    7.7.2.2 Comparator Modules
    7.7.2.3 Media Clock Generation and Recovery Flow
    7.7.3 Enabling Media Generation and Recovery
    7.7.4 Signals Related to Media Generation and Recovery
    7.7.5 Registers Related to Media Clock Generation and Recovery
    7.7.6 Programming Guidelines for Media Clock Generation and Recovery
    7.8 PTP Timestamp Offload Function
    7.8.1 Introduction to PTP Timestamp Offload Function
    7.8.2 Description of PTP Offload Function
    7.8.2.1 PTP Packet Generation
    7.8.2.2 PTP Message-Specific Fields
    7.8.3 Enabling PTP Timestamp Offload Function
    7.9 One-Step Timestamp
    7.9.1 Introduction to One-Step Timestamp
    7.9.2 Description of One-Step Timestamp
    7.9.2.1 MAC Transmit PTP Mode
    7.9.3 Enabling One-Step Timestamp
    7.10 One-Step Time Stamping for PTP Over UDP
    7.10.1 Introduction to One-Step Timestamping for PTP Over UDP
    7.10.2 Checksum Update for One-Step Timestamping for PTP Over UDP
    7.11 IEEE 1588 Sub Nanoseconds Timestamp
    7.11.1 Description of IEEE 1588 Sub Nanoseconds Timestamp
    7.11.2 Enabling IEEE 1588 Sub Nanoseconds Timestamp
    8 Multiple Channels and Queues Support
    8.1 Block Diagram
    8.2 Multiple Queues and Channels Support in the Transmit Path (for EQOS-AHB, EQOS-AXI, and EQOS-DMA)
    8.2.1 Introduction to Multiple Queues Support in the Transmit Path
    8.2.2 Description of Fixed Priority Scheme in EQOS-AHB and EQOS-DMA
    8.2.3 Description of Fixed Priority Scheme in EQOS-AXI
    8.2.4 Description of Weighted Strict Priority in EQOS-AHB and EQOS-DMA
    8.2.5 Description of Weighted Round Robin in EQOS-AHB and EQOS-DMA
    8.2.6 Selecting the Number of Transmit Queues
    8.2.7 Programming Guidelines for Multiple Queues and Channels in the Transmit Path
    8.3 Multiple Queues and Channels Support in the Receive Path
    8.3.1 Introduction to Multiple Queues in the Receive Path
    8.3.2 Description of Multiple Queues in the Receive Path
    8.3.2.1 Priority Scheme for Tx DMA and Rx DMA
    8.3.3 Selecting the Number of Receive Queues and Channels
    8.3.4 Programming Guidelines for Multiple Queues and Channels in the Receive Path
    8.4 Multiple Queues and Channels Support in EQOS-MTL
    8.4.1 Introduction to Multiple Queues and Channels Support in EQOS-MTL
    8.4.2 Queue Memory
    8.4.3 Selecting the Number of Transmit Queues in EQOS-MTL
    8.5 Rx Queue to DMA Mapping
    8.5.1 Static Mapping
    8.5.2 Dynamic (Per Packet) Mapping
    8.5.2.1 Broadcast/Multicast Packet Duplication
    8.6 Selection of Tag Priorities Assigned to Tx and Rx Queues
    8.7 Rx Side Routing from MAC to Queues
    8.8 Rx Side Arbitration Between DMA and MTL
    8.9 Tx Side Arbitration between DMA and MTL
    8.10 Data Centre Bridging
    8.10.1 Introduction to Data Centre Bridging
    8.10.2 Description of Data Center Bridging Feature
    8.10.2.1 Weighted Round Robin
    8.10.2.2 Deficit Weighted Round Robin
    8.10.2.3 Weighted Fair Queuing
    8.10.3 Enabling Data Center Bridging
    8.11 Audio Video Bridging
    8.11.1 Introduction to AV Feature
    8.11.2 Transmit Path Functions
    8.11.3 Receive Path Functions
    8.11.4 Credit-Based Shaper Algorithm
    8.11.4.1 Credit Value
    8.11.4.2 idleSlopeCredit and sendSlopeCredit Values
    8.11.4.3 Bandwidth Status
    8.11.5 Enabling AV Bridging
    8.11.6 Slot Number Function and Audio Video Bridging
    8.11.6.1 Introduction to Slot Number Function
    8.11.6.2 Description of Slot Number Function
    8.11.7 Programming Guidelines for Initializing the DMA
    8.11.8 Programming Guidelines for Enabling Slot Number Checking
    8.11.9 Programming Guidelines for Enabling Average Bits Per Slot Reporting
    8.12 Queue Modes
    8.12.1 Programming Guidelines for Disabling Flow Control in AV Queues
    8.13 Queue Priorities
    8.14 Enhancements to Scheduled Traffic (EST)
    8.14.1 Frequently Used Terms in EST
    8.14.2 Updates to the Transmit Scheduling to Support EST
    8.14.2.1 Implementation of Gate Control List (GCL)
    8.14.2.2 Registers Related to Gate Control List
    8.14.2.3 Transmission Gating Implementation
    8.14.3 Idle Slope Computation Updates
    8.14.3.1 Operational Details of GCL
    8.14.3.2 Installing a New GCL
    8.14.4 Impact of Transmit Scheduling Algorithms on EST
    8.14.5 Programming Guidelines for EST
    8.15 Frame Preemption (FPE)
    8.15.1 Overview of the Frame Preemption
    8.15.2 Description of the Frame Preemption
    8.15.3 Enabling the Frame Preemption
    8.15.4 GCL Modification to Support FPE
    8.15.5 Impact of Preemption on CBS
    8.15.6 mPacket Format
    8.15.7 Transmit Preemption
    8.15.7.1 MTL Tx Preemption
    8.15.7.2 MAC Tx Preemption
    8.15.8 Receive Preemption
    8.15.8.1 MAC Receive Preemption
    8.15.9 Received Preemption Frames Support in Offload Engines
    8.15.10 Verify and Respond mPackets
    8.15.11 Frame Preemption and MMC Counter and Interrupt Registers
    8.15.11.1 Additional Registers Associated With MMC Interrupts
    8.16 Time-Based Scheduling
    8.16.1 Description of Time-Based Scheduling
    8.16.2 Definitions Used
    8.16.2.1 Launch Time
    8.16.2.2 Launch Expiry Time
    8.16.2.3 Fetch Time
    8.16.3 Enabling the Time-Based Scheduling Feature
    8.16.4 Programming Guidelines for Time-Based Scheduling
    8.16.5 Time-Based Scheduling Flow
    9 TCP/IP Offloading Features
    9.1 Transmit Checksum Offload Engine
    9.1.1 Overview of Transmit Checksum Offload Engine
    9.1.2 Description of Transmit Checksum Offload Engine
    9.1.2.1 IP Header Checksum Engine
    9.1.2.2 TCP/UDP/ICMP Checksum Engine
    9.1.3 Enabling the Transmit Checksum Offload Engine
    9.2 Receive Checksum Offload Engine
    9.2.1 Overview of Receive Checksum Offload Engine
    9.2.2 Description of Receive Checksum Offload Engine
    9.2.3 Enabling the Receive Checksum Offload Engine
    9.3 Header-Payload Split
    9.3.1 Enabling Splitting the Header on Receive
    9.3.2 Programming Guidelines for Splitting the Header on Receive
    9.4 TCP/IP Segmentation Offload (TSO) Engine
    9.4.1 Overview of TCP/IP Segmentation Offload Engine
    9.4.2 Description of TCP Segmentation Offload Engine
    9.4.2.1 DMA Operation with TSO Feature
    9.4.2.2 TCP/IP Header Fields
    9.4.2.3 Header and Payload Fields of Segmented Packets
    9.4.2.4 Context Descriptor Sequence
    9.4.3 Building the Descriptor and the Packet for the TSO Feature
    9.4.4 Enabling the TSO Engine
    9.4.5 Programming Guidelines for TSO
    9.4.6 External TSO Memory Interface
    9.4.6.1 External TSO Memory Interface Signals
    9.4.6.2 TSO Memory Synchronous Timing
    9.4.6.3 Enabling the External TSO Memory Interface
    9.5 UDP/IPv4 Fragment Offload (UFO) Engine
    9.5.1 Description of UFO Engine
    9.5.1.1 UFO with valid UDP checksum
    9.5.1.2 UFO with no UDP checksum
    9.5.2 Segmentation Versus Fragmentation
    9.5.3 Enabling the UFO Engine
    9.5.4 Registers for the UFO Engine
    9.5.5 Programming Guidelines for the UFO Engine
    9.6 Using the IPv4 ARP Offload Engine
    9.6.1 Introduction to IPv4 ARP Offload Engine
    9.6.2 Description of IPv4 ARP Offload Engine
    9.6.3 Enabling the IPv4 ARP Offload Engine
    10 Power Management and Energy Efficient Ethernet
    10.1 Overview of Low-Power Management
    10.2 Description of Magic Packet Mode
    10.2.1 Magic Packet Data Format
    10.3 Description of Remote Wakeup Packet Mode
    10.4 Design Partitioning for Low-Power Support
    10.5 Remote Wake-Up Packet Filters
    10.6 PMT Interrupt
    10.7 Enabling PMT through Remote Wake-Up Packet Mode
    10.8 Enabling PMT through Magic Packet Mode
    10.9 Power-Down and Power-Up Sequence
    10.9.1 Power-Down Sequence
    10.9.2 Power-Up Sequence
    10.10 Description of Energy Efficient Ethernet
    10.10.1 Transmit Path Functions
    10.10.2 Automated Entry/Exit of LPI mode in Transmit Path
    10.10.3 Receive Path Functions
    10.10.4 EEE Registers
    10.10.5 EEE Signals
    10.10.6 LPI Timers
    10.10.7 LPI Interrupt
    10.10.8 Enabling Energy Efficient Ethernet (EEE)
    10.10.9 Programming Guidelines for Energy Efficient Ethernet
    11 MAC Management Counters
    11.1 MAC Management Counters
    11.2 Address Assignments
    11.3 Enabling MAC Management Counters
    12 Flow Control
    12.1 Transmit Flow Control
    12.1.1 Flow Control in Full-Duplex Mode
    12.1.1.1 Pause Packet Structure
    12.1.1.2 Pause Packet Control
    12.1.2 Flow Control in Half-Duplex Mode
    12.1.3 Enabling Transmit Flow Control
    12.1.4 Triggering Transmit Flow Control
    12.2 Receive Flow Control
    12.2.1 Description of Receive Flow Control
    12.2.2 Enabling Receive Flow Control
    13 Loopback Mode
    13.1 Loopback Mode
    13.1.1 Guidelines for Using Loopback Mode
    13.1.2 Enabling Loopback Mode
    14 Automotive Safety Features
    14.1 Error Correction Code (ECC) Protection for Memories
    14.1.1 Overview
    14.1.2 Description of ECC Protection for Memories
    14.1.2.1 Handling the Address Mismatch
    14.1.2.2 Diagnostic Support for the Error Management
    14.1.2.3 Handling the Uncorrectable Errors
    14.1.2.4 ECC Error Injection Capabilities
    14.1.3 Enabling ECC Protection for Memories
    14.1.4 Signals Related to ECC Protection for Memories
    14.1.5 Registers Related to ECC Protection for Memories
    14.1.6 Programming Guidelines for ECC Protection for Memories
    14.2 On-Chip Data Path Parity Protection
    14.2.1 Overview
    14.2.2 Description
    14.2.2.1 Transmit Datapath Parity Protection
    14.2.2.2 Receive Data Path Parity Protection
    14.2.2.3 AXI Slave Data Path Parity Protection
    14.2.2.4 Parity Error Injection
    14.2.2.5 Interrupt for Parity Error
    14.2.3 Enabling On-Chip Data Path Parity Protection
    14.2.4 Signals Related to On-Chip Data Path Parity Protection
    14.2.5 Registers Related to On-Chip Data Path Parity Protection
    14.2.6 Programming Guidelines for On-Chip Data Path Parity Protection
    14.3 FSM Parity and Timeout Protection
    14.3.1 Overview
    14.3.2 Description
    14.3.2.1 FSM State Parity Protection
    14.3.2.2 FSM Timeout Protection
    14.3.3 Enabling FSM Parity and Timeout Protection
    14.3.4 Signals Related to FSM Parity and Timeout Protection
    14.3.5 Registers Related to FSM Parity and Timeout Protection
    14.3.6 Programming Guidelines for FSM Parity and Timeout Protection
    14.4 Application/CSR Interface Timeout Protection
    14.4.1 Overview
    14.4.2 Description
    14.4.2.1 AHB Master Interface
    14.4.2.2 ATI and ARI Interface
    14.4.2.3 AXI Master Interface
    14.4.2.4 AXI Slave Interface
    14.4.3 Enabling Application/CSR Interface Timeout Protection
    14.4.4 Signals Related to Application/CSR Interface Timeout Protection
    14.4.5 Programming Guidelines for Application/CSR Interface Timeout Protection
    15 Parameter Descriptions
    15.1 Features / Application Interface Parameters
    15.2 Features / General Features Parameters
    15.3 Features / General Features / CDC Synchronization Parameters
    15.4 Features / Buffer Management Parameters
    15.5 Features / PHY Interface Parameters
    15.6 Features / Filtering Parameters
    15.7 Features / Multiple Queues Support Parameters
    15.8 Features / IEEE 1588 Timestamp Parameters
    15.9 Features / Time Sensitive Networking Parameters
    15.10 Features / Time Based Scheduling Parameters
    15.11 Features / TCP/IP Offloading Features Parameters
    15.12 Features / Low Power Management Parameters
    15.13 Features / RMON Counters Parameters
    15.14 Features / RMON Counters / RMON Transmit Counters Parameters
    15.15 Features / RMON Counters / RMON Receive Counters Parameters
    15.16 Features / RMON Counters / RMON IPC Receive Counters Parameters
    15.17 Features / Automotive Safety features Parameters
    16 Signal Descriptions
    16.1 MII Clocks and Reset Signals
    16.2 MAC Control Interface Signals
    16.3 MAC Application Clock and Reset Interface Signals
    16.4 SGMII/TBI/RTBI/SMII Clocks and Reset Signals
    16.5 RMII Clocks and Reset Signals
    16.6 RGMII/RTBI Clocks and Reset Signals
    16.7 TBI Interface Signals
    16.8 RevMII Interface Signals
    16.9 IEEE 1588 Timestamp Interface Signals
    16.10 Sideband Interface Signals
    16.11 TBI/SGMII/RTBI/SMII PHY Interface Signals
    16.12 General Purpose Interface Signals
    16.13 Test Mode Interface Signals
    16.14 Energy Efficient Ethernet Interface Signals
    16.15 Power Management Interface Signals
    16.16 PHY Interface Signals
    16.17 SMA Interface Signals
    16.18 APB Interface Signals
    16.19 AXI Master Interface Signals
    16.20 AXI Slave Interface Signals
    16.21 AXI Low Power Interface Signals
    16.22 AHB Master Interface Signals
    16.23 AHB Slave Interface Signals
    16.24 MDC Interface Signals
    16.25 TSO Memory Interface (TMI) Signals
    16.26 Application Transmit Interface (ATI) Signals
    16.27 Application Receive Interface (ARI) Signals
    16.28 Rx Parser Interface Signals
    16.29 DPRAM Interface Signals
    16.30 SPRAM Interface Signals
    16.31 MAC Tx Interface Signals
    16.32 MAC Rx Interface Signals
    16.33 EST Memory Interface Signals
    16.34 Debug Bus Interface Signals
    17 Register Descriptions
    17.1 EQOS_MAC Registers
    17.1.1 MAC_Configuration
    17.1.2 MAC_Ext_Configuration
    17.1.3 MAC_Packet_Filter
    17.1.4 MAC_Watchdog_Timeout
    17.1.5 MAC_Hash_Table_Reg0
    17.1.6 MAC_Hash_Table_Reg1
    17.1.7 MAC_Hash_Table_Reg2
    17.1.8 MAC_Hash_Table_Reg3
    17.1.9 MAC_Hash_Table_Reg4
    17.1.10 MAC_Hash_Table_Reg5
    17.1.11 MAC_Hash_Table_Reg6
    17.1.12 MAC_Hash_Table_Reg7
    17.1.13 MAC_VLAN_Tag
    17.1.14 MAC_VLAN_Tag_Ctrl
    17.1.15 MAC_VLAN_Tag_Data
    17.1.16 MAC_VLAN_Tag_Filter(#i) (for i = 0; i <= DWC_EQOS_NRVF-1)
    17.1.17 MAC_VLAN_Hash_Table
    17.1.18 MAC_VLAN_Incl(#i) (for i = 0; i <= DWC_EQOS_NUM_TXQ-1)
    17.1.19 MAC_VLAN_Incl
    17.1.20 MAC_Inner_VLAN_Incl
    17.1.21 MAC_Q0_Tx_Flow_Ctrl
    17.1.22 MAC_Q(#i)_Tx_Flow_Ctrl (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.1.23 MAC_Rx_Flow_Ctrl
    17.1.24 MAC_RxQ_Ctrl4
    17.1.25 MAC_TxQ_Prty_Map0
    17.1.26 MAC_TxQ_Prty_Map1
    17.1.27 MAC_RxQ_Ctrl0
    17.1.28 MAC_RxQ_Ctrl1
    17.1.29 MAC_RxQ_Ctrl2
    17.1.30 MAC_RxQ_Ctrl3
    17.1.31 MAC_Interrupt_Status
    17.1.32 MAC_Interrupt_Enable
    17.1.33 MAC_Rx_Tx_Status
    17.1.34 MAC_PMT_Control_Status
    17.1.35 MAC_RWK_Packet_Filter
    17.1.36 RWK_Filter(#i)_Byte_Mask (for i = 0; i <= DWC_EQOS_NUM_PMT_RWK_FILT-1)
    17.1.37 RWK_Filter(#i)(#j)_CRC (for i = 0; i <= (DWC_EQOS_NUM_PMT_RWK_FILT/2)-1)
    17.1.38 RWK_Filter(#i)(#j)(#k)(#l)_Offset (for i = 0; i <= (DWC_EQOS_NUM_PMT_RWK_FILT/4)-1)
    17.1.39 RWK_Filter(#i)(#j)(#k)(#l)_Command (for i = 0; i <= (DWC_EQOS_NUM_PMT_RWK_FILT/4)-1)
    17.1.40 MAC_LPI_Control_Status
    17.1.41 MAC_LPI_Timers_Control
    17.1.42 MAC_LPI_Entry_Timer
    17.1.43 MAC_1US_Tic_Counter
    17.1.44 MAC_AN_Control
    17.1.45 MAC_AN_Status
    17.1.46 MAC_AN_Advertisement
    17.1.47 MAC_AN_Link_Partner_Ability
    17.1.48 MAC_AN_Expansion
    17.1.49 MAC_TBI_Extended_Status
    17.1.50 MAC_PHYIF_Control_Status
    17.1.51 MAC_Version
    17.1.52 MAC_Debug
    17.1.53 MAC_HW_Feature0
    17.1.54 MAC_HW_Feature1
    17.1.55 MAC_HW_Feature2
    17.1.56 MAC_HW_Feature3
    17.1.57 MAC_DPP_FSM_Interrupt_Status
    17.1.58 MAC_AXI_SLV_DPE_Addr_Status
    17.1.59 MAC_FSM_Control
    17.1.60 MAC_FSM_ACT_Timer
    17.1.61 SNPS_SCS_REG1
    17.1.62 MAC_MDIO_Address
    17.1.63 MAC_MDIO_Data
    17.1.64 MAC_GPIO_Control
    17.1.65 MAC_GPIO_Status
    17.1.66 MAC_ARP_Address
    17.1.67 MAC_CSR_SW_Ctrl
    17.1.68 MAC_FPE_CTRL_STS
    17.1.69 MAC_Ext_Cfg1
    17.1.70 MAC_Presn_Time_ns
    17.1.71 MAC_Presn_Time_Updt
    17.1.72 MAC_Address0_High
    17.1.73 MAC_Address0_Low
    17.1.74 MAC_Address(#i)_High (for i = 1; i <= DWC_EQOS_ADD_MAC_ADDR_REG-1)
    17.1.75 MAC_Address(#i)_Low (for i = 1; i <= DWC_EQOS_ADD_MAC_ADDR_REG-1)
    17.1.76 MAC_Address(#i)_High (for i = 32; i <= 63)
    17.1.77 MAC_Address(#i)_Low (for i = 32; i <= 63)
    17.1.78 MAC_Address(#i)_High (for i = 64; i <= 127)
    17.1.79 MAC_Address(#i)_Low (for i = 64; i <= 127)
    17.1.80 MMC_Control
    17.1.81 MMC_Rx_Interrupt
    17.1.82 MMC_Tx_Interrupt
    17.1.83 MMC_Rx_Interrupt_Mask
    17.1.84 MMC_Tx_Interrupt_Mask
    17.1.85 Tx_Octet_Count_Good_Bad
    17.1.86 Tx_Packet_Count_Good_Bad
    17.1.87 Tx_Broadcast_Packets_Good
    17.1.88 Tx_Multicast_Packets_Good
    17.1.89 Tx_64Octets_Packets_Good_Bad
    17.1.90 Tx_65To127Octets_Packets_Good_Bad
    17.1.91 Tx_128To255Octets_Packets_Good_Bad
    17.1.92 Tx_256To511Octets_Packets_Good_Bad
    17.1.93 Tx_512To1023Octets_Packets_Good_Bad
    17.1.94 Tx_1024ToMaxOctets_Packets_Good_Bad
    17.1.95 Tx_Unicast_Packets_Good_Bad
    17.1.96 Tx_Multicast_Packets_Good_Bad
    17.1.97 Tx_Broadcast_Packets_Good_Bad
    17.1.98 Tx_Underflow_Error_Packets
    17.1.99 Tx_Single_Collision_Good_Packets
    17.1.100 Tx_Multiple_Collision_Good_Packets
    17.1.101 Tx_Deferred_Packets
    17.1.102 Tx_Late_Collision_Packets
    17.1.103 Tx_Excessive_Collision_Packets
    17.1.104 Tx_Carrier_Error_Packets
    17.1.105 Tx_Octet_Count_Good
    17.1.106 Tx_Packet_Count_Good
    17.1.107 Tx_Excessive_Deferral_Error
    17.1.108 Tx_Pause_Packets
    17.1.109 Tx_VLAN_Packets_Good
    17.1.110 Tx_OSize_Packets_Good
    17.1.111 Rx_Packets_Count_Good_Bad
    17.1.112 Rx_Octet_Count_Good_Bad
    17.1.113 Rx_Octet_Count_Good
    17.1.114 Rx_Broadcast_Packets_Good
    17.1.115 Rx_Multicast_Packets_Good
    17.1.116 Rx_CRC_Error_Packets
    17.1.117 Rx_Alignment_Error_Packets
    17.1.118 Rx_Runt_Error_Packets
    17.1.119 Rx_Jabber_Error_Packets
    17.1.120 Rx_Undersize_Packets_Good
    17.1.121 Rx_Oversize_Packets_Good
    17.1.122 Rx_64Octets_Packets_Good_Bad
    17.1.123 Rx_65To127Octets_Packets_Good_Bad
    17.1.124 Rx_128To255Octets_Packets_Good_Bad
    17.1.125 Rx_256To511Octets_Packets_Good_Bad
    17.1.126 Rx_512To1023Octets_Packets_Good_Bad
    17.1.127 Rx_1024ToMaxOctets_Packets_Good_Bad
    17.1.128 Rx_Unicast_Packets_Good
    17.1.129 Rx_Length_Error_Packets
    17.1.130 Rx_Out_Of_Range_Type_Packets
    17.1.131 Rx_Pause_Packets
    17.1.132 Rx_FIFO_Overflow_Packets
    17.1.133 Rx_VLAN_Packets_Good_Bad
    17.1.134 Rx_Watchdog_Error_Packets
    17.1.135 Rx_Receive_Error_Packets
    17.1.136 Rx_Control_Packets_Good
    17.1.137 Tx_LPI_USEC_Cntr
    17.1.138 Tx_LPI_Tran_Cntr
    17.1.139 Rx_LPI_USEC_Cntr
    17.1.140 Rx_LPI_Tran_Cntr
    17.1.141 MMC_IPC_Rx_Interrupt_Mask
    17.1.142 MMC_IPC_Rx_Interrupt
    17.1.143 RxIPv4_Good_Packets
    17.1.144 RxIPv4_Header_Error_Packets
    17.1.145 RxIPv4_No_Payload_Packets
    17.1.146 RxIPv4_Fragmented_Packets
    17.1.147 RxIPv4_UDP_Checksum_Disabled_Packets
    17.1.148 RxIPv6_Good_Packets
    17.1.149 RxIPv6_Header_Error_Packets
    17.1.150 RxIPv6_No_Payload_Packets
    17.1.151 RxUDP_Good_Packets
    17.1.152 RxUDP_Error_Packets
    17.1.153 RxTCP_Good_Packets
    17.1.154 RxTCP_Error_Packets
    17.1.155 RxICMP_Good_Packets
    17.1.156 RxICMP_Error_Packets
    17.1.157 RxIPv4_Good_Octets
    17.1.158 RxIPv4_Header_Error_Octets
    17.1.159 RxIPv4_No_Payload_Octets
    17.1.160 RxIPv4_Fragmented_Octets
    17.1.161 RxIPv4_UDP_Checksum_Disable_Octets
    17.1.162 RxIPv6_Good_Octets
    17.1.163 RxIPv6_Header_Error_Octets
    17.1.164 RxIPv6_No_Payload_Octets
    17.1.165 RxUDP_Good_Octets
    17.1.166 RxUDP_Error_Octets
    17.1.167 RxTCP_Good_Octets
    17.1.168 RxTCP_Error_Octets
    17.1.169 RxICMP_Good_Octets
    17.1.170 RxICMP_Error_Octets
    17.1.171 MMC_FPE_Tx_Interrupt
    17.1.172 MMC_FPE_Tx_Interrupt_Mask
    17.1.173 MMC_Tx_FPE_Fragment_Cntr
    17.1.174 MMC_Tx_Hold_Req_Cntr
    17.1.175 MMC_FPE_Rx_Interrupt
    17.1.176 MMC_FPE_Rx_Interrupt_Mask
    17.1.177 MMC_Rx_Packet_Assembly_Err_Cntr
    17.1.178 MMC_Rx_Packet_SMD_Err_Cntr
    17.1.179 MMC_Rx_Packet_Assembly_OK_Cntr
    17.1.180 MMC_Rx_FPE_Fragment_Cntr
    17.1.181 MAC_L3_L4_Control(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.182 MAC_Layer4_Address(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.183 MAC_Layer3_Addr0_Reg(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.184 MAC_Layer3_Addr1_Reg(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.185 MAC_Layer3_Addr2_Reg(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.186 MAC_Layer3_Addr3_Reg(#i) (for i = 0; i <= DWC_EQOS_L3_L4_FILTER_NUM-1)
    17.1.187 MAC_Timestamp_Control
    17.1.188 MAC_Sub_Second_Increment
    17.1.189 MAC_System_Time_Seconds
    17.1.190 MAC_System_Time_Nanoseconds
    17.1.191 MAC_System_Time_Seconds_Update
    17.1.192 MAC_System_Time_Nanoseconds_Update
    17.1.193 MAC_Timestamp_Addend
    17.1.194 MAC_System_Time_Higher_Word_Seconds
    17.1.195 MAC_Timestamp_Status
    17.1.196 MAC_Tx_Timestamp_Status_Nanoseconds
    17.1.197 MAC_Tx_Timestamp_Status_Seconds
    17.1.198 MAC_Auxiliary_Control
    17.1.199 MAC_Auxiliary_Timestamp_Nanoseconds
    17.1.200 MAC_Auxiliary_Timestamp_Seconds
    17.1.201 MAC_Timestamp_Ingress_Asym_Corr
    17.1.202 MAC_Timestamp_Egress_Asym_Corr
    17.1.203 MAC_Timestamp_Ingress_Corr_Nanosecond
    17.1.204 MAC_Timestamp_Egress_Corr_Nanosecond
    17.1.205 MAC_Timestamp_Ingress_Corr_Subnanosec
    17.1.206 MAC_Timestamp_Egress_Corr_Subnanosec
    17.1.207 MAC_Timestamp_Ingress_Latency
    17.1.208 MAC_Timestamp_Egress_Latency
    17.1.209 MAC_PPS_Control
    17.1.210 MAC_PPS(#i)_Target_Time_Seconds (for i = 0; i <= DWC_EQOS_PPS_OUT_NUM-1)
    17.1.211 MAC_PPS(#i)_Target_Time_Nanoseconds (for i = 0; i <= DWC_EQOS_PPS_OUT_NUM-1)
    17.1.212 MAC_PPS(#i)_Interval (for i = 0; i <= DWC_EQOS_PPS_OUT_NUM-1)
    17.1.213 MAC_PPS(#i)_Width (for i = 0; i <= DWC_EQOS_PPS_OUT_NUM-1)
    17.1.214 MAC_PTO_Control
    17.1.215 MAC_Source_Port_Identity0
    17.1.216 MAC_Source_Port_Identity1
    17.1.217 MAC_Source_Port_Identity2
    17.1.218 MAC_Log_Message_Interval
    17.2 EQOS_MTL Registers
    17.2.1 MTL_Operation_Mode
    17.2.2 MTL_DBG_CTL
    17.2.3 MTL_DBG_STS
    17.2.4 MTL_FIFO_Debug_Data
    17.2.5 MTL_Interrupt_Status
    17.2.6 MTL_RxQ_DMA_Map0
    17.2.7 MTL_RxQ_DMA_Map1
    17.2.8 MTL_TBS_CTRL
    17.2.9 MTL_EST_Control
    17.2.10 MTL_EST_Status
    17.2.11 MTL_EST_Sch_Error
    17.2.12 MTL_EST_Frm_Size_Error
    17.2.13 MTL_EST_Frm_Size_Capture
    17.2.14 MTL_EST_Intr_Enable
    17.2.15 MTL_EST_GCL_Control
    17.2.16 MTL_EST_GCL_Data
    17.2.17 MTL_FPE_CTRL_STS
    17.2.18 MTL_FPE_Advance
    17.2.19 MTL_RXP_Control_Status
    17.2.20 MTL_RXP_Interrupt_Control_Status
    17.2.21 MTL_RXP_Drop_Cnt
    17.2.22 MTL_RXP_Error_Cnt
    17.2.23 MTL_RXP_Indirect_Acc_Control_Status
    17.2.24 MTL_RXP_Indirect_Acc_Data
    17.2.25 MTL_ECC_Control
    17.2.26 MTL_Safety_Interrupt_Status
    17.2.27 MTL_ECC_Interrupt_Enable
    17.2.28 MTL_ECC_Interrupt_Status
    17.2.29 MTL_ECC_Err_Sts_Rctl
    17.2.30 MTL_ECC_Err_Addr_Status
    17.2.31 MTL_ECC_Err_Cntr_Status
    17.2.32 MTL_DPP_Control
    17.3 EQOS_MTL_Q0 Registers
    17.3.1 MTL_TxQ0_Operation_Mode
    17.3.2 MTL_TxQ0_Underflow
    17.3.3 MTL_TxQ0_Debug
    17.3.4 MTL_TxQ0_ETS_Status
    17.3.5 MTL_TxQ0_Quantum_Weight
    17.3.6 MTL_Q0_Interrupt_Control_Status
    17.3.7 MTL_RxQ0_Operation_Mode
    17.3.8 MTL_RxQ0_Missed_Packet_Overflow_Cnt
    17.3.9 MTL_RxQ0_Debug
    17.3.10 MTL_RxQ0_Control
    17.4 EQOS_MTL_Q1 Registers
    17.4.1 MTL_TxQ(#i)_Operation_Mode (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.2 MTL_TxQ(#i)_Underflow (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.3 MTL_TxQ(#i)_Debug (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.4 MTL_TxQ(#i)_ETS_Control (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.5 MTL_TxQ(#i)_ETS_Status (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.6 MTL_TxQ(#i)_Quantum_Weight (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.7 MTL_TxQ(#i)_SendSlopeCredit (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.8 MTL_TxQ(#i)_HiCredit (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.9 MTL_TxQ(#i)_LoCredit (for i = 1; i <= DWC_EQOS_NUM_TXQ-1)
    17.4.10 MTL_Q(#i)_Interrupt_Control_Status) (for i = 1; i <= max(DWC_EQOS_NUM_TXQ-1,DWC_EQOS_NUM_RXQ-1))
    17.4.11 MTL_RxQ(#i)_Operation_Mode (for i = 1; i <= DWC_EQOS_NUM_RXQ-1)
    17.4.12 MTL_RxQ(#i)_Missed_Packet_Overflow_Cnt (for i = 1; i <= DWC_EQOS_NUM_RXQ-1)
    17.4.13 MTL_RxQ(#i)_Debug (for i = 1; i <= DWC_EQOS_NUM_RXQ-1)
    17.4.14 MTL_RxQ(#i)_Control (for i = 1; i <= DWC_EQOS_NUM_RXQ-1)
    17.5 EQOS_DMA Registers
    17.5.1 DMA_Mode
    17.5.2 DMA_SysBus_Mode
    17.5.3 DMA_Interrupt_Status
    17.5.4 DMA_Debug_Status0
    17.5.5 DMA_Debug_Status1
    17.5.6 DMA_Debug_Status2
    17.5.7 AXI4_Tx_AR_ACE_Control
    17.5.8 AXI4_Rx_AW_ACE_Control
    17.5.9 AXI4_TxRx_AWAR_ACE_Control
    17.5.10 AXI_LPI_Entry_Interval
    17.5.11 DMA_TBS_CTRL
    17.5.12 DMA_Safety_Interrupt_Status
    17.5.13 DMA_ECC_Interrupt_enable
    17.5.14 DMA_ECC_Interrupt_Status
    17.6 EQOS_DMA_CH0 Registers
    17.6.1 DMA_CH(#i)_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_CSR_CH-1)
    17.6.2 DMA_CH(#i)_Tx_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.3 DMA_CH(#i)_Rx_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.4 DMA_CH(#i)_TxDesc_List_HAddress (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.5 DMA_CH(#i)_TxDesc_List_Address (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.6 DMA_CH(#i)_RxDesc_List_HAddress (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.7 DMA_CH(#i)_RxDesc_List_Address (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.8 DMA_CH(#i)_TxDesc_Tail_Pointer (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.9 DMA_CH(#i)_RxDesc_Tail_Pointer (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.10 DMA_CH(#i)_TxDesc_Ring_Length (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.11 DMA_CH(#i)_RxDesc_Ring_Length (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.12 DMA_CH(#i)_Interrupt_Enable (for i = 0; i <= DWC_EQOS_NUM_DMA_CSR_CH-1)
    17.6.13 DMA_CH(#i)_Rx_Interrupt_Watchdog_Timer (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.14 DMA_CH(#i)_Slot_Function_Control_Status (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.15 DMA_CH(#i)_Current_App_TxDesc (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.16 DMA_CH(#i)_Current_App_RxDesc (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.17 DMA_CH(#i)_Current_App_TxBuffer_H (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.18 DMA_CH(#i)_Current_App_TxBuffer (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
    17.6.19 DMA_CH(#i)_Current_App_RxBuffer_H (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.20 DMA_CH(#i)_Current_App_RxBuffer (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.21 DMA_CH(#i)_Status (for i = 0; i <= DWC_EQOS_NUM_DMA_CSR_CH-1)
    17.6.22 DMA_CH(#i)_Miss_Frame_Cnt (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.23 DMA_CH(#i)_RXP_Accept_Cnt (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    17.6.24 DMA_CH(#i)_RX_ERI_Cnt (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
    18 Internal Parameter Descriptions
    19 Descriptors
    19.1 Overview
    19.2 Descriptor Structure
    19.3 Descriptor Structure for Split Header Support
    19.4 Descriptor Endianness
    19.5 Transmit Descriptor
    19.5.1 Transmit Normal Descriptor (Read Format)
    19.5.1.1 TDES0 Normal Descriptor (Read Format)
    19.5.1.2 TDES1 Normal Descriptor (Read Format)
    19.5.1.3 TDES2 Normal Descriptor (Read Format)
    19.5.1.4 TDES3 Normal Descriptor (Read Format)
    19.5.1.5 Transmit Normal Descriptor (Write-Back Format)
    19.5.1.6 TDES0 Normal Descriptor (Write-Back Format)
    19.5.1.7 TDES1 Normal Descriptor (Write-Back Format)
    19.5.1.8 TDES2 Normal Descriptor (Write-Back Format)
    19.5.1.9 TDES3 Normal Descriptor (Write-Back Format)
    19.5.2 Transmit Context Descriptor
    19.5.2.1 TDES0 Context Descriptor
    19.5.2.2 TDES1 Context Descriptor
    19.5.2.3 TDES2 Context Descriptor
    19.5.2.4 TDES3 Context Descriptor
    19.6 Receive Descriptor
    19.6.1 Receive Normal Descriptor (Read Format)
    19.6.1.1 RDES0 Normal Descriptor (Read Format)
    19.6.1.2 RDES1 Normal Descriptor (Read Format)
    19.6.1.3 RDES2 Normal Descriptor (Read Format)
    19.6.1.4 RDES3 Normal Descriptor (Read Format)
    19.6.2 Receive Normal Descriptor (Write-Back Format)
    19.6.2.1 RDES0 Normal Descriptor (Write-Back Format)
    19.6.2.2 RDES1 Normal Descriptor (Write-Back Format)
    19.6.2.3 RDES2 Normal Descriptor (Write-Back Format)
    19.6.2.4 RDES3 Normal Descriptor (Write-Back Format)
    19.6.3 Receive Context Descriptor
    19.6.3.1 RDES0 Context Descriptor
    19.6.3.2 RDES1 Context Descriptor
    19.6.3.3 RDES2 Context Descriptor
    19.6.3.4 RDES3 Context Descriptor
    19.7 Enhanced Descriptor for Time-Based Scheduling
    19.7.1 Enhanced Normal Descriptor - Read (32-Bit Mode)
    19.7.2 Enhanced Normal Descriptor (Write, 32-Bit Mode)
    19.7.3 Enhanced Context Descriptor (Read, 32-bit Mode)
    19.7.4 Enhanced Context Descriptor (Write, 32 Bit Mode)
    20 Programming
    20.1 Initializing DMA
    20.2 Initializing MTL Registers
    20.3 Initializing MAC
    20.4 Performing Normal Receive and Transmit Operation
    20.5 Stopping and Starting Transmission
    20.6 Programming Guidelines for Switching to New Descriptor List in RxDMA
    20.7 Programming Guidelines for Switching the AHB or AXI Clock Frequency
    20.8 Programming Guidelines for Multi-Channel Multi-Queuing
    20.8.1 Transmit
    20.8.2 Receive
    20.8.3 Programming Guidelines for Recovering from DMA Channel Failure
    20.8.3.1 Recovering from the Receive DMA Channel Failure
    20.8.3.2 Recovering from the Transmit DMA Channel Failure
    20.9 Programming Guidelines for GMII Link State Transitions
    20.9.1 Transmit and Receive Clocks Running when Link Down
    20.9.2 Transmit and Receive Clocks Stopped when Link Down
    20.10 Programming Guidelines for IEEE 1588 Timestamping
    20.10.1 Initialization Guidelines for System Time Generation
    20.10.2 System Time Correction
    20.10.2.1 Coarse Correction Method
    20.10.2.2 Fine Correction Method
    20.11 Programming Guidelines for AV Feature
    20.11.1 Initializing the DMA in Audio Video Feature
    20.11.2 Enabling Slot Number Checking
    20.11.3 Enabling Average Bits Per Slot Reporting
    20.11.4 Disabling Flow Control for AV Enabled Queues
    20.11.4.1 Transmit Flow
    20.11.4.2 Receive Flow Control
    20.12 Programming Guidelines for Energy Efficient Ethernet
    20.12.1 Entering and Exiting the Tx LPI Mode
    20.12.2 Gating Off the CSR Clock in the LPI Mode
    20.12.2.1 Gating Off the CSR Clock in the Rx LPI Mode
    20.12.2.2 Gating Off the CSR Clock in the Tx LPI Mode
    20.13 Programming Guidelines for Flexible Pulse-Per-Second Output
    20.13.1 Generating Single Pulse on PPS
    20.13.2 Generating Next Pulse on PPS
    20.13.3 Generating a Pulse Train on PPS
    20.13.4 Generating an Interrupt without Affecting the PPS
    20.14 Programming Guidelines for TSO
    20.15 Programming Guidelines for UFO
    20.15.1 Software Guidelines
    20.16 Programming Guidelines for Header Payload Split Receive
    20.17 Programming Guidelines for VLAN Filtering on Receive
    20.18 Programming Guidelines for Extended VLAN Filtering and Routing on Receive
    20.19 Programming Sequence for Queue/Channel Based VLAN Inclusion Register
    20.20 Programming Guidelines for EST
    20.20.1 Programming the GCL and GCL Linked Registers
    20.20.2 Programming the EST Registers
    20.21 Programming the Launch Time in Time-Based Scheduling
    20.22 Programming Guidelines for Media Clock Generation and Recovery
    20.22.1 Programming Guidelines for Media Clock Generation
    20.22.2 Programming Guidelines for Media Clock Recovery
    20.23 Programming Guidelines for ECC Protection for Memories
    20.23.1 Programming Guidelines for ECC Hardware Error Injection (Debug Mode)
    20.24 Programming Guidelines for On-Chip Datapath Parity Protection
    20.25 Programming Guidelines for FSM Parity and Timeout
    A Area and Power
    A.1 Area
    A.1.1 Gate Count Summary
    A.2 Power and Area Differences Due to Scan Ready, Clock Gating, and Low Power Mode
    B Endian Support
    B.1 Introduction
    B.1.1 Little-Endian Mode
    B.1.2 Big-Endian Mode
    B.1.3 Byte-Invariant Big-Endian Mode
    B.2 32-bit Data Bus Transfers
    B.2.1 Master Interface
    B.2.1.1 Little-Endian Data Transfer
    B.2.1.2 Conventional Big-Endian/ Byte-Invariant Big-Endian Data Transfer
    B.2.2 Slave Interface
    B.2.2.1 Little-Endian Data Transfer
    B.2.2.2 Conventional Big-Endian Data Transfer
    B.2.2.3 Byte-Invariant Big-Endian Data Transfer
    B.3 64-bit Data Bus Transfers
    B.3.1 Master Interface
    B.3.1.1 Little-Endian Data Transfer
    B.3.1.2 Conventional Big-Endian/ Byte-Invariant Big-Endian Data Transfer
    B.3.2 Slave Interface
    B.3.2.1 Little-Endian Data Transfer
    B.3.2.2 Conventional Big-Endian Data Transfer
    B.3.2.3 Byte-Invariant Big-Endian Data Transfer
    B.4 128-bit Data Bus Transfers
    B.4.1 Master Interface
    B.4.1.1 Little-Endian Data Transfer
    B.4.1.2 Conventional Big-Endian/ Byte-Invariant Big-Endian Data Transfer
    B.4.2 Slave Interface
    B.4.2.1 Little-Endian Data Transfer
    B.4.2.2 Conventional Big-Endian Data Transfer
    B.4.2.3 Byte-Invariant Big-Endian Data Transfer
    C Back-to-Back Register Support
    D DWC_ether_qos Automotive Safety
    D.1 Overview of Automotive Safety Features
    D.2 Automotive Safety Package Documents
    D.3 Configuring the Automotive Safety Features
    DesignWare Cores Ethernet Quality-of-Service Databook DWC-ETHERNET-QOS-SRC - Product Code: 6842-0 DWC-Ether-QOS-TSN1 Add-On - Product Code: C432-0 DWC-ETHERNET-QOS-TSN2 Add-On - Product Code: C433-0 DWC-Ethernet-QOS-ASP - Product Code: C118-0 Version 5.10a December 2017
    Ethernet Quality-of-Service Databook Copyright Notice and Proprietary Information © 2017 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at http://www.synopsys.com/Company/Pages/Trademarks.aspx. All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 690 E. Middlefield Road Mountain View, CA 94043 www.synopsys.com 2 SolvNet DesignWare.com Synopsys, Inc. Version 5.10a December 2017
    Ethernet Quality-of-Service Databook Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Chapter 1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.2 DWC_ether_qos Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.3 DWC_ether_qos Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 1.4 DWC_ether_qos Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 1.5 Related Synopsys Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Chapter 2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.1 CSR Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.2 Application Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.3 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.4 MAC Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 2.5 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Chapter 3 VLAN and Double VLAN Insertion, Deletion, Replacement and Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 3.1 Double VLAN Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 3.2 Source Address and VLAN Insertion, Replacement, or Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 3.3 Queue/Channel Based VLAN Tag Insertion on Tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Chapter 4 Managing Buffers and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 4.1 Introduction to Transmit and Receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4.2 Description of Transmit and Receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4.3 Transmit and Receive FIFO-Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4.4 Configuring Transmit and Receive FIFO Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4.5 TCP/IP Header Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 4.6 Accessing Memory In Slave/Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 Chapter 5 Using PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 5.1 Station Management Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 5.10a December 2017 Synopsys, Inc. SolvNet DesignWare.com 3
    Ethernet Quality-of-Service Databook 5.2 Physical Coding Sub-Layer (PCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 5.3 Reduced Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 5.4 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 5.5 Serial Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 5.6 Reverse Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 5.7 Serial Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 5.8 Reduced Ten-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 5.9 Multiple PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Chapter 6 Packet Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 6.1 Packet Filtering Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 6.2 Source Address or Destination Address Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 6.3 VLAN Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 6.4 VLAN Filter Fail Packets Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 6.5 Extended Receive VLAN Filtering and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 6.6 Layer 3 and Layer 4 Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 6.7 Flexible Receive Parser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Chapter 7 IEEE 1588 Timestamp Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 7.1 IEEE 1588 Timestamp Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 7.2 IEEE 1588 System Time Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 7.3 Programming Guidelines for IEEE 1588 Timestamping (For Internal Timestamp Source Configuration) 261 7.4 IEEE 1588 Higher Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 7.5 IEEE 1588 Auxillary Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 7.6 Flexible Pulse-Per-Second Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 7.7 Media Clock Generation and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 7.8 PTP Timestamp Offload Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 7.9 One-Step Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 7.10 One-Step Time Stamping for PTP Over UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 7.11 IEEE 1588 Sub Nanoseconds Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Chapter 8 Multiple Channels and Queues Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 8.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 8.2 Multiple Queues and Channels Support in the Transmit Path (for EQOS-AHB, EQOS-AXI, and EQOS-DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 8.3 Multiple Queues and Channels Support in the Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 8.4 Multiple Queues and Channels Support in EQOS-MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 8.5 Rx Queue to DMA Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 8.6 Selection of Tag Priorities Assigned to Tx and Rx Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 8.7 Rx Side Routing from MAC to Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 8.8 Rx Side Arbitration Between DMA and MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 8.9 Tx Side Arbitration between DMA and MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 8.10 Data Centre Bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 8.11 Audio Video Bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 8.12 Queue Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 4 SolvNet DesignWare.com Synopsys, Inc. 5.10a December 2017
    Ethernet Quality-of-Service Databook 8.13 Queue Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 8.14 Enhancements to Scheduled Traffic (EST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 8.15 Frame Preemption (FPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319 8.16 Time-Based Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 Chapter 9 TCP/IP Offloading Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 9.1 Transmit Checksum Offload Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 9.2 Receive Checksum Offload Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344 9.3 Header-Payload Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 9.4 TCP/IP Segmentation Offload (TSO) Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350 9.5 UDP/IPv4 Fragment Offload (UFO) Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 9.6 Using the IPv4 ARP Offload Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 Chapter 10 Power Management and Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 10.1 Overview of Low-Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 10.2 Description of Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 10.3 Description of Remote Wakeup Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 10.4 Design Partitioning for Low-Power Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 10.5 Remote Wake-Up Packet Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 10.6 PMT Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 10.7 Enabling PMT through Remote Wake-Up Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 10.8 Enabling PMT through Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 10.9 Power-Down and Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375 10.10 Description of Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 Chapter 11 MAC Management Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 11.1 MAC Management Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 11.2 Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 11.3 Enabling MAC Management Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 Chapter 12 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 12.1 Transmit Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 12.2 Receive Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 Chapter 13 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 13.1 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 Chapter 14 Automotive Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 14.1 Error Correction Code (ECC) Protection for Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398 14.2 On-Chip Data Path Parity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 14.3 FSM Parity and Timeout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412 14.4 Application/CSR Interface Timeout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 5.10a December 2017 Synopsys, Inc. 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    Ethernet Quality-of-Service Databook Chapter 15 Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 15.1 Features / Application Interface Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 15.2 Features / General Features Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 15.3 Features / General Features / CDC Synchronization Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 15.4 Features / Buffer Management Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 15.5 Features / PHY Interface Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 15.6 Features / Filtering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 15.7 Features / Multiple Queues Support Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 15.8 Features / IEEE 1588 Timestamp Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .439 15.9 Features / Time Sensitive Networking Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 15.10 Features / Time Based Scheduling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 15.11 Features / TCP/IP Offloading Features Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443 15.12 Features / Low Power Management Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446 15.13 Features / RMON Counters Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 15.14 Features / RMON Counters / RMON Transmit Counters Parameters . . . . . . . . . . . . . . . . . . . . . . . . .448 15.15 Features / RMON Counters / RMON Receive Counters Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .455 15.16 Features / RMON Counters / RMON IPC Receive Counters Parameters . . . . . . . . . . . . . . . . . . . . . .462 15.17 Features / Automotive Safety features Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468 Chapter 16 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471 16.1 MII Clocks and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473 16.2 MAC Control Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .475 16.3 MAC Application Clock and Reset Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479 16.4 SGMII/TBI/RTBI/SMII Clocks and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481 16.5 RMII Clocks and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483 16.6 RGMII/RTBI Clocks and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484 16.7 TBI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486 16.8 RevMII Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488 16.9 IEEE 1588 Timestamp Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .492 16.10 Sideband Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495 16.11 TBI/SGMII/RTBI/SMII PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .499 16.12 General Purpose Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501 16.13 Test Mode Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .502 16.14 Energy Efficient Ethernet Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503 16.15 Power Management Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504 16.16 PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506 16.17 SMA Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513 16.18 APB Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .515 16.19 AXI Master Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519 16.20 AXI Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531 16.21 AXI Low Power Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 16.22 AHB Master Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .543 16.23 AHB Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547 16.24 MDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551 16.25 TSO Memory Interface (TMI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 16.26 Application Transmit Interface (ATI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 16.27 Application Receive Interface (ARI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .565 6 SolvNet DesignWare.com Synopsys, Inc. 5.10a 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    Ethernet Quality-of-Service Databook 16.28 Rx Parser Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .571 16.29 DPRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573 16.30 SPRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579 16.31 MAC Tx Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588 16.32 MAC Rx Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597 16.33 EST Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600 16.34 Debug Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602 Chapter 17 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605 17.1 EQOS_MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626 17.2 EQOS_MTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1080 17.3 EQOS_MTL_Q0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1164 17.4 EQOS_MTL_Q1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1188 17.5 EQOS_DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1218 17.6 EQOS_DMA_CH0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1261 Chapter 18 Internal Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1307 Chapter 19 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1315 19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1316 19.2 Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1317 19.3 Descriptor Structure for Split Header Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1319 19.4 Descriptor Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1321 19.5 Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1323 19.6 Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1337 19.7 Enhanced Descriptor for Time-Based Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1350 Chapter 20 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1355 20.1 Initializing DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1357 20.2 Initializing MTL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1359 20.3 Initializing MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1360 20.4 Performing Normal Receive and Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1361 20.5 Stopping and Starting Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1362 20.6 Programming Guidelines for Switching to New Descriptor List in RxDMA . . . . . . . . . . . . . . . . . . . .1363 20.7 Programming Guidelines for Switching the AHB or AXI Clock Frequency . . . . . . . . . . . . . . . . . . . . .1363 20.8 Programming Guidelines for Multi-Channel Multi-Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1364 20.9 Programming Guidelines for GMII Link State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1366 20.10 Programming Guidelines for IEEE 1588 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1367 20.11 Programming Guidelines for AV Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1369 20.12 Programming Guidelines for Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1372 20.13 Programming Guidelines for Flexible Pulse-Per-Second Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1374 20.14 Programming Guidelines for TSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1376 20.15 Programming Guidelines for UFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1377 20.16 Programming Guidelines for Header Payload Split Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1378 20.17 Programming Guidelines for VLAN Filtering on Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1378 5.10a December 2017 Synopsys, Inc. SolvNet DesignWare.com 7
    Ethernet Quality-of-Service Databook 20.18 Programming Guidelines for Extended VLAN Filtering and Routing on Receive . . . . . . . . . . . . . .1379 20.19 Programming Sequence for Queue/Channel Based VLAN Inclusion Register . . . . . . . . . . . . . . . . .1379 20.20 Programming Guidelines for EST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1380 20.21 Programming the Launch Time in Time-Based Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1382 20.22 Programming Guidelines for Media Clock Generation and Recovery . . . . . . . . . . . . . . . . . . . . . . . .1383 20.23 Programming Guidelines for ECC Protection for Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1384 20.24 Programming Guidelines for On-Chip Datapath Parity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . .1385 20.25 Programming Guidelines for FSM Parity and Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1386 Chapter A Area and Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1387 A.1 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1388 A.2 Power and Area Differences Due to Scan Ready, Clock Gating, and Low Power Mode . . . . . . . . . . .1395 Chapter B Endian Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1397 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1398 B.2 32-bit Data Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1399 B.3 64-bit Data Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1402 B.4 128-bit Data Bus Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1406 Chapter C Back-to-Back Register Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1413 Chapter D DWC_ether_qos Automotive Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1415 D.1 Overview of Automotive Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1416 D.2 Automotive Safety Package Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1417 D.3 Configuring the Automotive Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1418 8 SolvNet DesignWare.com Synopsys, Inc. 5.10a December 2017
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