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Coagent_Enterprise_Limited__SiI-PR-1066-B-9293.pdf
Programmer’s Reference
SiI9293 MHL/HDMI Receiver
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
Programmer’s Reference
Document # SiI-PR-1066-B
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
June 2013
Copyright Notice
Silicon Image, Inc.
Copyright © 2012-2013 Silicon Image, Inc. All rights reserved. The contents of these materials contain proprietary and
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UltraGig™ are trademarks or registered trademarks of Silicon Image, Inc. in the United States or other countries.
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Silicon Image Confidential for
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Internal Use Only
Date
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Further Information
Revision History
Revision
A
B
3/2013
6/2013
First production release.
Updated contents of CBUS Bus Status Register and CBUS Interrupt Status
Register 2.
© 2012-2013 Silicon Image, Inc. All rights reserved.
ii
© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
SiI-PR-1066-B
Silicon Image, Inc.
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
Table of Contents
Introduction .......................................................................................................................................................................... 1
Block Diagram .................................................................................................................................................................. 1
Register Map .................................................................................................................................................................... 1
Conventions ...................................................................................................................................................................... 3
Theory of Operation ......................................................................................................................................................... 3
DDC-accessible Registers .................................................................................................................................................... 5
Device Identification Register (SiI9293) .......................................................................................................................... 5
HDCP Registers ................................................................................................................................................................ 5
HDCP BKSV Register .................................................................................................................................................. 5
HDCP Ri Register ......................................................................................................................................................... 6
HDCP AKSV Register ................................................................................................................................................. 6
HDCP AN Register ...................................................................................................................................................... 6
BCAPS Register ........................................................................................................................................................... 7
BSTATUS Register ...................................................................................................................................................... 7
HDCP Repeater Registers................................................................................................................................................. 8
V.H Registers ............................................................................................................................................................... 8
KSV FIFO Register ...................................................................................................................................................... 8
Sink-accessible Registers...................................................................................................................................................... 9
ID and System Initialization Registers ............................................................................................................................. 9
ID Register (SiI9293) ................................................................................................................................................... 9
Software Reset Register .............................................................................................................................................. 10
System Status Register ............................................................................................................................................... 11
Software Reset Register 2 ........................................................................................................................................... 11
System Control Register 1 .......................................................................................................................................... 12
SYS Switch Configuration Register ........................................................................................................................... 12
SYSPCLK Stop Register ............................................................................................................................................ 13
Hot Plug Control Register .......................................................................................................................................... 13
KSV FIFO Control Register ....................................................................................................................................... 14
SYS TMDS CH Map .................................................................................................................................................. 14
PCLK Auto Stop Register .......................................................................................................................................... 15
Slave Address Mapping Registers .................................................................................................................................. 15
Page 7 Slave Address Register ................................................................................................................................... 15
Page 2 Slave Address Register ................................................................................................................................... 15
Page 4 Slave Address Register ................................................................................................................................... 15
Page 1 Slave Address Register ................................................................................................................................... 16
Page CEC Slave Address Register.............................................................................................................................. 16
Page CBUS Slave Address Register ........................................................................................................................... 16
Page 9 Slave Address Register ................................................................................................................................... 16
Page 5 Slave Address Register ................................................................................................................................... 16
Page 6 Slave Address Register ................................................................................................................................... 17
HDCP Registers .............................................................................................................................................................. 17
HDCP Shadow BKSV Registers ................................................................................................................................ 17
HDCP Shadow Ri Registers ....................................................................................................................................... 17
HDCP Shadow AKSV Registers ................................................................................................................................ 18
HDCP Shadow AN Registers ..................................................................................................................................... 18
HDCP BCAPS_SET Register..................................................................................................................................... 19
HDCP BSTATUS_SET Register 1............................................................................................................................. 19
HDCP BSTATUS_SET Register 2............................................................................................................................. 19
HDCP Debug Register ................................................................................................................................................ 20
HDCP Status Register ................................................................................................................................................ 20
HDCP KSV/SHA Start Register ................................................................................................................................. 21
HDCP SHA Length Register ...................................................................................................................................... 21
HDCP SHA Control Register ..................................................................................................................................... 21
HDCP Repeater KSV FIFO Register.......................................................................................................................... 22
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
SiI-PR-1066-B
© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
iii
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
Silicon Image, Inc.
Video Input Registers ..................................................................................................................................................... 22
Video H Resolution Registers ..................................................................................................................................... 22
Video V Refresh Registers ......................................................................................................................................... 22
Video DE Pixels Registers .......................................................................................................................................... 22
Video DE Line Registers ............................................................................................................................................ 23
Video VSYNC to Active Video Lines Register .......................................................................................................... 23
Video Vertical Front Porch Register ........................................................................................................................... 23
Video Status Register ................................................................................................................................................. 23
Video Horizontal Front Porch Registers ..................................................................................................................... 24
Video Hsync Active Width Registers ......................................................................................................................... 24
Video Pixel Clock Timing Registers .......................................................................................................................... 24
Video Channel PCLK Count Multiplication Register ................................................................................................ 25
Video Channel PCLK Count Base Register ............................................................................................................... 25
Video Channel 0 XCLK To PCLK Update Register .................................................................................................. 25
Video Channel 0 Pixel Clock Count Base Registers .................................................................................................. 26
Video Channel 0 Pixel Clock Count Threshold Register ............................................................................................ 26
Video Processing Registers ............................................................................................................................................ 26
Video Control Register ............................................................................................................................................... 26
Video Mode 2 Register ............................................................................................................................................... 27
Video Mode 1 Register ............................................................................................................................................... 28
Video Digital Blank Value Registers .......................................................................................................................... 28
Video Field 2 Back Porch Mode Register .................................................................................................................. 29
Video Channel Map Register ...................................................................................................................................... 29
Video Control 2 Register ............................................................................................................................................ 30
General Control Packet Header Register .................................................................................................................... 30
General Control Packet Phase LUT Register .............................................................................................................. 30
Auto Video Configuration Registers .............................................................................................................................. 31
Auto Output Format Register ..................................................................................................................................... 31
Interrupt Registers .......................................................................................................................................................... 31
Interrupt State Register ............................................................................................................................................... 31
Interrupt Status 1 Register .......................................................................................................................................... 32
Interrupt Status 2 Register .......................................................................................................................................... 33
Interrupt Status 3 Register .......................................................................................................................................... 34
Interrupt Status 4 Register .......................................................................................................................................... 35
Interrupt 1 Mask Register ........................................................................................................................................... 36
Interrupt 2 Mask Register ........................................................................................................................................... 37
Interrupt 3 Mask Register ........................................................................................................................................... 38
Interrupt 4 Mask Register ........................................................................................................................................... 39
Interrupt Control Register ........................................................................................................................................... 39
Interrupt Packet Control Register ............................................................................................................................... 40
Interrupt Status 5 Register .......................................................................................................................................... 41
Interrupt Status 6 Register .......................................................................................................................................... 41
Interrupt 5 Mask Register ........................................................................................................................................... 42
Interrupt 6 Mask Register ........................................................................................................................................... 43
Interrupt Status 7 Register .......................................................................................................................................... 44
Interrupt Status 8 Register .......................................................................................................................................... 44
Interrupt 7 Mask Register ........................................................................................................................................... 45
Interrupt 8 Mask Register ........................................................................................................................................... 45
Interrupt State 2 Register ............................................................................................................................................ 45
Analog Core Registers .................................................................................................................................................... 45
TMDS Termination Control Register ......................................................................................................................... 46
Auto Audio and Video Control ....................................................................................................................................... 47
Auto Audio and Video Control Register .................................................................................................................... 47
AAC Control Register ................................................................................................................................................ 48
Auto Audio Control (AAC) Registers ............................................................................................................................ 49
Audio Exception Enable Registers ............................................................................................................................. 49
AVC Enable Registers ................................................................................................................................................ 50
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
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© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
SiI-PR-1066-B
Silicon Image, Inc.
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
ECC Control Registers ................................................................................................................................................... 51
ECC Control Register ................................................................................................................................................. 51
ECC BCH Threshold Register .................................................................................................................................... 51
ECC T4 Corrected Threshold Register ....................................................................................................................... 51
ECC T4 Uncorrected Threshold Register ................................................................................................................... 51
ECC Error Threshold and Count Registers ................................................................................................................. 52
HDCP Repeater Registers............................................................................................................................................... 53
SHA Control 2 Register .............................................................................................................................................. 53
V Value Ready Status Register ................................................................................................................................... 53
KSV Source Select Register ....................................................................................................................................... 53
EDID Control Register ............................................................................................................................................... 53
Downstream BSTATUS 1 Register ............................................................................................................................ 53
Downstream BSTATUS 2 Register ............................................................................................................................ 54
Downstream M0 Registers ......................................................................................................................................... 54
Downstream VH Registers ......................................................................................................................................... 55
Extended Color Gamut Registers ................................................................................................................................... 55
xvYCC Control Register ............................................................................................................................................ 55
RGB to xvYCC Coefficient Registers ........................................................................................................................ 56
xvYCC Control Register 2.......................................................................................................................................... 56
xvYCC Y2RGB Coefficient Register ......................................................................................................................... 56
xvYCC Cr2R Coefficient Register ............................................................................................................................. 57
xvYCC Cb2B Coefficient Register ............................................................................................................................ 57
xvYCC Cr2G Coefficient Register ............................................................................................................................. 57
xvYCC Cb2G Coefficient Register ............................................................................................................................ 57
xvYCC Y Offset Register ........................................................................................................................................... 58
xvYCC Offset1 Register ............................................................................................................................................. 58
xvYCC Offset2 Register ............................................................................................................................................. 58
xvYCC DC-level Register .......................................................................................................................................... 58
AVC Enable Register 3 .............................................................................................................................................. 59
xvYCC Red Min Range Register ............................................................................................................................... 59
xvYCC Red Max Range Register ............................................................................................................................... 59
xvYCC Green Min Range Register ............................................................................................................................ 59
xvYCC Green Max Range Register............................................................................................................................ 60
xvYCC Blue Min Range Register .............................................................................................................................. 60
xvYCC Blue Max Range Register .............................................................................................................................. 60
xvYCC Reverse Binary Offset Enable Register ......................................................................................................... 61
GBD Packet Registers ................................................................................................................................................ 62
Audio Clock Recovery (ACR) Registers ........................................................................................................................ 63
ACR Control Register 1 ............................................................................................................................................. 63
ACR MCLK Select Register ...................................................................................................................................... 64
ACR Audio Frequency Register ................................................................................................................................. 64
ACR N Value Registers .............................................................................................................................................. 65
ACR CTS Value Registers ......................................................................................................................................... 65
ACR UPLL Divider Value Registers.......................................................................................................................... 65
ACR Post Divider Value Registers ............................................................................................................................. 66
ACR PLL Lock Window Register .............................................................................................................................. 66
ACR PLL Lock Threshold Registers .......................................................................................................................... 66
ACR Hardware Extracted Fs Register ........................................................................................................................ 67
ACR Control 3 Register ............................................................................................................................................. 67
ACR Configuration Registers ..................................................................................................................................... 68
Audio Output Formatting Registers ................................................................................................................................ 68
Audio Out I2S Control Register 1 ............................................................................................................................... 68
Audio Out I2S Control Register 2 ............................................................................................................................... 69
Audio Out I2S Map Register ....................................................................................................................................... 69
Audio Out Control Register ........................................................................................................................................ 70
Audio Out SPDIF Channel Status 1 Register ............................................................................................................. 71
Audio Out SPDIF Channel Status 2 Register ............................................................................................................. 71
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
SiI-PR-1066-B
© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
v
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
Silicon Image, Inc.
Audio Out SPDIF Channel Status 3 Register ............................................................................................................. 71
RX TDM Control Register 1 ...................................................................................................................................... 72
RX TDM Control Register 2 ...................................................................................................................................... 72
Audio Out Soft Mute Divider Register ....................................................................................................................... 73
Audio Swap and Overwrite Register .......................................................................................................................... 73
Audio CHST5 Overwrite Register .............................................................................................................................. 73
Audio Out S/PDIF Channel Status 4 Register ............................................................................................................ 74
Audio Out S/PDIF Channel Status 5 Register ............................................................................................................ 74
Audio Out Channel Mute Register ............................................................................................................................. 75
HDMI Control and Status Registers ............................................................................................................................... 76
HDMI Audio Status Register ...................................................................................................................................... 76
HDMI Audio Preamble Criteria Register ................................................................................................................... 76
HDMI Audio Filter Register ....................................................................................................................................... 76
HDMI Audio MUTE Register .................................................................................................................................... 77
HDMI Audio HDCP Enable Criteria Register ............................................................................................................ 77
HDMI Audio FIFO Read/Write Pointer Difference Register ..................................................................................... 77
System Power Down Registers ....................................................................................................................................... 77
Power Down Total Register ........................................................................................................................................ 77
System Power Down 3 Register ................................................................................................................................. 78
System Power Down 2 Register ................................................................................................................................. 78
System Power Down Register .................................................................................................................................... 79
Packet Registers .............................................................................................................................................................. 79
AVI InfoFrame Registers............................................................................................................................................ 80
SPD InfoFrame Registers ........................................................................................................................................... 81
SPD Packet Type Decode Register ............................................................................................................................. 82
Audio InfoFrame Registers ......................................................................................................................................... 82
MPEG InfoFrame Registers ........................................................................................................................................ 83
MPEG Packet Type Decode Register ......................................................................................................................... 84
Audio Content Protection Packet Registers ................................................................................................................ 84
ACP Packet Type Decode Register ............................................................................................................................ 85
Unrecognized Packet Registers................................................................................................................................... 85
General Control Packet Registers ................................................................................................................................... 86
CP Packet Byte 1 Register .......................................................................................................................................... 86
General Purpose IO Control Registers ............................................................................................................................ 86
GPIO Output Enable Register ..................................................................................................................................... 86
GPIO Control Output Register ................................................................................................................................... 86
GPIO Control Input Register ...................................................................................................................................... 87
GPIO Mode Control Register ..................................................................................................................................... 87
Receiver Control Registers ............................................................................................................................................. 88
Receiver Control Register 1 ........................................................................................................................................ 88
Receiver Control Register 4 ........................................................................................................................................ 88
Receiver Control Register 5 ........................................................................................................................................ 89
MHL and CBUS Control Registers ................................................................................................................................ 89
MHL Sideband Channel ................................................................................................................................................. 90
MSC Commands Error Codes .................................................................................................................................... 91
Remote Control Protocol (RCP) ................................................................................................................................. 91
Request Action Protocol (RAP) .................................................................................................................................. 91
MHL/CBUS Programming ............................................................................................................................................. 92
CBUS Control Registers Register Group........................................................................................................................ 93
CBUS Bus Status Register .......................................................................................................................................... 93
CBUS DDC ABORT Reason Register ....................................................................................................................... 93
CBUS MHL Sideband Channel Transfer Abort Reason Register .............................................................................. 94
CBUS Follower Abort Reason Register ..................................................................................................................... 94
CBUS Start Command Register ................................................................................................................................. 94
CBUS Command and Offset Register ........................................................................................................................ 95
CBUS Write Data Registers ....................................................................................................................................... 95
CBUS Read Data Register .......................................................................................................................................... 95
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
vi
© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
SiI-PR-1066-B
Silicon Image, Inc.
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
CBUS MHL Sideband Channel Command Register .................................................................................................. 95
CBUS MHL Sideband Channel Data Register ........................................................................................................... 95
CBUS MHL Sideband Channel Write Burst Data Length Register ........................................................................... 95
CBUS Protocol Virtual Register Group.......................................................................................................................... 96
CBUS MHL Device Capability Registers .................................................................................................................. 96
CBUS MHL Interrupt Registers ................................................................................................................................. 96
CBUS MHL Status Registers ..................................................................................................................................... 97
CBUS MHL Scratchpad Registers ............................................................................................................................. 97
MHL Interrupt Enable and Status Register Group ......................................................................................................... 98
CBUS Interrupt Status Register 1 ............................................................................................................................... 98
CBUS Interrupt Status Register 2 ............................................................................................................................... 98
References ...................................................................................................................................................................... 99
Standards Documents ..................................................................................................................................................... 99
Silicon Image Documents ............................................................................................................................................... 99
Silicon Image Confidential for
Coagent Enterprise Limited
Internal Use Only
SiI-PR-1066-B
© 2012-2013 Silicon Image, Inc. All rights reserved.
CONFIDENTIAL
vii
SiI9293 MHL/HDMI Receiver
Programmer’s Reference
Silicon Image, Inc.
List of Figures
Figure 1. Typical SiI9293 HDMI/MHL Dual Mode Receiver User Case ............................................................................ 1
Figure 2. Top Flow Chart of the Starter Kit Firmware ......................................................................................................... 4
Figure 3. AEC Enable Control ............................................................................................................................................ 50
Figure 4. Sending an MHL MSC_MSG Command (RCP Subcommand) .......................................................................... 92
Figure 5. Sending an MHL SET_INT Command ............................................................................................................... 92
Figure 6. Sending an MHL SET_HPD Command .............................................................................................................. 92
Figure 7. Sending an WRITE_BURST Command ............................................................................................................. 93
Table 1. Register Address Groups ........................................................................................................................................ 2
Table 2. Control of Primary I2C Address with CI2CA Pin ................................................................................................... 2
Table 3. Conventions and Usage .......................................................................................................................................... 3
Table 4. MHL CBUS Register Sets Accessible by an MHL-capable Peer Device ............................................................. 90
Table 5. MSC Commands ................................................................................................................................................... 91
Table 6. Referenced Documents ......................................................................................................................................... 99
Table 7. Standards Groups Contact Information ................................................................................................................ 99
Table 8. Silicon Image Documents ..................................................................................................................................... 99
List of Tables
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CONFIDENTIAL
SiI-PR-1066-B
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