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Universal Serial Bus 3.0 Specification.pdf
USB3.0协议规范(英文完整版).pdf
Universal Serial Bus 3.0 Specification
Revision History
Acknowledgement of USB 3.0 Technical Contribution
Contents
1 Introduction
1.1 Motivation
1.2 Objective of the Specification
1.3 Scope of the Document
1.4 USB Product Compliance
1.5 Document Organization
1.6 Design Goals
1.7 Related Documents
2 Terms and Abbreviations
3 SuperSpeed USB Architectural Overview
3.1 USB 3.0 Overview
3.1.1 SuperSpeed Architecture Overview
3.1.1.1 Physical Layer
3.1.1.2 Link Layer
3.1.1.3 Protocol Layer
3.1.1.4 Hubs
3.1.1.5 Power Management
3.2 USB 3.0 System
3.2.1 Comparing SuperSpeed USB to USB 2.0
3.2.2 System Level Topology
3.2.2.1 Hosts
3.2.2.2 Hubs
3.2.2.3 Devices
3.2.3 Bus Protocol
3.2.4 Robustness
3.2.4.1 Error Detection
3.2.4.2 Error Handling
3.3 USB Specification Chapter Overview
3.3.1 Mechanical
3.3.2 Physical Layer
3.3.3 Link Layer
3.3.4 Protocol Layer
3.3.5 Framework Layer
3.3.6 Hubs
3.3.6.1 Hub Architecture
3.3.6.2 Hub Repeater/Forwarder Architecture
3.3.6.3 Hubs and Transfers to Power Managed Links
3.3.7 Performance and Power Efficiency
3.3.8 SuperSpeed Power Management
3.3.8.1 Link Power Management
3.3.8.2 Function and Device Power Management
3.3.8.3 Platform PM Support
4. SuperSpeed Data Flow Model
4.1 Implementer Viewpoints
4.2 SuperSpeed USB Communication Flow
4.2.1 Pipes
4.3 SuperSpeed USB Protocol Overview
4.3.1 Differences with USB 2.0
4.3.1.1 Comparing USB 2.0 and SuperSpeed USB Transactions
4.3.1.2 Comparing USB 2.0 and SuperSpeed USB Bus Topology
4.3.1.3 Introduction to SuperSpeed USB Packets
4.4 Generalized Transfer Description
4.4.1 Data Bursting
4.4.2 IN Transfers
4.4.3 OUT Transfers
4.4.4 Power Management and Performance
4.4.5 Control Transfers
4.4.5.1 Control Transfer Packet Size
4.4.5.2 Control Transfer Bandwidth Requirements
4.4.5.3 Control Transfer Data Sequences
4.4.6 Bulk Transfers
4.4.6.1 Bulk Transfer Packet Size
4.4.6.2 Bulk Transfer Bandwidth Requirements
4.4.6.3 Bulk Transfer Data Sequences
4.4.6.4 Bulk Streams
4.4.7 Interrupt Transfers
4.4.7.1 Interrupt Transfer Packet Size
4.4.7.2 Interrupt Transfer Bandwidth Requirements
4.4.7.3 Interrupt Transfer Data Sequences
4.4.8 Isochronous Transfers
4.4.8.1 Isochronous Transfer Packet Size
4.4.8.2 Isochronous Transfer Bandwidth Requirements
4.4.8.3 Isochronous Transfer Data Sequences
4.4.9 Device Notifications
4.4.10 Reliability
4.4.10.1 Physical Layer
4.4.10.2 Link Layer
4.4.10.3 Protocol Layer
4.4.11 Efficiency
5 Mechanical
5.1 Objective
5.2 Significant Features
5.2.1 Connectors
5.2.1.1 USB 3.0 Standard-A Connector
5.2.1.2 USB 3.0 Standard-B Connector
5.2.1.3 USB 3.0 Power-B Connector
5.2.1.4 USB 3.0 Micro-B Connector
5.2.1.5 USB 3.0 Micro-AB and USB 3.0 Micro-A Connectors
5.2.2 Compliant Cable Assemblies
5.2.3 Raw Cables
5.3 Connector Mating Interfaces
5.3.1 USB 3.0 Standard-A Connector
5.3.1.1 Interface Definition
5.3.1.2 Pin Assignments and Description
5.3.1.3 USB 3.0 Standard-A Connector Color Code
5.3.2 USB 3.0 Standard-B Connector
5.3.2.1 Interface Definition
5.3.2.2 Pin Assignments and Description
5.3.3 USB 3.0 Power-B Connector
5.3.3.1 Interface Definition
5.3.3.2 Pin Assignments and Descriptions
5.3.4 USB 3.0 Micro-B Connector Family
5.3.4.1 Interfaces Definition
5.3.4.2 Pin Assignments and Description
5.4 Cable Construction and Wire Assignments
5.4.1 Cable Construction
5.4.2 Wire Assignments
5.4.3 Wire Gauges and Cable Diameters
5.5 Cable Assemblies
5.5.1 USB 3.0 Standard-A to USB 3.0 Standard-B Cable Assembly
5.5.2 USB 3.0 Standard-A to USB 3.0 Micro-B Cable Assembly
5.5.3 USB 3.0 Micro-A to USB 3.0 Micro-B Cable Assembly
5.5.4 USB 3.0 Micro-A to USB 3.0 Standard-B Cable Assembly
5.5.5 Captive Cables
5.5.6 Cable Assembly Length
5.6 Electrical Requirements
5.6.1 High Speed Electrical Requirements
5.6.1.1 Raw Cable
5.6.1.2 Mated Connector
5.6.1.3 Mated Cable Assemblies
5.6.2 DC Electrical Requirements
5.6.2.1 Low Level Contact Resistance (EIA 364-23B)
5.6.2.2 Dielectric Strength (EIA 364-20, Method 301)
5.6.2.3 Insulation Resistance (EIA 364-21, Method 302)
5.6.2.4 Contact Current Rating (EIA 364- 70, Method 2)
5.7 Mechanical and Environmental Requirements
5.7.1 Mechanical Requirements
5.7.1.1 Insertion Force (EIA 364-13)
5.7.1.2 Extraction Force (EIA 364-13)
5.7.1.3 Durability or Insertion/Extraction Cycles (EIA 364-09)
5.7.1.4 Cable Flexing (EIA 364-41, Condition I)
5.7.1.5 Cable Pull-Out (EIA 364-38, Condition A)
5.7.1.6 Peel Strength (Micro-B Connector Family Only)
5.7.1.7 4-Axes Continuity Test (USB 3.0 Micro-B Connector Family Only)
5.7.1.8 Wrenching Strength (Reference, Micro-B Connector Family Only)
5.7.1.9 Lead Co-Planarity
5.7.1.10 Solderability
5.7.1.11 RoHS Compliance
5.7.2 Environmental Requirements
5.7.3 Materials
5.8 Implementation Notes and Design Guides
5.8.1 Mated Connector Dimensions
5.8.2 EMI Management
5.8.3 Stacked Connectors
5.8.4 Captive Cables
6 Physical Layer
6.1 Physical Layer Overview
6.2 Physical Layer Functions
6.2.1 Measurement Overview
6.2.2 Channel Overview
6.3 Symbol Encoding
6.3.1 Serialization and De-serialization of Data
6.3.2 Normative 8b/10b Decode Rules
6.3.3 Data Scrambling
6.3.4 8b/10b Decode Errors
6.3.5 Special Symbols for Framing and Link Management
6.4 Link Initialization and Training
6.4.1 Normative Training Sequence Rules
6.4.1.1 Training Control Bits
6.4.1.2 Training Sequence Values
6.4.2 Lane Polarity Inversion
6.4.3 Elasticity Buffer and SKP Ordered Set
6.4.4 Compliance Pattern
6.5 Clock and Jitter
6.5.1 Informative Jitter Budgeting
6.5.2 Normative Clock Recovery Function
6.5.3 Normative Spread Spectrum Clocking (SSC)
6.5.4 Normative Slew Rate Limit
6.6 Signaling
6.6.1 Eye Diagrams
6.6.2 Voltage Level Definitions
6.6.3 Tx and Rx Input Parasitics
6.7 Transmitter Specifications
6.7.1 Transmitter Electrical Parameters
6.7.2 Transmitter Eye
6.7.3 Tx Compliance Reference Receiver Equalize Function
6.7.4 Informative Transmitter De-emphasis
6.7.5 Entry into Electrical Idle, U1
6.8 Receiver Specifications
6.8.1 Receiver Equalization Training
6.8.2 Informative Receiver CTLE Function
6.8.3 Receiver Electrical Parameters
6.8.4 Receiver Loopback
6.7.4.1 Loopback BERT
6.8.5 Normative Receiver Tolerance Compliance Test
6.9 Low Frequency Periodic Signaling (LFPS)
6.9.1 LFPS Signal Definition
6.9.2 Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3 Wakeup
6.9.3 Example Warm Reset
6.10 Transmitter and Receiver DC Specifications
6.10.1 Informative ESD Protection
6.10.2 Informative Short Circuit Requirements
6.10.3 Normative High Impedance Reflections
6.11 Receiver Detection
6.11.1 Rx Detect Overview
6.11.2 Rx Detect Sequence
6.11.3 Upper Limit on Channel Capacitance
7 Link Layer
7.1 Link Management and Flow Control
7.1.1 Packets and Packet Framing
7.1.1.1 Header Packet Structure
7.1.1.2 Data Packet Payload Structure
7.1.2 Link Commands
7.1.2.1 Link Command Structure
7.1.2.2 Link Command Word Definition
7.1.2.3 Link Command Placement
7.1.3 Logical Idle
7.1.4 Link Command Usage for Flow Control, Error Recovery and Power Management
7.1.4.1 Header Packet Flow Control and Error Recovery
7.1.4.2 Link Power Management and Flow
7.2 Link Error Rules/Recovery
7.2.1 Overview of SuperSpeed Bit Errors
7.2.2 Link Error Types, Detection and Recovery
7.2.3 Packet Errors
7.2.3.1 Packet Framing Detection
7.2.3.2 Header Packet CRC or Length Error
7.2.3.3 Rx Header Sequence Number Error
7.2.3.4 ACK Tx Header Sequence Number Error
7.2.3.5 Header Sequence Number Advertisement Error
7.2.4 Training Sequence Error
7.2.5 Link Command Detection and Declarations
7.2.6 Summary of Error Types and Recovery
7.3 PowerOn Reset and Inband Reset
7.3.1 PowerOn Reset
7.3.2 Inband Reset
7.4 Link Training and Status State Machine (LTSSM)
7.4.1 SS.Disabled
7.4.2 SS.Inactive
7.4.2.1 SS.Inactive.Quiet
7.4.2.2 SS.Inactive.Disconnect.Detect
7.4.3 Rx.Detect
7.4.3.1 Rx.Detect.Reset
7.4.3.2 Rx.Detect.Active
7.4.3.3 Rx.Detect.Quiet
7.4.4 Polling
7.4.4.1 Polling.LFPS
7.4.4.2 Polling.RxEQ
7.4.4.3 Polling.Active
7.4.4.4 Polling.Configuration
7.4.4.5 Polling.Idle
7.4.5 Compliance Mode
7.4.6 U0
7.4.7 U1
7.4.8 U2
7.4.9 U3
7.4.10 Recovery
7.4.10.1 Recovery.Active
7.4.10.2 Recovery.Configuration
7.4.10.3 Recovery.Idle
7.4.11 Loopback
7.4.11.1 Loopback.Active
7.4.11.2 Loopback.Exit
7.4.12 Hot Reset
7.4.12.1 Hot Reset.Active
7.4.12.2 Hot Reset.Exit
8 Protocol Layer
8.1 USB 3.0 Transactions
8.2 Packet Types
8.3 Packet Formats
8.3.1 Fields Common to all Headers
8.3.1.1 Packet Revision Field
8.3.1.2 Packet Type Field
8.3.1.3 CRC-16
8.3.1.4 Link Control Word
8.4 Link Management Packet (LMP)
8.4.1 Subtype Field
8.4.2 Set Link Function
8.4.3 U2 Inactivity Timeout
8.4.4 Vendor Device Test
8.4.5 Port Capabilities
8.4.6 Port Configuration
8.4.7 Port Configuration ACK
8.5 Transaction Packet (TP)
8.5.1 ACK Transaction Packet
8.5.2 NRDY Transaction Packet
8.5.3 Endpoint Ready (ERDY) Transaction Packet
8.5.4 STATUS Transaction Packet
8.5.5 STALL Transaction Packet
8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet
8.5.6.1 Function Wake Device Notification
8.5.6.2 Latency Tolerance Messaging Device Notification
8.5.6.3 Bus Interval Adjustment Message Device Notification
8.5.6.4 Best Effort Latency Tolerance Messaging
8.5.6.5 Bus Interval Adjustment Messaging
8.5.7 PING Transaction Packet
8.5.8 PING_RESPONSE Transaction Packet
8.6 Data Packet (DP)
8.7 Isochronous Timestamp Packet (ITP)
8.8 Addressing Triple
8.9 Route String Field
8.9.1 Route String Port Field
8.9.2 Route String Port Field Width
8.9.3 Port Number
8.10 Transaction Packet Usages
8.10.1 Flow Control Conditions
8.10.2 Burst Transactions
8.10.3 Short Packets
8.11 TP Responses
8.11.1 Device Response to TP Requesting Data
8.11.2 Host Response to Data Received from a Device
8.11.3 Device Response to Data Received from the Host
8.11.4 Device Response to a SETUP DP
8.12 TP Sequences
8.12.1 Bulk Transactions
8.12.1.1 State Machine Notation Information
8.12.1.2 Bulk IN Transactions
8.12.1.3 Bulk OUT Transactions
8.12.1.4 Introduction to Bulk Streaming Protocol
8.12.2 Control Transfers
8.12.2.1 Reporting Status Results
8.12.2.2 Variable-length Data Stage
8.12.2.3 STALL TPs Returned by Control Pipes
8.12.3 Bus Interval and Service Interval
8.12.4 Interrupt Transactions
8.12.4.1 Interrupt IN Transactions
8.12.4.2 Interrupt OUT Transactions
8.12.5 Host Timing Information
8.12.6 Isochronous Transactions
8.12.6.1 Host Flexibility in Performing Isochronous Transactions
8.12.6.2 Device Response to Isochronous IN Transactions
8.12.6.3 Host Processing of Isochronous IN Transactions
8.12.6.4 Device Response to an Isochronous OUT Data Packet
8.13 Timing Parameters
9 Device Framework
9.1 USB Device States
9.1.1 Visible Device States
9.1.1.1 Attached
9.1.1.2 Powered
9.1.1.3 Default
9.1.1.4 Address
9.1.1.5 Configured
9.1.1.6 Suspended
9.1.2 Bus Enumeration
9.2 Generic USB Device Operations
9.2.1 Dynamic Attachment and Removal
9.2.2 Address Assignment
9.2.3 Configuration
9.2.4 Data Transfer
9.2.5 Power Management
9.2.5.1 Power Budgeting
9.2.5.2 Changing Device Suspend State
9.2.5.3 Function Suspend
9.2.5.4 Changing Function Suspend State
9.2.6 Request Processing
9.2.6.1 Request Processing Timing
9.2.6.2 Reset/Resume Recovery Time
9.2.6.3 Set Address Processing
9.2.6.4 Standard Device Requests
9.2.6.5 Class-specific Requests
9.2.6.6 Speed Dependent Descriptors
9.2.7 Request Error
9.3 USB Device Requests
9.3.1 bmRequestType
9.3.2 bRequest
9.3.3 wValue
9.3.4 wIndex
9.3.5 wLength
9.4 Standard Device Requests
9.4.1 Clear Feature
9.4.2 Get Configuration
9.4.3 Get Descriptor
9.4.4 Get Interface
9.4.5 Get Status
9.4.6 Set Address
9.4.7 Set Configuration
9.4.8 Set Descriptor
9.4.9 Set Feature
9.4.10 Set Interface
9.4.11 Set Isochronous Delay
9.4.12 Set SEL
9.4.13 Synch Frame
9.5 Descriptors
9.6 Standard USB Descriptor Definitions
9.6.1 Device
9.6.2 Binary Device Object Store (BOS)
9.6.2.1 USB 2.0 Extension
9.6.2.2 SuperSpeed USB Device Capability
9.6.3 Configuration
9.6.4 Interface Association
9.6.5 Interface
9.6.6 Endpoint
9.6.7 SuperSpeed Endpoint Companion
9.6.8 String
9.7 Device Class Definitions
9.7.1 Descriptors
9.7.2 Interface(s)
9.7.3 Requests
10 Hub, Host Downstream Port, and Device Upstream Port Specification
10.1 Hub Feature Summary
10.1.1 SuperSpeed Capable Host with SuperSpeed Capable Software
10.1.2 USB 2.0 Host
10.1.3 Hub Connectivity
10.1.3.1 Packet Signaling Connectivity
10.1.3.2 Routing Information
10.1.4 Resume Connectivity
10.1.5 Hub Fault Recovery Mechanisms
10.1.6 Hub Header Buffer Architecture
10.1.6.1 Hub Data Buffer Architecture
10.2 Hub Power Management
10.2.1 Link States
10.2.2 U1/U2 Timers
10.2.3 Downstream/Upstream Port Link State Transitions
10.3 Downstream Facing Ports
10.3.1 Downstream Facing Port State Descriptions
10.3.1.1 DSPORT.Powered-off
10.3.1.2 DSPORT.Disconnected (Waiting for SS Connect)
10.3.1.3 DSPORT.Training
10.3.1.4 DSPORT.ERROR
10.3.1.5 DSPORT.Enabled
10.3.1.6 DSPORT.Resetting
10.3.2 Disconnect Detect Mechanism
10.3.3 Labeling
10.4 Downstream Facing Ports Power Management
10.4.1 Downstream Facing Port PM Timer
10.4.2 Downstream Facing Port State Descriptions
10.4.2.1 Enabled U0 States
10.4.2.2 Attempt U0 – U1 Transition
10.4.2.3 Attempt U0 – U2 Transition
10.4.2.4 Link in U1
10.4.2.5 Link in U2
10.4.2.6 Link in U3
10.5 Upstream Facing Port
10.5.1 Upstream Facing Port State Descriptions
10.5.1.1 USPORT.Powered-off
10.5.1.2 USPORT.Powered-on
10.5.1.3 USPORT.Training
10.5.1.4 USPORT.Connected
10.5.1.5 USPORT.ERROR
10.5.1.6 USPORT.Enabled
10.6 Upstream Facing Port Power Management
10.7 Hub Header Forwarding and Data Repeater
10.7.1 Hub Elasticity Buffer
10.7.2 SKP Ordered Sets
10.7.3 Interpacket Spacing
10.7.4 Header Buffer Architecture
10.7.5 Upstream Facing Port TX
10.7.6 Upstream Facing Port TX State Descriptions
10.7.6.1 TX Idle
10.7.6.2 TX Header
10.7.6.3 TX Data
10.7.6.4 TX Data Abort
10.7.6.5 TX Link Command
10.7.7 Upstream Facing Port RX
10.7.8 Upstream Facing Port RX State Descriptions
10.7.8.1 RX Idle
10.7.8.2 RX Data
10.7.8.3 RX Header
10.7.8.4 Process Header
10.7.8.5 RX Link Command
10.7.8.6 Process Link Command
10.7.9 Downstream Facing Port TX
10.7.10 Downstream Facing Port TX State Descriptions
10.7.10.1 TX Idle
10.7.10.2 TX Header
10.7.10.3 TX Data
10.7.10.4 TX Data Abort
10.7.10.5 TX Link Command
10.7.11 Downstream Facing Port RX
10.7.12 Downstream Facing Port RX State Descriptions
10.7.12.1 RX Idle
10.7.12.2 RX Data
10.7.12.3 RX Header
10.7.12.4 Process Header
10.7.12.5 RX Link Command
10.7.12.6 Process Link Command
10.7.13 SuperSpeed Packet Connectivity
10.8 Suspend and Resume
10.9 Hub Reset Behavior
10.10 Hub Port Power Control
10.10.1 Multiple Gangs
10.11 Hub Controller
10.11.1 Endpoint Organization
10.11.2 Hub Information Architecture and Operation
10.11.3 Port Change Information Processing
10.11.4 Hub and Port Status Change Bitmap
10.11.5 Over-current Reporting and Recovery
10.11.6 Enumeration Handling
10.12 Hub Configuration
10.13 Descriptors
10.13.1 Standard Descriptors for Hub Class
10.13.2 Class-specific Descriptors
10.13.2.1 Hub Descriptor
10.14 Requests
10.14.1 Standard Requests
10.14.2 Class-specific Requests
10.14.2.1 Clear Hub Feature
10.14.2.2 Clear Port Feature
10.14.2.3 Get Hub Descriptor
10.14.2.4 Get Hub Status
10.14.2.5 Get Port Error Count
10.14.2.6 Get Port Status
10.14.2.7 Set Hub Descriptor
10.14.2.8 Set Hub Feature
10.14.2.9 Set Hub Depth
10.14.2.10 Set Port Feature
10.15 Host Root (Downstream) Ports
10.16 Device Upstream Ports
10.16.1 Peripheral Device Upstream Ports
10.16.1.1 Peripheral Device Connect State Machine
10.16.2 Peripheral Device Connect State Descriptions
10.16.2.1 PCONNECT.Powered-off
10.16.2.2 PCONNECT.Attempt SS Connect
10.16.2.3 PCONNECT.Connected on SS
10.16.2.4 PCONNECT.Connected on USB 2.0
10.16.2.5 PCONNECT.Connected on USB 2.0 Attempting SS Connection
10.17 Hub Chapter Parameters
11 Interoperability and Power Delivery
11.1 USB 3.0 Host Support for USB 2.0
11.2 USB 3.0 Hub Support for USB 2.0
11.3 USB 3.0 Device Support for USB 2.0
11.4 Power Distribution
11.4.1 Classes of Devices and Connections
11.4.1.1 Self-powered Hubs
11.4.1.2 Low-power Bus-powered Devices
11.4.1.3 High-power Bus-powered Devices
11.4.1.4 Self-powered Devices
11.4.2 Steady-State Voltage Drop Budget
11.4.3 Power Control During Suspend/Resume
11.4.4 Dynamic Attach and Detach
11.4.4.1 Inrush Current Limiting
11.4.4.2 Dynamic Detach
11.4.5 Vbus Electrical Characteristics
11.4.6 Powered-B Connector
11.4.7 Wire Gauge Table
A Symbol Encoding
B Symbol Scrambling
B.1 Data Scrambling
C Power Management
C.1 SuperSpeed Power Management Overview
C.1.1 Link PM States and Entry & Exit Processes
C.1.1.1 Summary of Link PM States
C.1.1.2 U0 – Link Active
C.1.1.3 U1 – Link Idle with Fast Exit
C.1.1.4 U2 – Link Idle with Slow Exit
C.1.1.5 U3 – Link Suspend
C.1.2 Link PM for Hubs
C.1.2.1 Link PM State Coordination and Management
C.1.2.2 Packet Deferring
C.1.2.3 Software Interface
C.1.3 Other Link PM Support Mechanisms
C.1.3.1 Packet Pending Flag
C.1.3.2 Support for Isochronous Transfers
C.1.3.3 Support for Interrupt Transfers
C.1.4 Device PM
C.1.4.1 Function Suspend
C.1.4.2 Device Suspend
C.1.4.3 Device and Fabric Suspend Entry Process
C.1.4.4 Host Initiated Device and Fabric Wakeup Process
C.1.4.5 Device and Fabric Remote Wakeup Process
C.1.5 Platform PM Support
C.2 SuperSpeed vs. High Speed Interface Selection Considerations for Devices
C.3 Link Power Management Implementation Guidelines
C.3.1 Recommendations for Device Initiated U1 and U2 Entry
C.3.1.1 System Information Available To Devices
C.3.1.2 Control Endpoints
C.3.1.3 Bulk Endpoints
C.3.1.4 Interrupt Endpoints
C.3.1.5 Isochronous Endpoints
C.3.1.6 Recommendations for Control Endpoints
C.3.1.7 Recommendations for Bulk Endpoints
C.3.1.8 Recommendations for Interrupt Endpoints
C.3.1.9 Recommendations for Isochronous Endpoints
C.3.1.10 Hub Downstream Ports Connected to another Hub
C.4 Device Power Management Implementation Guidelines
C.4.1 Deciding When to Initiate Selective Suspend
C.4.1.1 Background Information
C.4.1.2 Implementation Recommendations
C.4.2 Latency Tolerance Messaging (LTM) Implementation Guidelines
C.4.2.1 Device State Model and State Transition Algorithm
C.4.2.2 Other Considerations
C.4.3 Removing Power From Portions of a Device During Suspend
C.4.3.1 Devices Which Must Create Their Own Switched Power Rail
C.4.3.2 Devices Which Have a Switched Power Rail Provided by System
C.4.3.3 Self Powered Devices
C.4.3.4 Identifying What Needs To Remain Powered During Suspend
C.5 Calculation Examples for U1 and U2 System Exit Latency Fields
C.5.1 Path 1: Device Connected Directly to Host, Downstream Direction
C.5.2 Path 2: Device Connected Directly to Host, Upstream Direction
C.5.3 Path 3: Device Connected to Hub That is Connected to Host, Downstream Direction
C.5.4 Path 4: Device Connected to Hub That is Connected to Host, Upstream Direction
elecfans
Link Layer
Universal Serial Bus 3.0
Specification
HP
Intel Corporation
Microsoft Corporation
NEC Corporation
NXP Semiconductors
Texas Instruments Incorporated
Revision 0.9
July 30, 2008
Universal Serial Bus 3.0 Specification, Revision 0.9
Revision History
Comments
First consolidated review draft.
Updates to Chapters 6, 7, 8, 10, and 11.
Added Chapters 1, 3, and 12 and Appendixes A, B, and C. Updated
Chapters 4, 5, 6, 7, 8, 10, and 11.
Moved content into Chapter 2 and Appendix C. Updated all other
chapters except Appendixes A and B.
Updated all chapters except Chapter 1 and Appendixes A and B.
Incorporated all approved SCRs
Issue Date
October 19, 2007
November 9, 2007
December 26, 2007
April 4, 2008
June 19, 2008
July 30, 2008
Revision
0.7
0.75
0.78
0.85
0.9RC1
0.9
INTELLECTUAL PROPERTY DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY
WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE
AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY
PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE
PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
NOTE: THIS IS A DRAFT SPECIFICATION. The authors of this draft specification may
make changes to it at any time, without notice. Product designers should not rely on the
specification, and the authors shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes.
Please send comments to usb3feedback@usb.org
For industry information, refer to the USB Implementers Forum web page at http://www.usb.org/usb30
All product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2007-2008, HP, Intel Corporation, Microsoft Corporation, NEC Corporation, NXP Semiconductors, and Texas
Instruments Incorporated.
All rights reserved.
ii
Acknowledgement of USB 3.0 Technical
Contribution
Dedication
Dedicated to the memory of Brad Hosler, the impact of whose
accomplishments made the Universal Serial Bus one of the most
successful technology innovations of the Personal Computer era.
The authors of this specification would like to recognize the following people who participated in
the USB 3.0 Bus Specification technical workgroups. We would also like to acknowledge the
many others throughout the industry who provided feedback and contributed to the development of
this specification.
Promoter Company Employees
Alan Berkema
Anthony Hudson
Arthur Zarnowitz
Huimin Chen
Bob Dunstan
Dan Froelich
Brad Hosler
John Howard
Rahman Ismail
Yun Ling
Andy Martwick
Steve McGowan
Duane Quiet
Brad Saunders
Micah Sheller
Clint Walker
Jim Walsh
Kai Wang
Randy Aull
Nathan Sherman
David Wooten
Nobuyuki Mizukoshi
Hajime Nozaki
Kenji Oguma
Hock Seow
"Peter" Chu Tin Teng
Hewlett Packard
Hewlett Packard
Hewlett Packard
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
iii
Universal Serial Bus 3.0 Specification, Revision 0.9
Socol Constantin
Linus Kerk
Martin Klein
Geert Knapen
Bart Vertenten
Julie Nirchi
Mitsuru Shimada
Sue Vining
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors
Texas Instruments
Texas Instruments
Texas Instruments
Contributor Company Employees
Glen Chandler
John Chen
Roger Hou
Charles Wang
Norman Wu
Steven Yang
George Yee
George Olear
Sophia Liu
William Northey
Tom Sultzer
Garry Biddle
Kuan-Yu Chen
Jason Chou
Gustavo Duenas
Bob Hall
Jiayong He
Jim Koser
Joe Ortega
Ash Raheja
James Sabo
Pei Tsao
Kevin Walker
Tsuneki Watanabe
Chong Yi
Taro Hishinuma
Kaz Ichikawa
Ryozo Koyama
Karl Kwiat
Tadashi Sakaizawa
Shinya Tono
Eiji Wakatsuki
Acon
Acon
Acon
Acon
Acon
Acon
Acon
Contech Research
Electronics Testing Center, Taiwan (ETC)
FCI
FCI
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
iv
Takashi Ehara
Ron Muir
Kazuhiro Saito
Hitoshi Kawamura
Takashi Kawasaki
Atsushi Nishio
Yasuhiko Shinohara
Tom Lu
Edmund Poh
Scott Sommers
Jason Squire
Dat Ba Nguyen
Jan Fahllund
Richard Petrie
Panu Ylihaavisto
Alvin Cox
Martin Furuhjelm
Julian Gorfajn
Marc Hildebrant
Tony Priborsky
Saleem Mohammad
Daniel Weinlader
Thomas Grzysiewicz
Masaaki Iwasaki
Kazukiyo Osada
Hiroshi Shirai
Scott Shuey
Masaru Ueno
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
Mitsumi
Mitsumi
Mitsumi
Mitsumi
Molex Inc.
Molex Inc.
Molex Inc.
Molex Inc.
NTS/National Technical System
Nokia
Nokia
Nokia
Seagate
Seagate
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Synopsys, Inc.
Synopsys, Inc.
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
v
Universal Serial Bus 3.0 Specification, Revision 0.9
vi
Contents
Acknowledgement of USB 3.0 Technical Contribution
1
Introduction
1.1 Motivation.................................................................................................................1-1
1.2
Objective of the Specification...................................................................................1-2
Scope of the Document............................................................................................1-2
1.3
USB Product Compliance.........................................................................................1-2
1.4
Document Organization............................................................................................1-3
1.5
1.6
Design Goals............................................................................................................1-3
Related Documents..................................................................................................1-3
1.7
2 Terms and Abbreviations
3 SuperSpeed USB Architectural Overview
3.1
3.2
3.3
3.2.3
3.2.4
USB 3.0 Overview....................................................................................................3-1
SuperSpeed Architecture Overview........................................................3-2
3.1.1
3.1.1.1
Physical Layer.................................................................3-2
Link Layer........................................................................3-3
3.1.1.2
Protocol Layer.................................................................3-3
3.1.1.3
Hubs................................................................................3-4
3.1.1.4
3.1.1.5
Power Management ........................................................3-5
USB 3.0 System.......................................................................................................3-5
Comparing SuperSpeed USB to USB 2.0 ..............................................3-5
3.2.1
System Level Topology ..........................................................................3-7
3.2.2
3.2.2.1
Hosts...............................................................................3-7
Hubs................................................................................3-8
3.2.2.2
3.2.2.3
Devices ...........................................................................3-8
Bus Protocol ...........................................................................................3-9
Robustness...........................................................................................3-10
Error Detection..............................................................3-10
3.2.4.1
3.2.4.2
Error Handling...............................................................3-10
USB Specification Chapter Overview.....................................................................3-11
3.3.1
Mechanical............................................................................................3-12
Physical Layer ......................................................................................3-14
3.3.2
Link Layer .............................................................................................3-15
3.3.3
Protocol Layer.......................................................................................3-15
3.3.4
3.3.5
Framework Layer..................................................................................3-16
Hubs .....................................................................................................3-16
3.3.6
Hub Architecture ...........................................................3-17
3.3.6.1
3.3.6.2
Hub Repeater/Forwarder Architecture ..........................3-18
3.3.6.3
Hubs and Transfers to Power Managed Links ..............3-18
Performance and Power Efficiency.......................................................3-18
3.3.7
vii
Universal Serial Bus 3.0 Specification, Revision 0.9
3.3.8
SuperSpeed Power Management.........................................................3-19
Link Power Management ..............................................3-19
3.3.8.1
Function and Device Power Management ....................3-20
3.3.8.2
3.3.8.3
Platform PM Support.....................................................3-21
4. SuperSpeed Data Flow Model
4.1
4.2
4.3
4.4
4.3.1.2
4.3.1.3
Implementer Viewpoints...........................................................................................4-1
SuperSpeed USB Communication Flow ..................................................................4-1
4.2.1
Pipes.......................................................................................................4-2
SuperSpeed USB Protocol Overview.......................................................................4-2
Differences with USB 2.0........................................................................4-2
4.3.1
4.3.1.1
Comparing USB 2.0 and SuperSpeed USB
Transactions....................................................................4-2
Comparing USB 2.0 and SuperSpeed USB Bus
Topology .........................................................................4-3
Introduction to SuperSpeed USB Packets ......................4-4
Generalized Transfer Description.............................................................................4-4
Data Bursting..........................................................................................4-5
4.4.1
IN Transfers............................................................................................4-6
4.4.2
OUT Transfers........................................................................................4-7
4.4.3
4.4.4
Power Management and Performance...................................................4-7
Control Transfers....................................................................................4-8
4.4.5
Control Transfer Packet Size ..........................................4-8
4.4.5.1
4.4.5.2
Control Transfer Bandwidth Requirements .....................4-9
4.4.5.3
Control Transfer Data Sequences...................................4-9
Bulk Transfers.........................................................................................4-9
Bulk Transfer Packet Size.............................................4-10
4.4.6.1
Bulk Transfer Bandwidth Requirements........................4-10
4.4.6.2
4.4.6.3
Bulk Transfer Data Sequences .....................................4-11
4.4.6.4
Bulk Streams.................................................................4-11
Interrupt Transfers ................................................................................4-13
Interrupt Transfer Packet Size ......................................4-14
4.4.7.1
4.4.7.2
Interrupt Transfer Bandwidth Requirements .................4-14
4.4.7.3
Interrupt Transfer Data Sequences...............................4-15
Isochronous Transfers..........................................................................4-15
Isochronous Transfer Packet Size ................................4-16
4.4.8.1
4.4.8.2
Isochronous Transfer Bandwidth Requirements ...........4-16
4.4.8.3
Isochronous Transfer Data Sequences.........................4-17
Device Notifications ..............................................................................4-17
Reliability ..............................................................................................4-18
4.4.10.1
Physical Layer...............................................................4-18
Link Layer......................................................................4-18
4.4.10.2
4.4.10.3
Protocol Layer...............................................................4-18
Efficiency ..............................................................................................4-18
4.4.9
4.4.10
4.4.6
4.4.7
4.4.8
5.1
5.2
Objective ..................................................................................................................5-1
Significant Features..................................................................................................5-1
5.2.1
Connectors .............................................................................................5-1
USB 3.0 Standard-A Connector ......................................5-2
5.2.1.1
4.4.11
5 Mechanical
viii
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