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ePAPR v1.1.pdf
Revision History
1 Introduction
1.1 Purpose and Scope
1.2 Relationship to IEEE™ 1275
1.3 32-bit and 64-bit Support
1.4 References
1.5 Definition of Terms
2 The Device Tree
2.1 Overview
2.2 Device Tree Structure and Conventions
2.2.1 Node Names
2.2.1.1 Node Name Requirements
2.2.2 Generic Names Recommendation
2.2.3 Path Names
2.2.4 Properties
2.2.4.1 Property Names
2.2.4.2 Property Values
2.3 Standard Properties
2.3.1 compatible
2.3.2 model
2.3.3 phandle
2.3.4 status
2.3.5 #address-cells and #size-cells
2.3.6 reg
2.3.7 virtual-reg
2.3.8 ranges
2.3.9 dma-ranges
2.3.10 name
2.3.11 device_type
2.4 Interrupts and Interrupt Mapping
2.4.1 Properties for Interrupt Generating Devices
2.4.1.1 interrupts
2.4.1.2 interrupt-parent
2.4.2 Properties for Interrupt Controllers
2.4.2.1 #interrupt-cells
2.4.2.2 interrupt-controller
2.4.3 Interrupt Nexus Properties
2.4.3.1 interrupt-map
2.4.3.2 interrupt-map-mask
2.4.3.3 #interrupts-cells
2.4.4 Interrupt Mapping Example
3 Device Node Requirements
3.1 Base Device Node Types
3.2 Root node
3.3 aliases node
3.4 Memory node
3.5 Chosen
3.6 CPUS Node Properties
3.7 CPU Node Properties
3.7.1 General Properties of CPU nodes
3.7.2 TLB Properties
3.7.3 Internal (L1) Cache Properties
3.7.4 Example
3.8 Multi-level and Shared Caches
4 Client Program Image Format
4.1 Variable Address Image Format
4.1.1 ELF Basics
4.1.2 Boot Program Requirements
4.1.2.1 Processing of PT_LOAD segments
4.1.2.2 Entry point
4.1.3 Client Program Requirements
4.2 Fixed Address Image Format
5 Client Program Boot Requirements
5.1 Boot and Secondary CPUs
5.2 Device Tree
5.3 Initial Mapped Areas
5.4 CPU Entry Point Requirements
5.4.1 Boot CPU Initial Register State
1.1.1
5.4.2 I/O Devices State
5.4.3 Initial I/O Mappings (IIO)
5.4.4 Boot CPU Entry Requirements: Real Mode
5.4.5 Boot CPU Entry Requirements for IMAs: Book IIII-E
5.5 Symmetric Multiprocessing (SMP) Boot Requirements
5.5.1 Overview
5.5.2 Spin Table
5.5.2.1 Overview
5.5.2.2 Boot Program Requirements
5.5.2.3 Client Program Requirements
5.5.3 Implementation-Specific Release from Reset
5.5.4 Timebase Synchronization
5.6 Asymmetric Configuration Considerations
6 Device Bindings
6.1 Binding Guidelines
6.1.1 General Principles
6.1.2 Miscellaneous Properties
6.1.2.1 clock-frequency
6.1.2.2 reg-shift
6.1.2.3 label
1.1
6.2 Serial devices
6.2.1 Serial Class Binding
6.2.1.1 clock-frequency
6.2.1.2 current-speed
6.2.2 National Semiconductor 16450/16550 Compatible UART Requirements
6.3 Network devices
6.3.1 Network Class Binding
6.3.1.1 address-bits
6.3.1.2 local-mac-address
6.3.1.3 mac-address
6.3.1.4 max-frame-size
6.3.2 Ethernet specific considerations
6.3.2.1 max-speed
6.3.2.2 phy-connection-type
6.3.2.3 phy-handle
6.4 open PIC Interrupt Controllers
6.5 simple-bus
7 Virtualization
7.1 Overview
7.2 Hypercall Application Binary Interface (ABI)
7.3 ePAPR Hypercall Token Definition
7.4 Hypercall Return Codes
7.5 Hypervisor Node
7.6 ePAPR Virtual Interrupt Controller Services
1.1.1
7.6.1 Virtual Interrupt Controller Device Tree Representation
7.6.1.1 Interrupt Controller Node
7.6.1.2 Interrupt Specifiers
7.6.1.3 IPI Representation
7.6.2 ePAPR Interrupt Controller Hypercalls
7.6.2.1 EV_INT_SET_CONFIG
7.6.2.2 EV_INT_GET_CONFIG
7.6.2.3 EV_INT_SET_MASK
7.6.2.4 EV_INT_GET_MASK
7.6.2.5 EV_INT_IACK
7.6.2.6 EV_INT_EOI
7.6.2.7 EV_INT_SEND_IPI
7.6.2.8 EV_INT_SET_TASK_PRIORITY
7.6.2.9 EV_INT_GET_TASK_PRIORITY
7.7 Byte-channel Services
7.7.1 Overview
7.7.2 Interrupts and Guest Device Tree Representation
7.7.3 Byte-channel Hypercalls
7.7.3.1 EV_BYTE_CHANNEL_SEND
7.7.3.2 EV_BYTE_CHANNEL_RECEIVE
7.7.3.3 EV_BYTE_CHANNEL_POLL
7.8 Inter-partition Doorbells
7.8.1 Overview
7.8.2 Doorbell Send Endpoints
7.8.3 Doorbell Receive Endpoints
7.8.4 Doorbell Hypercall
7.9 msgsnd
7.9.1 EV_MSGSND
1.1
7.10 Idle
EV_IDLE
8 Flat Device Tree Physical Structure
8.1 Versioning
8.2 Header
8.3 Memory Reservation Block
8.3.1 Purpose
8.3.2 Format
8.4 Structure Block
8.4.1 Lexical structure
8.4.2 Tree structure
8.5 Strings Block
8.6 Alignment
Appendix A Device Tree Source Format (version 1)
Appendix B1 Ebony Device Tree
Appendix B2 – MPC8572DS Device Tree
Power.org™ Standard for Embedded Power Architecture™ Platform Requirements
(ePAPR)
Version 1.1 – 08 April 2011
Copyright © 2008,2011 Power.org. All rights reserved.
The Power Architecture and Power.org word marks and the Power and Power.org logos
and related marks are trademarks and service marks licensed by Power.org.
Implementation of certain elements of this document may require licenses under third
party intellectual property rights, including without limitation, patent rights. Power.org
and its Members are not, and shall not be held, responsible in any manner for identifying
or failing to identify any or all such third party intellectual property rights.
THIS POWER.ORG SPECIFICATION PROVIDED “AS IS” AND WITHOUT ANY WARRANTY OF
ANY KIND, INCLUDING, WITHOUT LIMITATION, ANY EXPRESS OR IMPLIED WARRANTY OF
NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL POWER.ORG OR ANY MEMBER OF POWER.ORG BE LIABLE FOR ANY
DIRECT, INDIRECT, SPECIAL, EXEMPLARY, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
INCLUDING, WITHOUT LIMITATION, LOST PROFITS, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
Questions pertaining to this document, or the terms or conditions of its provision, should
be addressed to:
IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Power.org Board Secretary
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Version 1.1 – 7 March 2011
Power.org ePAPR
LICENSE INFORMATION
© Copyright 2008,2011 Power.org, Inc
© Copyright Freescale Semiconductor, Inc., 2008,2011
© Copyright International Business Machines Corporation, 2008,2011
All Rights Reserved.
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Page 2 of 108
Version 1.1 – 7 March 2011
Power.org ePAPR
2.2.1
2.2.2
2.2.3
2.2.4
Table of Contents
REVISION HISTORY ................................................................................................................................... 7
1
INTRODUCTION .............................................................................................................................. 8
1.1 PURPOSE AND SCOPE ............................................................................................................................. 8
1.2 RELATIONSHIP TO IEEE™ 1275 ............................................................................................................. 10
1.3 32-BIT AND 64-BIT SUPPORT ................................................................................................................ 10
1.4 REFERENCES ....................................................................................................................................... 11
1.5 DEFINITION OF TERMS .......................................................................................................................... 13
THE DEVICE TREE .......................................................................................................................... 14
2.1 OVERVIEW ......................................................................................................................................... 14
2.2 DEVICE TREE STRUCTURE AND CONVENTIONS ........................................................................................... 15
Node Names ......................................................................................................................... 15
Generic Names Recommendation ........................................................................................ 17
Path Names .......................................................................................................................... 18
Properties .............................................................................................................................. 18
2.3 STANDARD PROPERTIES ........................................................................................................................ 21
2.3.1
compatible ............................................................................................................................ 21
2.3.2 model .................................................................................................................................... 21
phandle ................................................................................................................................. 22
2.3.3
status .................................................................................................................................... 23
2.3.4
#address-cells and #size-cells ............................................................................................... 24
2.3.5
2.3.6
reg ......................................................................................................................................... 25
virtual-reg ............................................................................................................................. 25
2.3.7
ranges ................................................................................................................................... 26
2.3.8
dma-ranges ........................................................................................................................... 28
2.3.9
2.3.10
name ................................................................................................................................ 29
device_type ...................................................................................................................... 29
2.3.11
INTERRUPTS AND INTERRUPT MAPPING ................................................................................................... 30
Properties for Interrupt Generating Devices ......................................................................... 32
2.4.1
Properties for Interrupt Controllers ...................................................................................... 33
2.4.2
Interrupt Nexus Properties .................................................................................................... 33
2.4.3
2.4.4
Interrupt Mapping Example .................................................................................................. 35
DEVICE NODE REQUIREMENTS ...................................................................................................... 37
3.1 BASE DEVICE NODE TYPES .................................................................................................................... 37
3.2 ROOT NODE ....................................................................................................................................... 37
3.3 ALIASES NODE ..................................................................................................................................... 38
3.4 MEMORY NODE .................................................................................................................................. 39
3.5 CHOSEN ............................................................................................................................................ 40
3.6 CPUS NODE PROPERTIES ..................................................................................................................... 41
3.7 CPU NODE PROPERTIES ....................................................................................................................... 41
General Properties of CPU nodes .......................................................................................... 42
TLB Properties ....................................................................................................................... 44
Internal (L1) Cache Properties .............................................................................................. 45
3.7.1
3.7.2
3.7.3
2
2.4
3
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
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Version 1.1 – 7 March 2011
Power.org ePAPR
4
5
6
7
3.7.4
4.1.1
4.1.2
4.1.3
5.5.1
5.5.2
5.5.3
5.5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Example ................................................................................................................................ 46
3.8 MULTI-LEVEL AND SHARED CACHES ........................................................................................................ 46
CLIENT PROGRAM IMAGE FORMAT .............................................................................................. 48
4.1 VARIABLE ADDRESS IMAGE FORMAT ....................................................................................................... 48
ELF Basics .............................................................................................................................. 48
Boot Program Requirements ................................................................................................ 48
Client Program Requirements ............................................................................................... 49
4.2 FIXED ADDRESS IMAGE FORMAT ............................................................................................................ 50
CLIENT PROGRAM BOOT REQUIREMENTS ..................................................................................... 51
5.1 BOOT AND SECONDARY CPUS ............................................................................................................... 51
5.2 DEVICE TREE ...................................................................................................................................... 51
5.3
INITIAL MAPPED AREAS ........................................................................................................................ 51
5.4 CPU ENTRY POINT REQUIREMENTS ........................................................................................................ 52
Boot CPU Initial Register State.............................................................................................. 52
I/O Devices State ................................................................................................................... 53
Initial I/O Mappings (IIO) ...................................................................................................... 53
Boot CPU Entry Requirements: Real Mode ........................................................................... 54
Boot CPU Entry Requirements for IMAs: Book IIII-E .............................................................. 54
5.5 SYMMETRIC MULTIPROCESSING (SMP) BOOT REQUIREMENTS .................................................................... 55
Overview ............................................................................................................................... 55
Spin Table ............................................................................................................................. 56
Implementation-Specific Release from Reset ....................................................................... 59
Timebase Synchronization .................................................................................................... 59
5.6 ASYMMETRIC CONFIGURATION CONSIDERATIONS ...................................................................................... 59
DEVICE BINDINGS ......................................................................................................................... 60
6.1 BINDING GUIDELINES ........................................................................................................................... 60
6.1.1
General Principles ................................................................................................................. 60
6.1.2 Miscellaneous Properties ...................................................................................................... 61
6.2 SERIAL DEVICES ................................................................................................................................... 62
Serial Class Binding ............................................................................................................... 62
National Semiconductor 16450/16550 Compatible UART Requirements ............................ 63
6.3 NETWORK DEVICES .............................................................................................................................. 63
Network Class Binding .......................................................................................................... 63
Ethernet specific considerations ........................................................................................... 64
6.4 OPEN PIC INTERRUPT CONTROLLERS ....................................................................................................... 66
SIMPLE-BUS ........................................................................................................................................ 66
6.5
VIRTUALIZATION ........................................................................................................................... 67
7.1 OVERVIEW ......................................................................................................................................... 67
7.2 HYPERCALL APPLICATION BINARY INTERFACE (ABI) ................................................................................... 67
7.3
EPAPR HYPERCALL TOKEN DEFINITION ................................................................................................... 68
7.4 HYPERCALL RETURN CODES ................................................................................................................... 69
7.5 HYPERVISOR NODE .............................................................................................................................. 70
EPAPR VIRTUAL INTERRUPT CONTROLLER SERVICES .................................................................................. 71
7.6
Virtual Interrupt Controller Device Tree Representation ...................................................... 71
6.2.1
6.2.2
6.3.1
6.3.2
7.6.1
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Page 4 of 108
Version 1.1 – 7 March 2011
Power.org ePAPR
7.8
7.9.1
7.10
8
7.6.2
7.7.1
7.7.2
7.7.3
7.8.1
7.8.2
7.8.3
7.8.4
ePAPR Interrupt Controller Hypercalls .................................................................................. 73
7.7 BYTE-CHANNEL SERVICES ...................................................................................................................... 80
Overview ............................................................................................................................... 80
Interrupts and Guest Device Tree Representation ................................................................ 81
Byte-channel Hypercalls........................................................................................................ 82
INTER-PARTITION DOORBELLS ................................................................................................................ 84
Overview ............................................................................................................................... 84
Doorbell Send Endpoints ....................................................................................................... 84
Doorbell Receive Endpoints .................................................................................................. 84
Doorbell Hypercall ................................................................................................................ 85
7.9 MSGSND ............................................................................................................................................ 85
EV_MSGSND ......................................................................................................................... 85
IDLE ............................................................................................................................................. 86
EV_IDLE ............................................................................................................................................... 86
FLAT DEVICE TREE PHYSICAL STRUCTURE ...................................................................................... 87
8.1 VERSIONING ....................................................................................................................................... 87
8.2 HEADER ............................................................................................................................................ 88
8.3 MEMORY RESERVATION BLOCK.............................................................................................................. 89
Purpose ................................................................................................................................. 89
Format .................................................................................................................................. 90
8.4 STRUCTURE BLOCK .............................................................................................................................. 91
Lexical structure .................................................................................................................... 91
Tree structure ....................................................................................................................... 92
8.5 STRINGS BLOCK .................................................................................................................................. 93
8.6 ALIGNMENT ....................................................................................................................................... 94
APPENDIX A DEVICE TREE SOURCE FORMAT (VERSION 1) ..................................................................... 95
APPENDIX B1 EBONY DEVICE TREE ........................................................................................................ 97
APPENDIX B2 – MPC8572DS DEVICE TREE ............................................................................................ 104
8.3.1
8.3.2
8.4.1
8.4.2
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Page 5 of 108
Version 1.1 – 7 March 2011
Power.org ePAPR
Acknowledgements
The power.org Platform Architecture Technical Subcommittee would like thank the many individuals
and companies that contributed to the development this specification through writing, technical
discussions and reviews.
Individuals (in alphabetical order)
Hollis Blanchard
Dan Bouvier
Josh Boyer
Becky Bruce
Dale Farnsworth
Kumar Gala
David Gibson
Ben Herrenschmidt
Dan Hettena
Olof Johansson
Ashish Kalra
Grant Likely
Jon Loeliger
Hartmut Penner
Tim Radzykewycz
Heiko Schick
Timur Tabi
John Traill
John True
Matt Tyrlik
Dave Willoughby
Scott Wood
Jimi Xenidis
Stuart Yoder
Companies
Freescale Semiconductor
Green Hills Software
IBM
Montavista
Wind River
Other Acknowledgements
Significant aspects of the ePAPR device tree are based on work done by the Open Firmware Working
Group which developed bindings for IEEE-1275. We would like to acknowledge their contributions.
We would also like to acknowledge the contribution of the PowerPC Linux community that initially
developed and implemented the flattened device tree concept.
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Page 6 of 108
Version 1.1 – 7 March 2011
Power.org ePAPR
Revision History
Revision Date
1.0
1.1
7/23/2008
3/7/2011
Description
Initial Version
Updates include: virtualization chapter, consolidated representation of cpu
nodes, stdin/stdout properties on /chosen, label property, representation of
hardware threads on cpu nodes, representation of Power ISA categories on
cpu nodes, mmu type property, removal of some bindings, additional cpu
entry requirements for threaded cpus, miscellaneous cleanup and
clarifications.
Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Page 7 of 108
1 Introduction
1.1 Purpose and Scope
To initialize and boot a computer system, various software components interact—firmware might
perform low-level initialization of the system hardware before passing control to software such as an
operating system, bootloader, or hypervisor. Bootloaders and hypervisors can, in turn, load and
transfer control to operating systems. Standard, consistent interfaces and conventions facilitate the
interactions between these software components. In this document the term boot program is used to
generically refer to a software component that initializes the system state and executes another
software component referred to as a client program. Examples of a boot programs include: firmware,
bootloaders, and hypervisors. Examples of a client program include: bootloaders, hypervisors,
operating systems, and special purpose programs. A piece of software (e.g. a hypervisor) may be
both a client program and a boot program.
This specification, the Embedded Power Architecture Platform Requirements (ePAPR), provides a
complete boot program to client program interface definition, combined with minimum system
requirements that facilitate the development of a wide variety of embedded systems based on CPUs
that implement the Power architecture as defined in the Power ISA™ [1].
This specification is targeted towards the requirements of embedded systems. An embedded system
typically consists of system hardware, an operating system, and application software that are custom
designed to perform a fixed, specific set of tasks. This is unlike general purpose computers, which are
designed to be customized by a user with a variety of software and I/O devices. Other characteristics
of embedded systems can include:
a fixed set of I/O devices, possibly highly customized for the application
a system board optimized for size and cost
limited user interface
resource constraints like limited memory and limited nonvolatile storage
real-time constraints
•
•
•
•
•
• use of a wide variety of operating systems, including Linux, real-time operating systems, and
custom or proprietary operating systems
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Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
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