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AURIX TC275 UM.pdf
Table of Contents
1 TC27x Introduction
1.1 About this Document
1.1.1 Related Documentations
1.1.2 Text Conventions
1.1.3 Reserved, Undefined, and Unimplemented Terminology
1.1.4 Register Access Modes
1.1.5 Abbreviations and Acronyms
1.2 System Architecture of the TC27x
1.2.1 TC27x Block Diagram
1.3 Hardware Security Module (HSM)
1.4 On-Chip Debug Support (OCDS)
1.4.1 Feature List
1.4.2 Family Overview
1.4.3 Tool Interface Recommendations
1.4.4 Debug Access Server (DAS)
1.5 Emulation Device (ED)
1.5.1 Block Diagram
1.5.2 Feature List
1.5.3 Comparison to TC1798ED
1.5.4 Trace Based Measurement
1.5.5 ED Design and Layout
1.5.6 Emulation System Components
1.5.6.1 Emulation Memory (EMEM)
1.5.6.2 MCDS
1.5.6.3 DAP/JTAG based Tool Interface (IOC32)
1.5.6.4 Aurora GigaBit Trace (AGBT)
2 On-Chip System Buses and Bus Bridges
2.1 What is new
2.2 SRI Crossbar (XBar_SRI)
2.2.1 Introduction
2.2.1.1 XBar_SRI Features
2.2.2 SRI Transactions
2.2.3 SRI Op-Codes
2.2.4 SRI Error Conditions
2.2.5 SRI Transaction ID Error Conditions
2.2.6 Operational Overview
2.2.6.1 Functional Blocks
2.2.7 Functional Overview
2.2.7.1 Arbitration Block
2.2.7.2 Default Slave
2.2.7.3 Register Access Protection
2.2.7.4 SRI ECC Error Handling
2.2.7.5 Error Tracking Capability
2.2.7.6 Debug Trigger Event Generation (OCDS Level 1)
2.2.7.7 Interrupt and Debug Events of the XBar_SRI Module
2.2.8 Implementation of the Cross Bar (XBar_SRI) in the TC27x
2.2.8.1 Mapping of SRI Master Modules to XBar_SRI Master Interfaces
2.2.8.2 Mapping of SRI Slave modules to XBar_SRI Slave Interfaces
2.2.8.3 TC27x SRI Master / Slave Interconnection Matrix
2.2.8.4 Connection Master-Slave in XBar_SRI
2.2.9 SRI Crossbar Registers
2.2.9.1 TC27x Control Registers
2.3 Shared Resource Interconnect to FPI Bus Interface (SFI Bridge)
2.3.1 Functional Overview
2.4 System Peripheral Bus
2.4.1 Overview
2.4.2 Bus Transaction Types
2.4.3 Reaction of a Busy Slave
2.4.4 Address Alignment Rules
2.4.5 FPI Bus Basic Operations
2.5 FPI Bus Control Unit (SBCU)
2.5.1 FPI Bus Arbitration
2.5.1.1 Arbitration on the System Peripheral Bus
2.5.1.2 Default Master
2.5.1.3 Arbitration Algorithms
2.5.1.4 Starvation Prevention
2.5.2 FPI Bus Error Handling
2.5.3 System Registers
2.5.3.1 Register Access Protection (ACCEN1/0)
2.5.3.2 Kernel Reset Registers (KRST1/0, KRSTCLR)
2.5.3.3 Clock Control Register (CLC)
2.5.3.4 OCDS Control and Status Register (OCS)
2.5.4 BCU Debug Support
2.5.4.1 Address Triggers
2.5.4.2 Signal Status Triggers
2.5.4.3 Grant Triggers
2.5.4.4 Combination of Triggers
2.5.4.5 BCU Breakpoint Generation Examples
2.5.5 System Bus Control Unit Registers
2.5.5.1 SBCU System Registers
2.5.5.2 SBCU Control Registers Descriptions
2.5.5.3 SBCU Error Registers Descriptions
2.5.5.4 SBCU OCDS Registers Descriptions
2.6 On Chip Bus Master TAG Assignments
2.7 On Chip Bus Access Times
3 Memory Maps
3.1 How to Read the Address Maps
3.2 Contents of the Segments
3.3 Address Map of the On Chip Bus System
3.3.1 Segments 0 to 14
3.3.2 Segment 15
3.4 Memory Module Access Restrictions
3.5 Side Effects from Modules to CPU0 Data Scratch Pad SRAM (DSPR0)
4 TC27x BootROM Content
4.1 Startup Software
4.1.1 Events triggering SSW execution
4.1.1.1 Power-on
4.1.1.2 System reset
4.1.1.3 Application reset
4.1.2 Clock system during start-up
4.1.3 RAM overwrite during start-up
4.1.4 Boot Options Summary
4.1.5 Start-up mode selection
4.1.5.1 Hardware configuration
4.1.5.2 Configuration by Boot Mode Index (BMI)
4.1.6 Startup Software Main Flow
4.1.6.1 Basic Device Settings
4.1.6.2 RAMs Handling
4.1.6.3 Select and Prepare Startup Modes
4.1.6.4 Final Chip Settings
4.1.6.5 Ending the SSW and Starting the User Code
4.2 Bootstrap Loaders
4.2.1 ASC Bootstrap loader
4.2.2 CAN Bootstrap Loader
4.2.3 Summary of Bootstrap Loader Modes
4.3 Shutdown request handler
4.4 Power Supply Friendly Debug Monitor
4.4.1 PSFDM code with inverse exit condition
4.5 Preparation before to enter Stand-by mode
5 CPU Subsystem
5.1 AURIX Family CPU configurations
5.2 Central Processing Unit Features
5.3 TC1.6P Implementation Overview
5.3.1 CPU Diagram
5.3.2 Instruction Fetch Unit
5.3.3 Execution Unit
5.3.4 General Purpose Register File
5.4 TC1.6E Implementation Overview
5.4.1 CPU Diagram
5.4.2 Instruction Fetch Unit
5.4.3 Execution Unit
5.4.4 General Purpose Register File
5.5 Summary of functional changes from TC1.3.1
5.6 CPU Implementation-Specific Features
5.6.1 Context Save Areas / Context Operations
5.6.2 Program Counter (PC) Register
5.6.3 Store Buffers
5.6.4 Interrupt System
5.6.5 Trap System
5.6.6 Memory Integrity Error Handling
5.6.6.1 Program Side Memories
5.6.6.2 Data Side Memories
5.6.6.3 Memory Initialisation
5.6.7 WAIT Instruction
5.6.8 Instruction Memory Range Limitations
5.6.9 Atomicity of Data Accesses
5.6.10 A11 usage
5.7 Memory Addressing
5.7.1 CSFR and SFR base Locations
5.7.2 Local and Global Addressing
5.7.3 Cache Memory Access
5.8 CPU Subsystem Registers
5.8.1 CPU Core Special Function Registers (CSFR)
5.8.1.1 Registers
5.8.2 CPU General Purpose Registers
5.8.3 CPU Memory Protection Registers
5.8.4 Temporal Protection Registers
5.8.5 FPU Registers
5.8.6 Memory Integrity Registers
5.8.6.1 Register Descriptions
5.8.7 CPU Core Debug and Performance Counter Registers
5.8.7.1 Counter Source Details
5.8.8 Summary of CSFR Reset Values and Access Modes
5.8.9 Summary of SFR Reset Values and Access modes
5.9 CPU Instruction Timing
5.9.1 Integer-Pipeline Instructions
5.9.1.1 Simple Arithmetic Instruction Timings
5.9.1.2 Multiply Instruction Timings
5.9.1.3 Multiply Accumulate (MAC) Instruction Timing
5.9.1.4 Control Flow Instruction Timing TC1.6P
5.9.1.5 Control Flow Instruction Timing TC1.6E
5.9.2 Load-Store Pipeline Instructions
5.9.2.1 Address Arithmetic Timing
5.9.2.2 CSA Control Flow Instruction Timing
5.9.2.3 Load Instruction Timing
5.9.2.4 Store Instruction Timing
5.9.3 Floating Point Pipeline Timing
5.10 Program Memory Interface (PMI)
5.10.1 TC1.6P PMI Description
5.10.1.1 TC1.6P Scratchpad RAM
5.10.1.2 TC1.6P Program Cache
5.10.1.3 TC1.6P Program Line Buffer
5.10.1.4 TC1.6P CPU Slave Interface (CPS)
5.10.2 TC1.6E PMI Description
5.10.2.1 TC1.6E Program Scratchpad RAM
5.10.2.2 TC1.6E Program Cache
5.10.2.3 TC1.6E Program Line Buffer
5.10.2.4 TC1.6E CPU Slave Interface (CPS)
5.10.3 PMI Registers
5.10.3.1 PMI Register Descriptions
5.11 Data Memory Interface (DMI)
5.11.1 TC1.6P DMI Description
5.11.1.1 TC1.6P Data Scratchpad RAM (DSPR)
5.11.1.2 TC1.6P Data Cache (DCACHE)
5.11.2 TC1.6E DMI Description
5.11.2.1 TC1.6E Data Scratchpad RAM (DSPR)
5.11.2.2 TC1.6E Data Read Buffer (DRB)
5.11.3 DMI Trap Generation
5.11.4 DMI Registers
5.11.4.1 DMI Register Descriptions
5.12 Safety Features
5.12.1 SRI Data Master Address Phase Error Injection
5.12.2 SRI Data Master Write Phase Error Injection
5.12.3 SRI Data Slave Read Phase Error Injection
5.12.4 SRI Error Capture
5.12.5 SRI Safe Data Master tag
5.12.6 Safety Memory Protection
5.12.7 Safety Register Protection
5.12.8 Lock Step Implementation
5.12.9 MBIST usage recommendations
5.12.10 Registers Implementing Safety Features
6 Lockstep Comparator Logic (LCL)
6.1 Feature List
6.2 Lockstep Control
6.3 Lockstep Monitoring
6.4 Lockstep Self Test
6.5 Lockstep Failure Signalling Test
6.6 Functional Redundancy
6.7 Revision History
7 System Control Units
7.1 Clocking and Clock Control Unit (CCU)
7.1.1 Clock Sources
7.1.1.1 Oscillator Circuit (OSC)
7.1.1.2 Back-up Clock
7.1.2 Clock Speed Upscaling
7.1.2.1 Phase-Locked Loop (PLL) Module
7.1.2.2 ERAY Phase-Locked Loop (PLL_ERAY) Module
7.1.3 Clock Distribution
7.1.3.1 Clock Control Unit
7.1.4 Individual Clock Generation
7.1.4.1 Clock Control Register CLC
7.1.5 Clock Monitors
7.1.5.1 Clock Monitor Registers
7.1.6 Clock Emergency Behavior
7.1.7 External Clock Output
7.1.7.1 Programmable Frequency Output for EXTCLK0
7.1.7.2 Programmable Frequency Output for EXTCLK1
7.1.7.3 Clock Output Control Register
7.1.8 Clock Generation Unit
7.1.8.1 Example Sequence
7.1.9 CCU Register Address
7.1.10 CCU Kernel Registers
7.2 Reset Control Unit (RCU)
7.2.1 Reset Operation
7.2.1.1 Overview
7.2.1.2 Reset Types
7.2.1.3 Reset Sources Overview
7.2.1.4 Warm and Cold Resets
7.2.1.5 EVR Resets and PORST
7.2.1.6 Module Reset Behavior
7.2.1.7 General Reset Operation
7.2.1.8 Reset Generation
7.2.1.9 Shutdown and Reset Delay Timeout Counter (TOUTCNT)
7.2.1.10 Reset Triggers
7.2.1.11 Debug Reset Specific Behavior
7.2.1.12 Module Resets
7.2.1.13 Reset Controller Registers
7.2.2 External Reset Sources and Indications
7.2.2.1 External Service Requests (ESRx)
7.2.3 Boot Software Interface
7.2.3.1 Configuration done with Start-up
7.2.3.2 Start-up Configuration Options
7.2.3.3 Status Registers
7.2.4 NMI Trap Generation
7.2.4.1 Trap Control Registers
7.2.5 RCU Register Address
7.2.6 RCU Kernel Registers
7.3 Power Supply & Power Management Controller (PMC)
7.3.1 Power Supply and Control
7.3.1.1 Introduction
7.3.1.2 Supply Mode and Topology Selection
7.3.1.3 Linear Regulator Mode
7.3.1.4 Step-down Regulator Mode
7.3.1.5 External Supply Modes
7.3.1.6 Components and Layout
7.3.1.7 Voltage Monitoring
7.3.1.8 100 MHz EVR Clock Source
7.3.1.9 Sequence during Power-up and Power-down
7.3.1.10 EVR Control Registers
7.3.2 Power Management
7.3.2.1 Power Management Overview
7.3.2.2 Idle Mode
7.3.2.3 Sleep Mode
7.3.2.4 Standby Mode
7.3.2.5 Power Management Registers
7.3.3 Power Management Register Address
7.3.4 PMC Kernel Registers
7.4 System Control Unit (SCU)
7.4.1 External Request Unit (ERU)
7.4.1.1 Introduction
7.4.1.2 ERU Input Pin Connections
7.4.1.3 External Request Selecter Unit (ERS)
7.4.1.4 Event Trigger Logic (ETL)
7.4.1.5 Connecting Matrix
7.4.1.6 Output Gating Unit (OGU)
7.4.1.7 ERU Output Pin Connections
7.4.1.8 External Request Unit Registers
7.4.2 Lockstep CPU Configuration
7.4.2.1 Logic Monitor Control Registers
7.4.3 Die Temperature Measurement
7.4.3.1 Die Temperature Sensor Register
7.4.4 Watchdog Timers
7.4.4.1 Watchdog Timers Overview
7.4.4.2 Features of the Watchdog Timers
7.4.4.3 The Endinit Functions
7.4.4.4 Timer Operation
7.4.4.5 Watchdog Timer Registers
7.4.5 Emergency Stop Output Control
7.4.5.1 Port Triggered Emergency Stop
7.4.5.2 SMU Event Triggered Emergency Stop
7.4.5.3 Emergency Stop Register
7.4.6 LBIST Support
7.4.6.1 LBIST Control Register
7.4.7 Global Overlay Controls
7.4.7.1 Global Overlay Control
7.4.8 Miscellaneous System Control
7.4.8.1 System Control Register
7.4.8.2 Identification Registers
7.4.8.3 SCU Access Restriction Registers
7.4.9 SCU Register Address
7.4.10 SCU Kernel Registers
8 Memory Test Unit (MTU)
8.1 Memory Content Initialization
8.1.1 Non-Security Applications
8.1.2 Security Applications
8.2 Safety Notifications
8.3 Memory Test Unit (MTU) Kernel Registers
8.3.1 Descriptions
8.3.2 MTU Register Overview
8.4 Memory Controllers
8.4.1 Control and Status Interfaces
8.4.1.1 Direct CPU Interface
8.4.2 Registers
8.4.2.1 MBIST/ECC Registers
8.4.3 Safety Features
8.4.4 Operation Modes
8.4.4.1 Starting a Memory Test Sequence (example)
8.4.4.2 Getting Detailed Memory Test Results
8.4.4.3 Dumping Fail Bitmap
8.4.4.4 Filling a Memory with Defined Contents
8.4.4.5 Reading a Single Memory Location
8.4.4.6 Writing to a Single Memory Location
8.4.5 Memory Controller Register Addresses
8.4.6 Memory Controller Register Overview
8.5 ECC Implementation
8.5.1 ECC
8.5.1.1 ECC Codes
8.5.2 Address Error Detection
8.6 Implementation Section
8.6.1 Memory Control Register Implementation
8.6.1.1 MEMTEST Implementation
8.6.1.2 MEMMAP Implementation
8.6.1.3 MEMSTAT Implementation
8.6.1.4 Memory Controller Instances
9 Safety Management Unit (SMU)
9.1 Introduction
9.2 Features
9.3 Functional Overview
9.4 Functional Description
9.4.1 Reset Types
9.4.2 Interfaces Overview
9.4.2.1 Interfaces to SCU
9.4.2.2 Interfaces to the Interrupt Router
9.4.2.3 Interface to the Ports (Error Pin)
9.4.2.4 Interface to the Safety Flip-Flop Safety Mechanism
9.4.3 SMU Integration Guidelines
9.4.4 Alarm Mapping
9.4.4.1 Pre-alarm Definition
9.4.4.2 Pre-alarm Signals
9.4.4.3 Non-compliant Alarms
9.4.4.4 Internal SMU Alarms
9.4.4.5 Alarm Signals
9.4.5 Alarm Handling
9.4.5.1 Alarm protocol
9.4.5.2 Alarm Configuration
9.4.5.3 Alarm operation
9.4.5.4 Alarm Status Registers
9.4.5.5 Alarm Debug Registers
9.4.5.6 Port Emergency Stop
9.4.5.7 Recovery Timer
9.4.5.8 Watchdog Alarms
9.4.6 SMU Control Interface
9.4.7 SMU state machine
9.4.8 Fault Signaling Protocol (FSP)
9.4.8.1 Introduction
9.4.8.2 Bi-stable fault signaling protocol
9.4.8.3 Time switching protocol
9.4.8.4 FSP Fault State
9.4.8.5 FSP and SMU START State
9.4.9 OCDS Trigger Bus (OTGB) Interface
9.4.10 Register Properties
9.4.10.1 Register Write Protection
9.4.10.2 Safety Flip-Flops
9.5 SMU Module Registers
9.5.1 System Registers description
9.5.2 SMU Configuration Registers
9.5.3 SMU Alarm Configuration Registers
9.5.4 SMU Alarm Configuration Registers (Fault Signaling Protocol)
9.5.5 SMU Alarm Status Registers
9.5.6 SMU Alarm Debug Registers
9.5.7 SMU Special Safety Registers: Register Monitor
10 Program Memory Unit (PMU)
10.1 Generic Feature List
10.2 PMU Configuration of TC27x
10.2.1 Features of the BootROM
10.2.2 Features of the Program and Data Flash
10.2.2.1 Program Flash Features:
10.2.2.2 Data Flash Features
10.3 BootROM
10.4 Tuning Protection
10.5 Flash
10.5.1 Definition of Terms
10.5.2 Flash Structure
10.5.2.1 PFlash
10.5.2.2 DFlash of PMU0
10.5.3 Flash Read Access
10.5.3.1 Read Ports
10.5.3.2 DFlash, BootROM Read Port
10.5.3.3 Configuring Flash Wait Cycles
10.5.3.4 Requested DFlash Read
10.5.4 Flash Operations
10.5.4.1 Modes of Operation
10.5.4.2 Command Sequences
10.5.4.3 HSM Command Interface
10.5.4.4 Command Sequence Definitions
10.5.4.5 Operation Suspend and Resume
10.5.4.6 Programming Voltage Selection
10.5.5 Protection
10.5.5.1 Master Specific Access Control
10.5.5.2 Register Access Control
10.5.5.3 Effective Flash Read Protection
10.5.5.4 Effective Flash Write Protection
10.5.5.5 Configuring Protection in the UCB
10.5.5.6 System Wide Effects of Flash Protection
10.5.6 Data Integrity and Safety
10.5.6.1 SRI ECC (Safe Fetch Path)
10.5.6.2 Flash ECC
10.5.6.3 Margin Checks
10.5.6.4 PMU and Flash Register Supervision
10.5.7 Interrupts and Traps
10.5.8 Reset and Startup
10.5.9 Power Reduction
10.6 Signaling to the Safety Management Unit (SMU)
10.7 Register Set
10.7.1 PMU Registers
10.7.1.1 PMU Identification
10.7.2 Flash Registers
10.7.2.1 Master Specific Access Control
10.7.2.2 Flash Identification Register
10.7.2.3 Flash Status
10.7.2.4 Flash Configuration Control
10.7.2.5 Flash Protection
10.7.2.6 Protection Configuration
10.7.2.7 Flash Read Buffer Configuration
10.7.2.8 Requested Read Interface
10.7.2.9 Flash ECC Access
10.7.2.10 HSM Command Interface
10.7.2.11 HSM Requested Read Interface
10.7.2.12 Margin Check Control
10.7.2.13 Corrected Bits Address Buffer (CBAB)
10.7.2.14 Uncorrectable Bits Address Buffer (UBAB)
10.7.2.15 Direct Flash Communication
10.8 Application Hints
10.8.1 Changes with Respect to Audo Families Audo-NG/F/S/Max
10.8.2 Performing Flash Operations
10.8.3 EEPROM Emulation With DFlash
10.8.3.1 Robust EEPROM Emulation
10.8.4 Handling Errors
10.8.4.1 Handling Errors During Operation
10.8.4.2 Handling Errors During Startup
10.8.5 Resets During Flash Operation
10.8.5.1 General Advice
10.8.5.2 Advice for EEPROM Emulation
10.8.6 ECC
10.8.7 Startup Tests of ECC Logic
10.8.7.1 Testing ECC Alarms and Error Flags
10.8.7.2 Testing the “ECC Monitor”
10.8.7.3 Testing the SMU Alarm of the “ECC Monitor”
10.8.7.4 Testing the “EDC Comparator”
10.8.7.5 General Advice for Startup Tests
11 Local Memory Unit (LMU)
11.1 Feature List
11.2 Local Memory (LMU SRAM)
11.2.1 LMU SRAM Read Buffers
11.3 Memory Protection
11.4 Emulation Memory (EMEM)
11.4.1 EMEM Memory Read Buffers
11.4.2 Access to Emulation Device Register Space
11.5 Error Detection and Signalling
11.5.1 EMEM Read Error
11.5.2 EMEM Write Error
11.5.3 Internal ECC Error
11.5.4 Internal SRAM Read Error
11.5.5 ECC check failure
11.5.6 SRI write access data phase error
11.5.7 SRI access address phase error
11.6 Online Data Acquisition (OLDA) and its Overlay
11.7 Clock Control
11.8 LMU Register Protection
11.9 LMU Registers
12 Data Access Overlay (OVC)
12.1 Data Access Redirection
12.2 Target Memories
12.2.1 Online Data Acquisition (OLDA) Space
12.3 Overlay Memories
12.3.1 Local Memory
12.3.2 Emulation Memory
12.3.3 DSPR & PSPR Memory
12.4 Global Overlay Control
12.4.1 Global Overlay Control Synchronisation
12.5 Overlay Configuration Change
12.6 Access Protection, Attributes, Concurrent Matches
12.7 Overlay Control Registers
12.7.1 Block control registers
12.8 Global overlay control registers
13 General Purpose I/O Ports and Peripheral I/O Lines (Ports)
13.1 Basic Port Operation
13.2 Description Scheme for the Port IO Functions
13.3 Port Register Description
13.3.1 Module Identification Register
13.3.2 Port Input/Output Control Registers
13.3.3 Pad Driver Mode Register
13.3.4 LVDS Pad Control Register
13.3.5 Pin Function Decision Control Register
13.3.6 Pin Controller Select Register
13.3.7 Port Output Register
13.3.8 Port Output Modification Register
13.3.9 Port Output Modification Set Register
13.3.10 Port Output Modification Set Registers x
13.3.11 Port Output Modification Clear Register
13.3.12 Port Output Modification Clear Registers x
13.3.13 Emergency Stop Register
13.3.14 Port Input Register
13.3.15 Access Protection Registers
13.4 Port 00
13.4.1 Port 00 Configuration
13.4.2 Port 00 Function Table
13.4.3 Port 00 Registers
13.4.3.1 Port 00 Output Register
13.4.3.2 Port 00 Output Modification Register
13.4.3.3 Port 00 Output Modification Set Register
13.4.3.4 Port 00 Output Modification Set Register 12
13.4.3.5 Port 00 Output Modification Clear Register
13.4.3.6 Port 00 Output Modification Clear Register 12
13.4.3.7 Port 00 Input/Output Control Register 12
13.4.3.8 Port 00 Input Register
13.4.3.9 Port 00 Pad Driver Mode 1 Register
13.4.3.10 Port 00 Emergency Stop Register
13.4.3.11 Port 00 Pin Controller Select Register
13.5 Port 01
13.5.1 Port 01 Configuration
13.5.2 Port 01 Function Table
13.5.3 Port 01 Registers
13.5.3.1 Port 01 Output Register
13.5.3.2 Port 01 Output Modification Register
13.5.3.3 Port 01 Output Modification Set Register
13.5.3.4 Port 01 Output Modification Set Register 0
13.5.3.5 Port 01 Output Modification Clear Register
13.5.3.6 Port 01 Output Modification Clear Register 0
13.5.3.7 Port 01 Input/Output Control Register 0
13.5.3.8 Port 01 Input Register
13.5.3.9 Port 01 Pad Driver Mode 0 Register
13.5.3.10 Port 01 Emergency Stop Register
13.6 Port 02
13.6.1 Port 02 Configuration
13.6.2 Port 02 Function Table
13.6.3 Port 02 Registers
13.6.3.1 Port 02 Output Register
13.6.3.2 Port 02 Output Modification Register
13.6.3.3 Port 02 Output Modification Set Register
13.6.3.4 Port 02 Output Modification Clear Register
13.6.3.5 Port 02 Input Register
13.6.3.6 P02 Pad Driver Mode 1 Register
13.6.3.7 Port 02 Emergency Stop Register
13.7 Port 10
13.7.1 Port 10 Configuration
13.7.2 Port 10 Function Table
13.7.3 Port 10 Registers
13.7.3.1 Port 10 Output Register
13.7.3.2 Port 10 Output Modification Register
13.7.3.3 Port 10 Output Modification Set Register
13.7.3.4 Port 10 Output Modification Set Register 8
13.7.3.5 Port 10 Output Modification Clear Register
13.7.3.6 Port 10 Output Modification Clear Register 8
13.7.3.7 Port 10 Input/Output Control Register 8
13.7.3.8 Port 10 Input Register
13.7.3.9 Port 10 Pad Driver Mode 1 Register
13.7.3.10 Port 10 Emergency Stop Register
13.8 Port 11
13.8.1 Port 11 Configuration
13.8.2 Port 11 Function Table
13.8.3 Port 11 Registers
13.8.3.1 Port 11 Pin Controller Select Register
13.9 Port 12
13.9.1 Port 12 Configuration
13.9.2 Port 12 Function Table
13.9.3 Port 12 Registers
13.9.3.1 Port 12 Output Register
13.9.3.2 Port 12 Output Modification Register
13.9.3.3 Port 12Output Modification Set Register
13.9.3.4 Port 12 Output Modification Set Register 0
13.9.3.5 Port 12 Output Modification Clear Register
13.9.3.6 Port 12 Output Modification Clear Register 0
13.9.3.7 Port 12 Input/Output Control Register 0
13.9.3.8 Port 12 Input Register
13.9.3.9 Port 12 Pad Driver Mode 0 Register
13.9.3.10 Port 12 Emergency Stop Register
13.10 Port 13
13.10.1 Port 13 Configuration
13.10.2 Port 13 Function Table
13.10.3 Port 13 Registers
13.10.3.1 Port 13 Output Register
13.10.3.2 Port 13 Output Modification Register
13.10.3.3 Port 13 Output Modification Set Register
13.10.3.4 Port 13 Output Modification Clear Register
13.10.3.5 Port 13 Input Register
13.10.3.6 Port 13 Pad Driver Mode 0 Register
13.10.3.7 Port 13 LVDS Pad Control Register
13.10.3.8 Port 13 Emergency Stop Register
13.11 Port 14
13.11.1 Port 14 Configuration
13.11.2 Port 14 Function Table
13.11.3 Port 14 Registers
13.11.3.1 Port 14 Output Register
13.11.3.2 Port 14 Output Modification Register
13.11.3.3 Port 14 Output Modification Set Register
13.11.3.4 Port 14 Output Modification Set Register 8
13.11.3.5 Port 14 Output Modification Clear Register
13.11.3.6 Port 14Output Modification Clear Register 8
13.11.3.7 Port 14 Input/Output Control Register 8
13.11.3.8 Port 14 Input Register
13.11.3.9 Port 14 Pad Driver Mode 1 Register
13.11.3.10 Port 14 Emergency Stop Register
13.12 Port 15
13.12.1 Port 15 Configuration
13.12.2 Port 15 Function Table
13.12.3 Port 15 Registers
13.12.3.1 Port 15 Output Register
13.12.3.2 Port 15 Output Modification Register
13.12.3.3 Port 15 Output Modification Set Register
13.12.3.4 Port 15 Output Modification Set Register 8
13.12.3.5 Port 15 Output Modification Clear Register
13.12.3.6 Port 15 Output Modification Clear Register 8
13.12.3.7 Port 15 Input/Output Control Register 8
13.12.3.8 Port 15 Input Register
13.12.3.9 Port 15 Pad Driver Mode 1 Register
13.12.3.10 Port 15 Emergency Stop Register
13.13 Port 20
13.13.1 Port 20 Configuration
13.13.2 Port 20 Function Table
13.13.3 Port 20 Registers
13.13.3.1 Port 20 Output Register
13.13.3.2 Port 20 Output Modification Register
13.13.3.3 Port 20 Output Modification Set Register
13.13.3.4 Port 20 Output Modification Set Register 0
13.13.3.5 Port 20 Output Modification Set Register 4
13.13.3.6 Port 20 Output Modification Set Register 12
13.13.3.7 Port 20 Output Modification Clear Register
13.13.3.8 Port 20 Output Modification Clear Register 0
13.13.3.9 Port 20 Output Modification Clear Register 4
13.13.3.10 Port 20 Output Modification Clear Register 12
13.13.3.11 Port 20 Input/Output Control Register 0
13.13.3.12 Port 20 Input/Output Control Register 4
13.13.3.13 Port 20 Input/Output Control Register 12
13.13.3.14 Port 20 Input Register
13.13.3.15 Port 20 Pad Driver Mode 0 Register
13.13.3.16 Port 20 Pad Driver Mode 1 Register
13.13.3.17 Port 20 Emergency Stop Register
13.14 Port 21
13.14.1 Port 21 Configuration
13.14.2 Port 21 Function Table
13.14.3 Port 21 Registers
13.14.3.1 Port 21 Output Register
13.14.3.2 Port 21 Output Modification Register
13.14.3.3 Port 21 Output Modification Set Register
13.14.3.4 Port 21 Output Modification Clear Register
13.14.3.5 Port 21 Input Register
13.14.3.6 P21 LVDS Pad Control Register
13.14.3.7 Port 21 Emergency Stop Register
13.15 Port 22
13.15.1 Port 22 Configuration
13.15.2 Port 22 Function Table
13.15.3 Port 22 Registers
13.15.3.1 Port 22 Output Register
13.15.3.2 Port 22 Output Modification Register
13.15.3.3 Port 22 Output Modification Set Register
13.15.3.4 Port 22 Output Modification Clear Register
13.15.3.5 Port 22 Input Register
13.15.3.6 Port 22 Pad Driver Mode 0 Register
13.15.3.7 Port 22 Pad Driver Mode 1 Register
13.15.3.8 Port 22 LVDS Pad Control Register 0
13.15.3.9 Port 22 Emergency Stop Register
13.16 Port 23
13.16.1 Port 23 Configuration
13.16.2 Port 23 Function Table
13.16.3 Port 23 Registers
13.16.3.1 Port 23 Output Register
13.16.3.2 Port 23 Output Modification Register
13.16.3.3 Port 23 Output Modification Set Register
13.16.3.4 Port 23 Output Modification Clear Register
13.16.3.5 Port 23 Input Register
13.16.3.6 Port 23 Emergency Stop Register
13.17 Port 32
13.17.1 Port 32 Configuration
13.17.2 Port 32 Function Table
13.17.3 Port 32 Registers
13.17.3.1 Port 32 Output Register
13.17.3.2 Port 32 Output Modification Register
13.17.3.3 Port 32 Input/Output Control Register 0
13.17.3.4 Port 32 Output Modification Set Register
13.17.3.5 Port 32 Output Modification Clear Register
13.17.3.6 Port 32 Input Register
13.17.3.7 Port 32 Emergency Stop Register
13.18 Port 33
13.18.1 Port 33 Configuration
13.18.2 Port 33 Function Table
13.18.3 Port 33 Registers
13.18.3.1 Port 33 Emergency Stop Register
13.19 Port 34
13.19.1 Port 34 Configuration
13.19.2 Port 34 Function Table
13.19.3 Port 34 Registers
13.19.3.1 Port 34 Output Register
13.19.3.2 Port 34 Output Modification Register
13.19.3.3 Port 34 Output Modification Set Register
13.19.3.4 Port 34 Output Modification Set Register 0
13.19.3.5 Port 34 Output Modification Set Register 4
13.19.3.6 Port 34 Output Modification Clear Register
13.19.3.7 Port 34 Output Modification Clear Register 0
13.19.3.8 Port 34 Output Modification Clear Register 4
13.19.3.9 Port 34 Input/Output Control Register 0
13.19.3.10 Port 34 Input/Output Control Register 4
13.19.3.11 Port 34 Pad Driver Mode 0 Register
13.19.3.12 Port 34 Input Register
13.19.3.13 Port 34 Emergency Stop Register
13.20 Port 40
13.20.1 Port 40 Configuration
13.20.2 Port 40 Function Table
13.20.3 Port 40 Registers
13.20.4 Port 40 Input/Output Control Registers
13.20.5 Port 40 Pin Function Decision Control Register
13.20.6 Port 40 Pin Controller Select Register
14 Direct Memory Access (DMA)
14.1 What is new
14.2 Features
14.3 Block Diagram
14.4 Functional Description
14.4.1 Definition of Terms
14.4.2 DMA Principles
14.4.3 DMA Channel Functionality
14.4.3.1 Shadowed Source or Destination Address
14.4.3.2 DMA Channel Request Control
14.4.3.3 DMA Channel Operation Modes
14.4.3.4 DMA Service Requests
14.4.3.5 Channel Reset Operation
14.4.3.6 Channel Halt Operation
14.4.3.7 Transfer Count and Move Count
14.4.3.8 Circular Buffer
14.4.3.9 Address Counter
14.4.3.10 Flow Control
14.4.3.11 Double Buffering Operation
14.4.3.12 Linked Lists
14.4.3.13 DMA Linked List
14.4.3.14 Accumulated Linked List
14.4.3.15 Safe Linked List
14.4.3.16 Conditional Linked List
14.4.4 Transaction Control Engine
14.4.4.1 Error Conditions
14.4.5 Bus Switch, Bus Switch Priorities
14.4.6 DMA Module Priorities on On Chip Busses
14.4.6.1 On Chip Bus Access Rights, RMW support
14.4.6.2 On Chip Bus Master Interfaces
14.4.7 Pattern Detection
14.4.7.1 Pattern Compare Logic
14.4.7.2 Pattern Detection for 8-bit Data Width
14.4.7.3 Pattern Detection for 16-bit Data Width
14.4.7.4 Pattern Detection for 32-bit Data Width
14.4.8 DMA Configuration Interface
14.4.8.1 DMARAM Channel Control and Status Word
14.4.8.2 DMA Active Channel Write Back
14.4.8.3 DMA Active Channel Shadow Control
14.4.8.4 DMARAM Write Back During Linked List Execution
14.4.9 Interrupt Service Requests
14.4.9.1 Channel Transfer Interrupt Service Request
14.4.9.2 Channel Pattern Detection Interrupt Service Request
14.4.9.3 Channel Wrap Buffer Interrupt Service Request
14.4.9.4 Transaction Request Lost Interrupt Service Request
14.4.9.5 Source and Destination Error Interrupt Service Requests
14.4.9.6 DMA Linked List Error Interrupt Service Request
14.5 Power Modes
14.5.1 Sleep Mode
14.6 Functional Safety Features
14.6.1 Access Protection
14.6.2 Data Integrity
14.6.2.1 DMARAM
14.6.2.2 DMA SRI Read and Write Data
14.7 Debug Features
14.7.1 Channel Suspend Mode
14.7.2 OCDS Trigger Bus (OTGB) Interface
14.7.3 MCDS Trace Interface
14.8 Register Description
14.8.1 DMA General Module Control Registers
14.8.2 DMA Access Protection Registers
14.8.3 DMA Sub-block Error Registers
14.8.4 DMA Sub-block Move Engine Registers
14.8.5 DMA Move Engine Active Channel Registers
14.8.6 DMA OCDS Registers
14.8.7 DMA Pattern Detection Registers
14.8.8 DMA Flow Control Registers
14.8.9 DMA Channel Hardware Resource Registers
14.8.10 DMA Channel Suspend Registers
14.8.11 DMA Transaction State Registers
14.8.12 DMA Transaction Control Set
14.9 Use Cases
15 Flexible CRC Engine (FCE)
15.1 Related documentation
15.2 Features
15.3 Operational overview
15.4 FCE Functional Description
15.4.1 Overview
15.4.2 CRC Operation
15.4.3 Register protection and monitoring methods
15.4.4 FCE interrupts
15.5 Interfaces of the FCE Module
15.6 FCE Module Registers
15.6.1 System Registers description
15.6.2 CRC Kernel Control/Status Registers
15.7 Programming Guide
15.8 Properties of CRC code
16 Interrupt Router (IR)
16.1 Overview
16.2 Features
16.3 Service Request Nodes (SRN)
16.3.1 Service Request Control Registers
16.3.1.1 General Service Request Control Register Format
16.3.1.2 Changing the SRN configuration
16.3.1.3 Protection of the SRC Registers
16.3.1.4 Request Set and Clear Bits (SETR, CLRR)
16.3.1.5 Enable Bit (SRE)
16.3.1.6 Service Request Flag (SRR)
16.3.1.7 Type-Of-Service Control (TOS)
16.3.1.8 Service Request Priority Number (SRPN)
16.3.1.9 ECC Encoding (ECC)
16.3.1.10 Interrupt Trigger Overflow Bit (IOV)
16.3.1.11 Interrupt Trigger Overflow Clear Bit (IOVCLR)
16.3.1.12 SW Sticky Bit (SWS)
16.3.1.13 SW Sticky Clear Bit (SWSCLR)
16.4 Interrupt Control Unit (ICU)
16.4.1 ICU Control Registers
16.4.1.1 Latest Winning Service Request Register (LWSR)
16.4.1.2 Last Acknowledged Service Request Register (LASR)
16.4.1.3 Error Capture Register (ECR)
16.5 General Purpose Service Requests, Service Request Broadcast
16.5.1 General Purpose Service Requests (GPSRxy)
16.5.2 Service Request Broadcast Registers (SRBx)
16.6 System Registers
16.6.1 Register Access Protection (ACCEN1/0)
16.6.2 Kernel Reset Registers (KRST1/0, KRSTCLR)
16.6.3 Clock Control Register (CLC)
16.6.4 OCDS Control and Status Register (OCS)
16.7 Arbitration Process
16.7.1 Number of Clock Cycles per Arbitration Process
16.7.2 Service Request Acknowledge
16.7.3 Handling of detected ECC Errors
16.8 Usage of the TC27x Interrupt System
16.8.1 CPU to ICU Interface
16.8.2 DMA to ICU Interface
16.8.3 Software-Initiated Interrupts
16.8.4 External Interrupts
16.9 Use Case Examples
16.9.1 Use Case Example Interrupt Handler
16.10 Module Implementation
16.10.1 Characteristics of TC27x Interrupt Router Module
16.10.2 Mapping of TC27x Module Service Request Triggers to SRNs
16.10.2.1 Mapping of Service Request Control Registers
16.10.2.2 Interrupts related to the Debug Reset
16.10.2.3 Timing characteristics of Service Request Trigger Signals
16.11 Interrupt Router System and Module Registers
16.11.1 System and ICU Control Registers
16.12 OTGM Registers
16.12.1 Status and Control
16.12.2 IRQ MUX Control
16.12.3 Interrupt System Trace
16.12.4 MCDS Interface
16.13 Interrupt Router SRC Registers
17 System Timer (STM)
17.1 Overview
17.2 Operation
17.2.1 Compare Register Operation
17.2.2 Compare Match Interrupt Control
17.2.3 Using Multiple STMs
17.2.4 STM as Reset Trigger
17.3 STM Registers
17.3.1 Clock Control Register
17.3.2 Timer/Capture Registers
17.3.3 Compare Registers
17.3.4 Interrupt Registers
17.3.5 Interface Registers
18 Asynchronous/Synchronous Interface (ASCLIN)
18.1 Feature List
18.2 Overview
18.3 External Signals
18.4 User Interface
18.4.1 TxFIFO Overview
18.4.2 Using the TxFIFO
18.4.2.1 Standard ASC Mode
18.4.2.2 High Speed ASC Mode
18.4.2.3 LIN Mode
18.4.2.4 SPI Mode
18.4.3 RxFIFO Overview
18.4.4 Using the RxFIFO
18.4.4.1 Standard ASC Mode
18.4.4.2 High Speed ASC Mode
18.4.4.3 LIN Mode
18.4.4.4 SPI Mode
18.4.5 RTS / CTS Handshaking
18.5 Clock System
18.5.1 Baud Rate Generation
18.5.2 Bit Timing Properties
18.6 Data Frame Configuration
18.7 Miscellaneous Configuration
18.8 Synchronous Mode
18.8.1 Baud Rate and Clock Generation
18.8.2 Data Frame Configuration
18.8.3 Slave Selects Configuration
18.8.4 Miscellaneous Configuration
18.9 LIN Support
18.9.1 LIN Watchdog
18.9.1.1 LIN Break, Wake, Stuck Handling
18.9.1.2 LIN Header and Response Timers
18.9.2 LIN Master Sequences
18.9.3 LIN Slave Sequences
18.9.4 Using the ENI and HO Bits
18.9.5 LIN Error Recovery
18.9.6 LIN Sleep and LIN Wake-Up
18.10 Auto Baud Rate Detection
18.11 Collision Detection
18.12 LIN Protocol Control
18.13 Interrupts
18.14 Digital Glitch Filter
18.15 Suspend, Sleep and Power-Off Behavior
18.15.1 OCDS Suspend
18.15.2 Sleep Mode
18.15.3 Disable Request (Power-Off)
18.16 Reset Behavior
18.17 Use Case Example ASC Interface
18.18 Kernel Registers
18.18.1 Kernel Registers
18.19 Implementation
18.19.1 BPI_FPI Module Registers
18.19.1.1 System Registers
18.20 On-Chip Connections
18.21 ASC at CAN Support
19 Queued Synchronous Peripheral Interface (QSPI)
19.1 Feature List
19.2 Overview
19.2.1 External Signals
19.2.2 Operating Modes
19.2.3 Queue Support Overview
19.2.4 Architecture Overview
19.2.5 Three Wire Connection
19.3 Abstract Overview
19.4 Frequency Domains
19.5 Master Mode State Machine
19.5.1 Phases of one Communication Cycle
19.5.2 Configuration Extensions
19.5.3 Details of the Baud Rate and Phase Duration Control
19.5.4 Calculation of the Baud Rates and the Delays
19.5.5 State Diagram of Standard Communication Cycle
19.5.6 Expect Phase
19.5.7 External Slave Select Expansion
19.6 User Interface
19.6.1 Transmit and Receive FIFOs
19.6.1.1 Short Data Mode
19.6.1.2 Long Data Mode
19.6.1.3 Continuous Data Mode
19.6.1.4 Single Configuration - Multiple Frames Behavior
19.6.1.5 Big Endian Data Format
19.6.2 Loop-Back Mode
19.7 Interrupts
19.7.1 Slave Mode SLSI Interrupt
19.7.2 Interrupt Flags Behavior
19.7.3 TXFIFO Interrupt Generation
19.7.4 RXFIFO Interrupt Generation
19.7.5 DMA Transfer Example
19.8 Slave Mode
19.8.1 Shift Clock Phase and Polarity in Slave Mode
19.8.2 Shift Clock Monitoring
19.8.2.1 Baud Rate Error Detection
19.8.2.2 Spike Detection
19.8.2.3 Shift Clock Monitor Flags
19.8.3 Parity
19.9 Kernel Registers
19.9.1 Kernel Registers
19.10 Operation Modes
19.10.1 OCDS Suspend
19.10.2 Sleep Mode
19.10.3 Disabling the QSPI
19.11 Reset Behavior
19.12 QSPI Module Implementation
19.12.1 Module Identification Registers
19.12.2 Interfaces of the QSPI Modules
19.12.3 On-Chip Connections
19.12.4 QSPI Related External Registers
19.12.4.1 BPI_FPI Module Registers
19.12.4.2 Interrupt Control Registers
20 High Speed Serial Link (HSSL)
20.1 Lower communication layers module (HSCT)
20.2 HSSL Protocol Definition
20.2.1 List of Abbreviations, Acronyms, and Term Definitions
20.2.2 Frame Types
20.2.2.1 Frame and Payload Lengths
20.2.2.2 Data Types
20.2.2.3 Cyclic Redundancy Check Field - CRC
20.2.2.4 Header Structure
20.2.3 Single and Block Transfers
20.2.4 Streaming Interface
20.2.5 Sliding Window Protocol
20.2.6 Error Management
20.2.7 Shift Direction
20.3 HSSL Implementation
20.4 Overview
20.4.1 HSSL Module Operation
20.4.1.1 Frame Transmission Priorisation
20.4.1.2 Received Frame Management and Command Execution
20.4.2 HSSL Channel Architecture
20.4.3 Acknowledge Responses
20.4.4 Cross Dependencies Between the Frame Types
20.4.5 Command Timeout
20.4.5.1 Command Timeout Operation
20.4.6 Stream Timeout
20.4.6.1 Stream Timeout Operation
20.4.7 Data FIFOs of the Streaming Channel 2
20.5 Modes of Operation
20.6 Interrupts
20.7 Operating a Command Channel
20.7.1 Initiating a Single Write Command
20.7.2 Initiating a Single Read Command
20.7.3 Initiating a Single Trigger Command
20.7.4 DMA Operated Command Queues
20.7.5 Receiver Error Handling
20.7.5.1 Timeout Error
20.7.5.2 Transaction Tag Error
20.7.6 Global Error
20.8 Memory Block Transfer Modes of the Stream Channel
20.9 HSSL Reset
20.10 OCDS SRI / SPB Master Suspend
20.11 OCDS Trigger Sets
20.12 Access Protection
20.13 Kernel Registers
20.13.1 Global Registers
20.13.2 Channel.Flags Registers
20.13.3 Channel.Initiator Registers
20.13.4 Channel.Target Registers
20.13.5 Initiator Stream Registers
20.13.6 Target Stream Registers
20.13.7 Access Protection Registers
20.14 Module Implementation
20.14.1 BPI_SPB Module Registers
20.14.1.1 System Registers
20.15 High Speed Communication Tunnel (HSCT)
20.15.1 Overview
20.15.1.1 Features
20.15.2 Functional Description
20.15.2.1 Introduction
20.15.2.2 Physical Layer
20.15.2.3 Electrical Characteristics Based on LVDS for Reduced Link trace length
20.15.2.4 Protocol Layer
20.15.3 Use Cases
20.15.3.1 MC to ASIC
20.15.3.2 MC to FPGA
20.15.3.3 MC to MC
20.15.4 HSCT Register Description
20.15.4.1 Registers Definition
20.15.5 Suspend, Sleep and Power-Off Behavior
20.15.5.1 OCDS Suspend
20.15.5.2 Sleep Mode
20.15.5.3 Disable Request (Power-Off)
20.15.6 References
21 Micro Second Channel (MSC)
21.1 MSC Kernel Description
21.1.1 Overview
21.1.2 Downstream Channel
21.1.2.1 Frame Formats and Definitions
21.1.2.2 Shift Register Operation
21.1.2.3 External Signal Injection
21.1.2.4 Transmission Modes
21.1.2.5 Downstream Counter and Enable Signals
21.1.2.6 Baud Rate
21.1.2.7 Abort of Frames
21.1.3 Upstream Channel
21.1.3.1 Data Frames
21.1.3.2 Parity Checking
21.1.3.3 Data Reception
21.1.3.4 Baud Rate
21.1.3.5 Spike Filter
21.1.3.6 Upstream Timer
21.1.4 I/O Control
21.1.4.1 Downstream Channel Output Control
21.1.4.2 Upstream Channel
21.1.5 MSC Interrupts
21.1.5.1 Data Frame Interrupt
21.1.5.2 Command Frame Interrupt
21.1.5.3 Time Frame Finished Interrupt
21.1.5.4 Receive Data Interrupt
21.1.5.5 Interrupt Request Compressor
21.2 ABRA (Asynchronous Baud Rate Adjustment Block)
21.2.1 Overview
21.2.2 Timings Issues
21.2.3 Adjusting the Passive Phase of a Frame
21.2.4 Jitter of the Downstream Frames
21.2.4.1 Jitter in Active Phase Clock Mode
21.2.4.2 Jitter in Continuous Clock Mode
21.2.5 Interrupt Position with the ABRA Block
21.2.6 Configuring the ABRA block
21.2.7 Implementation Issues
21.2.8 ABRA Disable, Sleep and Suspend Behavior
21.2.8.1 Disable and Sleep Behavior
21.2.8.2 OCDS Suspend Behavior
21.3 MSC Kernel Registers
21.3.1 Module Identification Register
21.3.2 Status and Control Registers
21.3.3 Data Registers
21.3.4 Extension Registers
21.3.5 Asynchronous Block Registers
21.4 MSC Module Implementation
21.4.1 Module Identification Registers
21.4.2 BPI_FPI Module Registers (Single Kernel Configuration)
21.4.2.1 System Registers
21.4.3 Interface Connections of the MSC Module
21.4.4 MSC Module-Related External Registers
21.4.5 Clock Control
21.4.5.1 Clock Control Without the ABRA Block
21.4.5.2 Clock Control when using the ABRA Block
21.4.5.3 Fractional Divider Register
21.4.6 Port Control
21.4.7 On-Chip Connections
21.4.7.1 EMGSTOPMSC Signal (from SCU)
21.4.7.2 Interrupt Service Requests
21.4.7.3 Connections to Ports / Pins
21.4.7.4 GTM Connections
21.5 Use Case Example Micro Second Channel (MSC)
22 Controller Area Network Controller (MultiCAN+)
22.1 CAN Basics
22.1.1 Addressing and Bus Arbitration
22.1.2 CAN Frame Formats
22.1.3 CAN Frame Types
22.1.3.1 Data Frames
22.1.3.2 Remote Frames
22.1.3.3 Error Frames
22.1.3.4 Overload Frame
22.1.4 The Nominal Bit Time
22.1.4.1 CAN FD bit timing
22.1.5 Error Detection and Error Handling
22.2 Overview
22.2.1 Features List
22.3 CAN Flexible Data-Rate (CAN FD)
22.3.1 Transmitter Delay Compensation
22.4 MultiCAN+ Kernel Functional Description
22.4.1 Module Structure
22.4.2 Clock Control
22.4.3 Port Input Control
22.4.4 OCDS Suspend
22.4.5 OCDS Trigger Bus (OTGB) Interface
22.4.6 CAN Node Control
22.4.6.1 Bit Timing Unit
22.4.6.2 Bitstream Processor
22.4.6.3 Error Handling Unit
22.4.6.4 CAN Frame Counter
22.4.6.5 Node Timing Functions
22.4.6.6 CAN Node Interrupts
22.4.7 Message Object List Structure
22.4.7.1 Basics
22.4.7.2 List of Unallocated Elements
22.4.7.3 Connection to the CAN Nodes
22.4.7.4 List Command Panel
22.4.8 CAN Node Analyzer Mode
22.4.8.1 Analyzer Mode
22.4.8.2 Loop-Back Mode
22.4.8.3 Bit Timing Analysis
22.4.9 Message Acceptance Filtering
22.4.9.1 Receive Acceptance Filtering
22.4.9.2 Transmit Acceptance Filtering
22.4.10 Message Postprocessing
22.4.10.1 Message Object Interrupts
22.4.10.2 Pending Messages
22.4.11 Message Object Data Handling
22.4.11.1 Frame Reception
22.4.11.2 Frame Transmission
22.4.12 Message Object Functionality
22.4.12.1 Standard Message Object
22.4.12.2 Single Data Transfer Mode
22.4.12.3 Single Transmit Trial
22.4.12.4 Message Object Format (Classical CAN & CAN FD)
22.4.12.5 Message Object FIFO Structure
22.4.12.6 Receive FIFO
22.4.12.7 Transmit FIFO
22.4.12.8 Gateway Mode
22.4.12.9 Foreign Remote Requests
22.4.12.10 CAN FD - 64 byte Messages
22.4.13 Measurement for Oscillator Calibration
22.5 Use Case Example MultiCAN+
22.6 MultiCAN+ Kernel Registers
22.6.1 Global Module Registers
22.6.2 CAN Node Registers
22.6.3 Message Object Registers
22.7 MultiCAN+ Module Implementation
22.7.1 Interfaces of the MultiCAN+ Module
22.7.2 MultiCAN+ Module External Registers
22.7.2.1 System Registers
22.7.3 MultiCAN+ Clock Interconnects With SCU
22.7.4 Module Clock Generation
22.7.4.1 Clock Selection
22.7.4.2 Fractional Divider
22.7.5 Port and I/O Line Control
22.7.5.1 Input/Output Function Selection in Ports
22.7.5.2 Node Receive Input Selection
22.7.5.3 CAN Transmit Trigger Inputs
22.7.5.4 Connections to Interrupt Router Inputs
22.7.5.5 Connections to General Timer Module (GTM) Inputs
22.7.6 Interrupt Control
22.7.7 MultiCAN+ Module Register Address Map
22.8 MultiCAN+ Soft Configuration
22.9 Revision history
23 Single Edge Nibble Transmission (SENT)
23.1 SENT Kernel Description
23.1.1 Overview
23.1.2 General Operation
23.1.2.1 Definitions
23.1.3 Standard SENT Operation
23.1.3.1 Frame Formats and Definitions
23.1.4 SPC Operation
23.1.4.1 Synchronous Transmission
23.1.4.2 Range Selection
23.1.4.3 ID Selection
23.1.4.4 Bidirectional Transmit Mode
23.1.4.5 SPC Timing
23.1.4.6 Abort of Frames
23.1.5 Baud Rate Generation
23.1.6 Error Detection Capabilities
23.1.7 Digital Glitch Filter
23.1.8 Interrupts
23.1.9 Trigger Outputs
23.2 SENT Kernel Registers
23.2.1 Module Control
23.2.2 Channel Baud Rate Registers
23.2.3 Receiver Control and Status Registers
23.2.4 Input and Output Control
23.2.5 Receive Data Registers
23.2.6 SPC Control
23.2.7 Interrupt Control Registers
23.3 SENT Module Implementation
23.3.1 Interface Connections of the SENT Module
23.3.1.1 On-Chip Connections
23.3.1.2 Interrupt and DMA Controller Service Requests
23.3.2 SENT Module-Related External Registers
23.3.2.1 Port Control
23.3.3 BPI_FPI Module Registers
23.4 Revision History
24 FlexRay™ Protocol Controller (E-Ray)
24.1 E-Ray Kernel Description
24.2 Overview
24.3 Definitions
24.4 Block Diagram
24.5 Programmer’s Model
24.5.1 Register Map
24.5.2 E-Ray Kernel Registers
24.5.2.1 Customer Registers
24.5.2.2 Special Registers
24.5.2.3 Service Request Registers
24.5.2.4 Communication Controller Control Registers
24.5.2.5 Communication Controller Status Registers
24.5.2.6 Message Buffer Control Registers
24.5.2.7 Message Buffer Status Registers
24.5.2.8 Identification Registers
24.5.2.9 Input Buffer
24.5.2.10 Output Buffer
24.6 Functional Description
24.6.1 Communication Cycle
24.6.1.1 Static Segment
24.6.1.2 Dynamic Segment
24.6.1.3 Symbol Window
24.6.1.4 Network Idle Time (NIT)
24.6.1.5 Configuration of Network Idle Time (NIT) Start and Offset Correction Start
24.6.2 Communication Modes
24.6.3 Clock Synchronization
24.6.3.1 Global Time
24.6.3.2 Local Time
24.6.3.3 Synchronization Process
24.6.3.4 External Clock Synchronization
24.6.4 Error Handling
24.6.4.1 Clock Correction Failed Counter
24.6.4.2 Passive to Active Counter
24.6.4.3 HALT Command
24.6.4.4 FREEZE Command
24.6.5 Communication Controller States
24.6.5.1 Communication Controller State Diagram
24.6.5.2 DEFAULT_CONFIG State
24.6.5.3 MONITOR_MODE
24.6.5.4 READY State
24.6.5.5 WAKEUP State
24.6.5.6 STARTUP State
24.6.5.7 Startup Time-outs
24.6.5.8 Path of leading Coldstart Node (initiating coldstart)
24.6.5.9 NORMAL_ACTIVE State
24.6.5.10 NORMAL_PASSIVE State
24.6.5.11 HALT State
24.6.6 Network Management
24.6.7 Filtering and Masking
24.6.7.1 Frame ID Filtering
24.6.7.2 Channel ID Filtering
24.6.7.3 Cycle Counter Filtering
24.6.7.4 FIFO Filtering
24.6.8 Transmit Process
24.6.8.1 Static Segment
24.6.8.2 Dynamic Segment
24.6.8.3 Transmit Buffers
24.6.8.4 Frame Transmission
24.6.8.5 NULL Frame Transmission
24.6.9 Receive Process
24.6.9.1 Frame Reception
24.6.9.2 NULL Frame reception
24.6.10 FIFO Function
24.6.10.1 Description
24.6.10.2 Configuration of the FIFO
24.6.10.3 Access to the FIFO
24.6.11 Message Handling
24.6.11.1 Host access to Message RAM
24.6.11.2 Data Transfers between IBF / OBF and Message RAM
24.6.11.3 Minimum fCLC_ERAY
24.6.11.4 FlexRay™ Protocol Controller access to Message RAM
24.6.12 Message RAM
24.6.12.1 Header Partition
24.6.12.2 Data Partition
24.6.12.3 ECC Check
24.6.13 Host Handling of Errors
24.6.13.1 Self-Healing
24.6.13.2 CLEAR_RAMS Command
24.6.13.3 Temporary Unlocking of Header Section
24.7 Module Service Request
24.8 Restrictions
24.8.1 Message Buffers with the same Frame ID
24.8.2 Data Transfers between IBF / OBF and Message RAM
24.9 E-Ray Module Implementation
24.9.1 Interconnections of the E-Ray Module
24.9.2 Port Control and Connections
24.9.2.1 Input/Output Function Selection
24.9.3 On-Chip Connections
24.9.3.1 E-Ray Connections with IR
24.9.3.2 E-Ray Connections with SMU
24.9.3.3 E-Ray Connections with the External Request Unit of SCU
24.9.3.4 E-Ray Connections to GTM
24.9.3.5 E-Ray Connections with the External Clock Output of SCU
24.9.4 OCDS Trigger Bus (OTGB) Interface
24.9.5 OTGB E-Ray Registers
24.9.5.1 OCDS Trigger Bus (OTGB)
24.9.6 BPI_FPI Module Registers
24.9.7 Interrupt Registers
24.10 Revision History
25 Generic Timer Module (GTM)
25.1 Introduction
25.1.1 Overview
25.1.2 Document Structure
25.2 GTM Architecture
25.2.1 Overview
25.2.1.1 GTM Architecture Block Diagram
25.2.1.2 ARU Data Word Description
25.2.1.3 GTM signal multiplex
25.2.2 GTM Interfaces
25.2.2.1 GTM Generic Bus Interface (AEI)
25.2.2.2 GTM Multi-master and multi-tasking support
25.2.3 ARU Routing Concept
25.2.3.1 Principle of data routing using ARU
25.2.3.2 ARU Round Trip Time
25.2.3.3 ARU Blocking Mechanism
25.2.4 GTM Clock and Time Base Management (CTBM)
25.2.4.1 GTM Clock and time base management architecture
25.2.5 GTM Interrupt Concept
25.2.5.1 Level interrupt mode
25.2.5.2 Pulse interrupt mode
25.2.5.3 Pulse-notify interrupt mode
25.2.5.4 Single-pulse interrupt mode
25.2.5.5 GTM Interrupt concentration method
25.2.6 GTM Software Debugger Support
25.2.6.1 Register behaviour in case of Software Debugger accesses
25.2.7 GTM Programming conventions
25.2.8 GTM TOP-Level Configuration Registers Overview
25.2.9 GTM TOP-Level Configuration Registers Description
25.2.9.1 Register GTM_REV
25.2.9.2 Register GTM_RST
25.2.9.3 Register GTM_CTRL
25.2.9.4 Register GTM_AEI_ADDR_XPT
25.2.9.5 Register GTM_IRQ_NOTIFY
25.2.9.6 Register GTM_IRQ_EN
25.2.9.7 Register GTM_IRQ_FORCINT
25.2.9.8 Register GTM_IRQ_MODE
25.2.9.9 Register GTM_BRIDGE_MODE
25.2.9.10 Register GTM_BRIDGE_PTR1
25.2.9.11 Register GTM_BRIDGE_PTR2
25.2.9.12 Register GTM_EIRQ_EN
25.2.9.13 Register GTM_TIMi_AUX_IN_SRC (i= 0…n)
25.3 Advanced Routing Unit (ARU)
25.3.1 Overview
25.3.2 Special Data Sources
25.3.3 ARU Access via AEI
25.3.3.1 Default ARU Access
25.3.3.2 Debug Access
25.3.4 ARU Interrupt Signals
25.3.5 ARU Configuration Registers Overview
25.3.6 ARU Configuration Registers Description
25.3.6.1 Register ARU_ACCESS
25.3.6.2 Register ARU_DATA_H
25.3.6.3 Register ARU_DATA_L
25.3.6.4 Register ARU_DBG_ACCESS0
25.3.6.5 Register ARU_DBG_DATA0_H
25.3.6.6 Register ARU_DBG_DATA0_L
25.3.6.7 Register ARU_DBG_ACCESS1
25.3.6.8 Register ARU_DBG_DATA1_H
25.3.6.9 Register ARU_DBG_DATA1_L
25.3.6.10 Register ARU_IRQ_NOTIFY
25.3.6.11 Register ARU_IRQ_EN
25.3.6.12 Register ARU_IRQ_FORCINT
25.3.6.13 Register ARU_IRQ_MODE
25.4 Broadcast Module (BRC)
25.4.1 Overview
25.4.2 BRC Configuration
25.4.3 BRC Interrupt Signals
25.4.4 BRC Configuration Registers Overview
25.4.5 BRC Configuration Registers Description
25.4.5.1 Register BRC_SRCx_ADDR (x=0-11)
25.4.5.2 Register BRC_SRCx_DEST (x:0…11)
25.4.5.3 Register BRC_IRQ_NOTIFY
25.4.5.4 Register BRC_IRQ_EN
25.4.5.5 Register BRC_IRQ_FORCINT
25.4.5.6 Register BRC_IRQ_MODE
25.4.5.7 Register BRC_RST
25.4.5.8 Register BRC_EIRQ_EN
25.5 First In First Out Module (FIFO)
25.5.1 Overview
25.5.2 Operation Modes
25.5.2.1 Normal Operation Mode
25.5.2.2 Ring Buffer Operation Mode
25.5.3 FIFO Interrupt Signals
25.5.4 FIFOi Configuration Registers Overview
25.5.5 FIFOi Configuration Registers Description
25.5.5.1 Register FIFOi_CHx_CTRL (x:0…7)
25.5.5.2 Register FIFOi_CHx_END_ADDR (x:0…7)
25.5.5.3 Register FIFOi_CHx_START_ADDR (x:0…7)
25.5.5.4 Register FIFOi_CHx_UPPER_WM (x:0…7)
25.5.5.5 Register FIFOi_CHx_LOWER_WM (x:0…7)
25.5.5.6 Register FIFOi_CHx_STATUS (x:0…7)
25.5.5.7 Register FIFOi_CHx_FILL_LEVEL (x:0…7)
25.5.5.8 Register FIFOi_CHx_WR_PTR (x:0…7)
25.5.5.9 Register FIFOi_CHx_RD_PTR (x:0…7)
25.5.5.10 Register FIFOi_CHx_IRQ_NOTIFY (x:0…7)
25.5.5.11 Register FIFOi_CHx_IRQ_EN (x:0…7)
25.5.5.12 Register FIFOi_CHx_IRQ_FORCINT
25.5.5.13 Register FIFOi_CHx_IRQ_MODE
25.5.5.14 Register FIFOi_CHx_EIRQ_EN (x:0…7)
25.6 AEI to FIFO Data Interface (AFD)
25.6.1 Overview
25.6.2 AFD Register overview
25.6.3 AFD Register description
25.6.3.1 Register AFD0_CHx_BUF_ACC (x:0…7)
25.7 FIFO to ARU Unit (F2A)
25.7.1 Overview
25.7.2 Transfer modes
25.7.2.1 Data transfer of both ARU words between ARU and FIFO
25.7.3 F2A Configuration Registers Overview
25.7.4 F2A Configuration Registers description
25.7.4.1 Register F2Ai_ENABLE
25.7.4.2 Register F2Ai_CHx_ARU_RD_FIFO (x: 0…7)
25.7.4.3 Register F2Ai_CHx_STR_CFG (x: 0…7)
25.8 Clock Management Unit (CMU)
25.8.1 Overview
25.8.1.1 CMU Block Diagram
25.8.2 Global Clock Divider
25.8.3 Configurable Clock Generation Subunit (CFGU)
25.8.4 Wave Form of Generated Clock Signal CMU_CLK[x]
25.8.5 Fixed Clock Generation (FXU)
25.8.6 External Generation Unit (EGU)
25.8.7 CMU Configuration Registers Overview
25.8.8 CMU Configuration Register Description
25.8.8.1 Register CMU_CLK_EN
25.8.8.2 Register CMU_GCLK_NUM
25.8.8.3 Register CMU_GCLK_DEN
25.8.8.4 Register CMU_CLK_x_CTRL (x:0…5)
25.8.8.5 Register CMU_CLK_6_CTRL
25.8.8.6 Register CMU_CLK_7_CTRL
25.8.8.7 Register CMU_ECLK_z_NUM (z:0…2)
25.8.8.8 Register CMU_ECLK_z_DEN (z:0…2)
25.8.8.9 Register CMU_FXCLK_CTRL
25.9 Time Base Unit (TBU)
25.9.1 Overview
25.9.1.1 TBU Block Diagram
25.9.2 TBU Time Base Channels
25.9.2.1 TBU Channel Modes
25.9.3 TBU Configuration Registers Overview
25.9.4 TBU Registers description
25.9.4.1 Register TBU_CHEN
25.9.4.2 Register TBU_CH0_CTRL
25.9.4.3 Register TBU_CH0_BASE
25.9.4.4 Register TBU_CHy_CTRL (y:1, 2)
25.9.4.5 Register TBU_CHy_BASE (y:1,2)
25.10 Timer Input Module (TIM)
25.10.1 Overview
25.10.1.1 TIM Block Diagram
25.10.1.2 Input source selection INPUTSRCx
25.10.1.3 External capture source selection EXTCAPSRCx
25.10.2 TIM Filter Functionality (FLT)
25.10.2.1 Overview
25.10.2.2 TIM Filter Modes
25.10.2.3 TIM Filter reconfiguration
25.10.3 Timeout Detection Unit (TDU)
25.10.3.1 Architecture of the TDU Subunit
25.10.4 TIM Channel Architecture
25.10.4.1 Overview
25.10.4.2 TIM Channel Modes
25.10.5 MAP Submodule Interface
25.10.6 TIM Interrupt Signals
25.10.7 TIM Configuration Registers Overview
25.10.8 TIM Configuration Registers Description
25.10.8.1 Register TIMi_CHx_CTRL (x:0….7) (i: 13)
25.10.8.2 Register TIM0_CHx_CTRL (x:0…7)
25.10.8.3 Register TIMi_CHx_FLT_RE (i:0…3)(x:0…7)
25.10.8.4 Register TIMi_CHx_FLT_FE (i:0…3)(x:0…7)
25.10.8.5 Register TIMi_CHx_TDU (i:0…3)(x:0…7)
25.10.8.6 Register TIMi_CHx_GPR0 (i:0…3)(x:0…7)
25.10.8.7 Register TIMi_CHx_GPR1 (i:0…3)(x:0…7)
25.10.8.8 Register TIMi_CHx_CNT (i:0…3)(x:0…7)
25.10.8.9 Register TIMi_CHx_CNTS (i:0…3)(x:0…7)
25.10.8.10 Register TIMi_CHx_IRQ_NOTIFY (i:0…3)(x:0…7)
25.10.8.11 Register TIMi_CHx_IRQ_EN (i:0…3)(x:0…7)
25.10.8.12 Register TIMi_CHx_IRQ_FORCINT (i:0…3)(x:0…7)
25.10.8.13 Register TIMi_CHx_IRQ_MODE (i:0…3)(x:0…7)
25.10.8.14 Register TIMi_RST (i:0…3)
25.10.8.15 Register TIMi_IN_SRC (i:0…3)
25.10.8.16 Register TIMi_CHx_EIRQ_EN (i:0…3)(x:0…7)
25.10.8.17 Register TIMi_CHx_TDUV (i:0…3)(x:0…7)
25.10.8.18 Register TIMi_CHx_TDUC (i:0…3)(x:0…7)
25.10.8.19 Register TIMi_CHx_ECNT (i:0…3)(x:0…7)
25.10.8.20 Register TIMi_CHx_ECTRL (i:0…3)(x:0…7)
25.11 Timer Output Module (TOM)
25.11.1 Overview
25.11.1.1 TOM Block diagram
25.11.2 TOM Global Channel Control (TGC0, TGC1)
25.11.2.1 Overview
25.11.2.2 TGC Subunit
25.11.3 TOM Channel (TOM_CH[x])
25.11.3.1 TOM Channel 0…7 architecture
25.11.3.2 TOM Channel 8…14 architecture
25.11.3.3 TOM Channel 15 architecture for PCM generation
25.11.3.4 Duty cycle, period and selected counter clock frequency update mechanisms
25.11.3.5 TOM continuous mode
25.11.3.6 TOM One shot mode
25.11.3.7 Pulse count modulation
25.11.4 TOM BLDC Support
25.11.5 TOM Gated Counter Mode
25.11.6 TOM Interrupt signals
25.11.7 TOM Configuration Register overview
25.11.8 TOM Configuration Registers Description
25.11.8.1 Register TOMi_TGC0_GLB_CTRL
25.11.8.2 Register TOMi_TGC0_ENDIS_CTRL
25.11.8.3 Register TOMi_TGC0_ENDIS_STAT
25.11.8.4 Register TOMi_TGC0_ACT_TB
25.11.8.5 Register TOMi_TGC0_OUTEN_CTRL
25.11.8.6 Register TOMi_TGC0_OUTEN_STAT
25.11.8.7 Register TOMi_TGC0_FUPD_CTRL
25.11.8.8 Register TOMi_TGC0_INT_TRIG
25.11.8.9 Register TOMi_CHx_CTRL (x:0…14)
25.11.8.10 Register TOMi_CH15_CTRL
25.11.8.11 Register TOMi_CHx_CN0 (x:0…15)
25.11.8.12 Register TOMi_CHx_CM0 (x:0…15)
25.11.8.13 Register TOMi_CHx_SR0 (x:0…15)
25.11.8.14 Register TOMi_CHx_CM1 (x:0…15)
25.11.8.15 Register TOMi_CHx_SR1 (x:0…15)
25.11.8.16 Register TOMi_CHx_STAT (x:0…15)
25.11.8.17 Register TOMi_CHx_IRQ_NOTIFY (x:0…15)
25.11.8.18 Register TOMi_CHx_IRQ_EN (x:0…15)
25.11.8.19 Register TOMi_CHx_IRQ_FORCINT (x:0…15)
25.11.8.20 Register TOMi_CHx_IRQ_MODE (x:0…15)
25.12 ARU-connected Timer Output Module (ATOM)
25.12.1 Overview
25.12.1.1 ATOM Block diagram
25.12.1.2 ATOM Global control (AGC)
25.12.1.3 ATOM Channel mode overview
25.12.2 ATOM Channel architecture
25.12.2.1 ATOM Channel architecture
25.12.2.2 ARU Communication Interface
25.12.3 ATOM Channel modes
25.12.3.1 ATOM Signal Output Mode Immediate (SOMI)
25.12.3.2 ATOM Signal Output Mode Compare (SOMC)
25.12.3.3 ATOM Signal Output Mode PWM (SOMP)
25.12.3.4 ATOM Signal Output Mode Serial (SOMS)
25.12.4 ATOM Interrupt signals
25.12.5 ATOM Register overview
25.12.6 ATOM Register description
25.12.6.1 Register ATOMi_AGC_GLB_CTRL
25.12.6.2 Register ATOMi_CHx_CTRL (x: 0…7)
25.12.6.3 Register ATOMi_CHx_STAT (x: 0…7)
25.12.6.4 Register ATOMi_CHx_RDADDR (x: 0…7)
25.12.6.5 Register ATOMi_CHx_CN0 (x: 0…7)
25.12.6.6 Register ATOMi_CHx_CM0 (x: 0…7)
25.12.6.7 Register ATOMi_CHx_SR0 (x: 0…7)
25.12.6.8 Register ATOMi_CHx_CM1 (x: 0…7)
25.12.6.9 Register ATOMi_CHx_SR1 (x: 0…7)
25.12.6.10 Register ATOMi_CHx_IRQ_NOTIFY (x:0…7)
25.12.6.11 Register ATOMi_CHx_IRQ_EN (x:0…7)
25.12.6.12 Register ATOMi_CHx_IRQ_FORCINT (x:0…7)
25.12.6.13 Register ATOMi_CHx_IRQ_MODE (x:0…7)
25.13 Multi Channel Sequencer (MCS)
25.13.1 Overview
25.13.1.1 Architecture
25.13.1.2 Scheduling
25.13.2 Instruction Set
25.13.2.1 Instruction Format
25.13.2.2 Data Transfer Instructions
25.13.2.3 ARU Instructions
25.13.2.4 Arithmetic Logic Instructions
25.13.2.5 Test Instructions
25.13.2.6 Control Flow Instructions
25.13.2.7 Other Instructions
25.13.3 MCS Internal Registers
25.13.3.1 MCS Internal Registers Overview
25.13.3.2 General purpose register Rx (x:0…7)
25.13.3.3 Register STA
25.13.3.4 Register ACB
25.13.3.5 Register CTRG
25.13.3.6 Register STRG
25.13.3.7 Register TBU_TS0
25.13.3.8 Register TBU_TS1
25.13.3.9 Register TBU_TS2
25.13.3.10 Register MHB
25.13.4 MCS Configuration Registers
25.13.4.1 MCS Configuration Registers Overview
25.13.4.2 Register MCSi_CHx_CTRL (x:07)
25.13.4.3 Register MCSi_CHx_PC (x:0…7)
25.13.4.4 Register MCSi_CHx_Ry (x:0…7, y:0…7)
25.13.4.5 Register MCSi_CHx_ACB (x:0…7)
25.13.4.6 Register MCSi_CHx_IRQ_NOTIFY (x:0…7)
25.13.4.7 Register MCSi_CHx_IRQ_EN (x:0…7)
25.13.4.8 Register MCSi_CHx_IRQ_FORCINT (x:0…7)
25.13.4.9 Register MCSi_CHx_IRQ_MODE (x:0…7)
25.13.4.10 Register MCSi_CHx_EIRQ_EN (x:0…7)
25.13.4.11 Register MCSi_CTRL
25.13.4.12 Register MCSi_CTRG
25.13.4.13 Register MCSi_STRG
25.13.4.14 Register MCSi_RST
25.13.4.15 Register MCSi_ERR
25.14 Memory Configuration (MCFG)
25.14.1 Overview
25.14.1.1 Memory Layout Configurations (MSC_RAM1_EN_ADDR_MSB=0)
25.14.1.2 Memory layout Parameters (MSC_RAM1_EN_ADDR_MSB=0)
25.14.1.3 Memory Layout Configurations (MSC_RAM1_EN_ADDR_MSB=1)
25.14.1.4 Memory Layout Parameters (MSC_RAM1_EN_ADDR_MSB=1)
25.14.2 MCFG Configuration Registers
25.14.2.1 Register MCFG_CTRL
25.15 TIM0 Input Mapping Module (MAP)
25.15.1 Overview
25.15.1.1 MAP Submodule architecture
25.15.2 TIM Signal Preprocessing (TSPP)
25.15.2.1 TIM Signal Preprocessing (TSPP) subunit architecture
25.15.2.2 Bit Stream Combination
25.15.3 MAP Register overview
25.15.4 MAP Register description
25.15.4.1 Register MAP_CTRL
25.16 Digital PLL Module (DPLL)
25.16.1 Overview
25.16.2 Requirements and demarcation
25.16.3 Input signal courses
25.16.4 Block and interface description
25.16.4.1 DPLL Block diagram
25.16.4.2 Interface description of DPLL
25.16.5 DPLL Architecture
25.16.5.1 Purpose of the module
25.16.5.2 Explanation of the prediction methodology
25.16.5.3 Clock topology
25.16.5.4 Clock generation
25.16.5.5 Typical frequencies
25.16.5.6 Time stamps and systematic corrections
25.16.5.7 DPLL Architecture overview
25.16.5.8 DPLL Architecture description
25.16.5.9 Block diagrams of time stamp processing.
25.16.5.10 Register and RAM address overview
25.16.6 Prediction of the current increment duration
25.16.6.1 The use of increments in the past
25.16.6.2 Increment prediction in Normal Mode forwards (DIR1=0)
25.16.6.3 Increment prediction in Emergency Mode forwards (DIR2=0)
25.16.6.4 Increment prediction in Normal Mode backwards (DIR1=1)
25.16.6.5 Increment prediction in Emergency Mode backwards (DIR2=1)
25.16.7 Calculations for actions
25.16.7.1 Action calculations for TRIGGER forwards
25.16.7.2 Action calculations for TRIGGER backwards
25.16.7.3 Action calculations STATE forwards
25.16.7.4 Action calculations for STATE backwards
25.16.7.5 Update of RAM in Normal and Emergency Mode
25.16.7.6 Time and position stamps for actions in Normal Mode
25.16.7.7 The use of the RAM
25.16.7.8 Time and position stamps for actions in Emergency Mode
25.16.8 Signal processing
25.16.8.1 Time stamp processing
25.16.8.2 Count and compare unit
25.16.8.3 Sub pulse generation for SMC=0
25.16.8.4 Sub pulse generation for SMC=1
25.16.8.5 Calculation of the Accurate Position Values
25.16.8.6 Scheduling of the Calculation
25.16.9 DPLL Interrupt signals
25.16.9.1 DPLL Interrupt signals
25.16.10 DPLL Register overview
25.16.11 DPLL Register and Memory description
25.16.11.1 Register DPLL_CTRL_0
25.16.11.2 Register DPLL_CTRL_1
25.16.11.3 Register DPLL_CTRL_2
25.16.11.4 Register DPLL_CTRL_3
25.16.11.5 Register DPLL_CTRL_4
25.16.11.6 Register DPLL_ACT_STA
25.16.11.7 Register DPLL_OSW
25.16.11.8 Register DPLL_AOSV_2
25.16.11.9 Register DPLL_APT
25.16.11.10 Register DPLL_APS
25.16.11.11 Register DPLL_APT_2C
25.16.11.12 Register DPLL_APS_1C3
25.16.11.13 Register DPLL_NUTC
25.16.11.14 Register DPLL_NUSC
25.16.11.15 Register DPLL_NTI_CNT
25.16.11.16 Register DPLL_IRQ_NOTIFY
25.16.11.17 Register DPLL_IRQ_EN
25.16.11.18 Register DPLL_IRQ_FORCINT
25.16.11.19 Register DPLL_IRQ_MODE
25.16.11.20 Register DPLL_EIRQ_EN
25.16.11.21 Register DPLL_INC_CNT1
25.16.11.22 Register DPLL_INC_CNT2
25.16.11.23 Register DPLL_APT_SYNC
25.16.11.24 Register DPLL_APS_SYNC
25.16.11.25 Register DPLL_TBU_TS0_T
25.16.11.26 Register DPLL_TBU_TS0_S
25.16.11.27 Register DPLL_ADD_IN_LD1
25.16.11.28 Register DPLL_ADD_IN_LD2
25.16.11.29 Register DPLL_STATUS
25.16.11.30 Register DPLL_ID_PMTR_x
25.16.11.31 Register DPLL_CTRL_0_SHADOW_TRIGGER
25.16.11.32 Register DPLL_CTRL_0_SHADOW_STATE
25.16.11.33 Register DPLL_CTRL_1_SHADOW_TRIGGER
25.16.11.34 Register DPLL_CTRL_1_SHADOW_STATE
25.16.11.35 Register DPLL_RAM_INI
25.16.11.36 Memory DPLL_PSA[i]
25.16.11.37 Memory DPLL_DLA[i]
25.16.11.38 Memory DPLL_NA[i]
25.16.11.39 Memory DPLL_DTA[i]
25.16.11.40 Memory DPLL_TS_T
25.16.11.41 Memory DPLL_TS_T_OLD
25.16.11.42 Memory DPLL_FTV_T
25.16.11.43 Memory DPLL_TS_S
25.16.11.44 Memory DPLL_TS_S_OLD
25.16.11.45 Memory DPLL_FTV_S
25.16.11.46 Memory DPLL_THMI
25.16.11.47 Memory DPLL_THMA
25.16.11.48 Memory DPLL_THVAL
25.16.11.49 Memory DPLL_TOV
25.16.11.50 Memory DPLL_TOV_S
25.16.11.51 Memory DPLL_ADD_IN_CAL1
25.16.11.52 Memory DPLL_ADD_IN_CAL2
25.16.11.53 Memory DPLL_MPVAL1
25.16.11.54 Memory DPLL_MPVAL2
25.16.11.55 Memory DPLL_NMB_T_TAR
25.16.11.56 Memory DPLL_NMB_T_TAR_OLD
25.16.11.57 Memory DPLL_NMB_S_TAR
25.16.11.58 Memory DPLL_NMB_S_TAR_OLD
25.16.11.59 Memory DPLL_RCDT_TX
25.16.11.60 Memory DPLL_RCDT_SX
25.16.11.61 Memory DPLL_RCDT_TX_NOM
25.16.11.62 Memory DPLL_RCDT_SX_NOM
25.16.11.63 Memory DPLL_RDT_T_ACT
25.16.11.64 Memory DPLL_RDT_S_ACT
25.16.11.65 Memory DPLL_DT_T_ACT
25.16.11.66 Memory DPLL_DT_S_ACT
25.16.11.67 Memory DPLL_EDT_T
25.16.11.68 Memory DPLL_MEDT_T
25.16.11.69 Memory DPLL_EDT_S
25.16.11.70 Memory DPLL_MEDT_S
25.16.11.71 Memory DPLL_CDT_TX
25.16.11.72 Memory DPLL_CDT_SX
25.16.11.73 Memory DPLL_CDT_TX_NOM
25.16.11.74 Memory DPLL_CDT_SX_NOM
25.16.11.75 Memory DPLL_TLR
25.16.11.76 Memory DPLL_SLR
25.16.11.77 Memory DPLL_PDT[i]
25.16.11.78 Memory DPLL_MLS1
25.16.11.79 Memory DPLL_MLS2
25.16.11.80 Memory DPLL_CNT_NUM1
25.16.11.81 Memory DPLL_CNT_NUM2
25.16.11.82 Memory DPLL_PVT
25.16.11.83 Memory DPLL_PSTC
25.16.11.84 Memory DPLL_PSSC
25.16.11.85 Memory DPLL_PSTM
25.16.11.86 Memory DPLL_PSTM_OLD
25.16.11.87 Memory DPLL_PSSM
25.16.11.88 Memory DPLL_PSSM_OLD
25.16.11.89 Memory DPLL_NMB_T
25.16.11.90 Memory DPLL_NMB_S
25.16.11.91 Memory DPLL_RDT_Sx
25.16.11.92 Memory DPLL_TSF_S[i]
25.16.11.93 Memory DPLL_ADT_S[i]
25.16.11.94 Memory DPLL_DT_S[i]
25.16.11.95 Memory DPLL_TSAC[i]
25.16.11.96 Memory DPLL_PSAC[i]
25.16.11.97 Memory DPLL_ACBi
25.16.11.98 Memory DPLL_RDT_T[i]
25.16.11.99 Memory DPLL_TSF_T[i]
25.16.11.100 Memory DPLL_ADT_T[i]
25.16.11.101 Memory DPLL_DT_T[i]
25.16.12 Terms and Abbreviations
25.17 Sensor Pattern Evaluation (SPE)
25.17.1 Overview
25.17.1.1 SPE Submodule integration concept into GTM
25.17.1.2 SPE Sample input pattern for
25.17.2 SPE Submodule description
25.17.2.1 SPE to TOM Connections
25.17.2.2 SPE Submodule architecture
25.17.2.3 SPE[i]_IN_PAT register representation
25.17.2.4 SPE Revolution detection
25.17.3 SPE Interrupt signals
25.17.4 SPE Register overview
25.17.5 SPE Register description
25.17.5.1 Register SPEi_CTRL_STAT
25.17.5.2 Register SPEi_PAT
25.17.5.3 Register SPEi_OUT_PATx (x: 07)
25.17.5.4 Register SPEi_OUT_CTRL
25.17.5.5 Register SPEi_CNT
25.17.5.6 Register SPEi_CMP
25.17.5.7 Register SPEi_IRQ_NOTIFY
25.17.5.8 Register SPEi_IRQ_EN
25.17.5.9 Register SPEi_IRQ_FORCINT
25.17.5.10 Register SPEi_IRQ_MODE
25.17.5.11 Register SPEi_EIRQ_EN
25.18 Interrupt Concentrator Module (ICM)
25.18.1 Overview
25.18.2 Bundling
25.18.2.1 GTM Infrastructure Interrupt Bundling
25.18.2.2 DPLL Interrupt Bundling
25.18.2.3 TIM Interrupt Bundling
25.18.2.4 MCS Interrupt Bundling
25.18.2.5 TOM and ATOM Interrupt Bundling
25.18.3 ICM Interrupt Signals
25.18.4 ICM Configuration Registers Overview
25.18.5 ICM Configuration Registers Description
25.18.5.1 Register ICM_IRQG_0
25.18.5.2 Register ICM_IRQG_1 (DPLL Interrupt Group)
25.18.5.3 Register ICM_IRQG_2
25.18.5.4 Register ICM_IRQG_4
25.18.5.5 Register ICM_IRQG_6
25.18.5.6 Register ICM_IRQG_7
25.18.5.7 Register ICM_IRQG_9
25.18.5.8 Register ICM_IRQG_10
25.18.5.9 Register ICM_IRQG_MEI (Module Error Interrupt)
25.18.5.10 Register ICM_IRQG_CEI0 (Channel Error Interrupt 0)
25.18.5.11 Register ICM_IRQG_CEI1 (Channel Error Interrupt 1)
25.18.5.12 Register ICM_IRQG_CEI3 (Channel Error Interrupt 3)
25.19 Output Compare Unit (CMP)
25.19.1 Overview
25.19.1.1 Architecture of the Compare Unit
25.19.2 Bitwise Compare Unit (BWC)
25.19.3 Configuration of the Compare Unit
25.19.4 Error Generator
25.19.5 CMP Interrupt Signal
25.19.6 CMP Configuration Registers Overview
25.19.7 CMP Configuration Registers Description
25.19.7.1 Register CMP_EN
25.19.7.2 Register CMP_IRQ_NOTIFY
25.19.7.3 Register CMP_IRQ_EN
25.19.7.4 Register CMP_IRQ_FORCINT
25.19.7.5 Register CMP_IRQ_MODE
25.19.7.6 Register CMP_EIRQ_EN
25.20 Monitor Unit (MON)
25.20.1 Overview
25.20.1.1 MON Block Diagram
25.20.1.2 Realization without Activity Checker of the clock signals
25.20.2 Clock Monitoring
25.20.3 CMP error Monitoring
25.20.4 Checking the Characteristics of Signals by MCS
25.20.5 Checking ARU Cycle Time
25.20.6 MON Interrupt Signals
25.20.7 MON Registers Overview
25.20.8 MON Configuration Registers Description
25.20.8.1 Register MON_STATUS
25.20.8.2 Register MON_ACTIVITY_0
25.21 Appendix
25.21.1 ARU Write Address Overview
25.22 GTM Implementation
25.22.1 GTM Registers
25.22.2 Port Connections
25.22.2.1 Port to GTM Control Registers
25.22.2.2 GTM to Port Control Registers
25.22.3 MSC Connections
25.22.3.1 GTM to MSC Control Registers
25.22.4 DSADC Connections
25.22.5 ADC Connections
25.22.6 SENT Connections
25.22.7 CAN Connection
25.22.8 CCU6x Connections
25.22.9 PSI5 Connections
25.22.10 GTM Data Exchange Registers
25.22.11 SCU Connections
25.22.12 GTM Debug Interface
25.22.12.1 OCDS Trigger Bus (OTGB) Interface
25.22.12.2 GTM Debug Registers
25.23 ision History
26 Capture/Compare Unit 6 (CCU6)
26.1 Introduction
26.1.1 Feature Set Overview
26.1.2 Block Diagram
26.1.3 CCU6 Kernel Registers
26.2 Operating Timer T12
26.2.1 T12 Overview
26.2.2 T12 Counting Scheme
26.2.2.1 Clock Selection
26.2.2.2 Edge-Aligned / Center-Aligned Mode
26.2.2.3 Single-Shot Mode
26.2.3 T12 Compare Mode
26.2.3.1 Compare Channels
26.2.3.2 Channel State Bits
26.2.3.3 Hysteresis-Like Control Mode
26.2.4 Compare Mode Output Path
26.2.4.1 Dead-Time Generation
26.2.4.2 State Selection
26.2.4.3 Output Modulation and Level Selection
26.2.5 T12 Capture Modes
26.2.6 T12 Shadow Register Transfer
26.2.7 Timer T12 Operating Mode Selection
26.2.8 T12 related Registers
26.2.8.1 T12 Counter Register
26.2.8.2 Period Register
26.2.8.3 Capture/Compare Registers
26.2.8.4 Capture/Compare Shadow Registers
26.2.8.5 Dead-time Control Register
26.2.9 Capture/Compare Control Registers
26.2.9.1 Channel State Bits
26.2.9.2 T12 Mode Control Register
26.2.9.3 Timer Control Registers
26.3 Operating Timer T13
26.3.1 T13 Overview
26.3.2 T13 Counting Scheme
26.3.2.1 Clock Selection
26.3.2.2 T13 Counting
26.3.2.3 Single-Shot Mode
26.3.2.4 Synchronization to T12
26.3.3 T13 Compare Mode
26.3.4 Compare Mode Output Path
26.3.5 T13 Shadow Register Transfer
26.3.6 T13 related Registers
26.3.6.1 T13 Counter Register
26.3.6.2 Period Register
26.3.6.3 Compare Register
26.3.6.4 Compare Shadow Register
26.4 Synchronous Start Feature
26.5 Trap Handling
26.6 Multi-Channel Mode
26.7 Hall Sensor Mode
26.7.1 Hall Pattern Evaluation
26.7.2 Hall Pattern Compare Logic
26.7.3 Hall Mode Flags
26.7.4 Hall Mode for Brushless DC-Motor Control
26.8 Modulation Control Registers
26.8.1 Modulation Control
26.8.2 Trap Control Register
26.8.3 Passive State Level Register
26.8.4 Multi-Channel Mode Registers
26.9 Interrupt Handling
26.9.1 Interrupt Structure
26.9.2 Interrupt Registers
26.9.2.1 Interrupt Status Register
26.9.2.2 Interrupt Status Set Register
26.9.2.3 Status Reset Register
26.9.2.4 Interrupt Enable Register
26.9.2.5 Interrupt Node Pointer Register
26.10 General Module Operation
26.10.1 Input Selection
26.10.2 Input Monitoring
26.10.3 OCDS Suspend
26.10.4 OCDS Trigger Bus (OTGB) Interface
26.10.5 General Registers
26.10.5.1 ID Register
26.10.5.2 Port Input Select Registers
26.10.5.3 Module Configuration Register
26.10.5.4 Input Monitoring Register
26.10.5.5 Lost Indicator Register
26.10.5.6 Kernel State Control Sensitivity Register
26.10.6 BPI Registers
26.10.6.1 System Registers
26.11 Implementation
26.11.1 Address Map
26.11.1.1 Module Registers
26.11.2 Module Output Select
26.11.3 Synchronous Start
26.11.4 Digital Connections
26.11.4.1 Connections of CCU60
26.11.4.2 Connections of CCU61
27 General Purpose Timer Unit (GPT12)
27.1 Timer Block GPT1
27.1.1 GPT1 Core Timer T3 Control
27.1.2 GPT1 Core Timer T3 Operating Modes
27.1.3 GPT1 Auxiliary Timers T2/T4 Control
27.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes
27.1.5 GPT1 Clock Signal Control
27.1.6 GPT1 Registers
27.1.6.1 GPT1 Timer Registers
27.1.6.2 GPT1 Timer Control Registers
27.2 Timer Block GPT2
27.2.1 GPT2 Core Timer T6 Control
27.2.2 GPT2 Core Timer T6 Operating Modes
27.2.3 GPT2 Auxiliary Timer T5 Control
27.2.4 GPT2 Auxiliary Timer T5 Operating Modes
27.2.5 GPT2 Register CAPREL Operating Modes
27.2.6 GPT2 Clock Signal Control
27.2.7 GPT2 Registers
27.2.7.1 GPT2 Timer Registers
27.2.7.2 GPT2 Timer Control Registers
27.3 GPT12 Kernel Register Overview
27.4 General Module Operation
27.4.1 Input Selection
27.4.2 OCDS Suspend
27.4.3 Miscellaneous GPT12 Registers
27.4.3.1 Port Input Select Register
27.4.3.2 Identification Register
27.4.4 BPI Registers
27.4.4.1 System Registers
27.5 Implementation of the GPT12 Module
27.5.1 Address Map
27.5.2 Module Connections
28 Versatile Analog-to-Digital Converter (VADC)
28.1 Introduction and Basic Structure
28.2 Electrical Models
28.3 Configuration of General Functions
28.3.1 Module Identification
28.3.2 System Registers
28.3.3 General Clocking Scheme and Control
28.3.4 Register Access Control
28.4 Analog Module Activation and Control
28.4.1 Analog Converter Control
28.4.2 Alternate Reference Selection
28.4.3 Calibration
28.5 Conversion Request Generation
28.5.1 Queued Request Source Handling
28.5.2 Channel Scan Request Source Handling
28.5.3 Request Source Arbitration
28.5.3.1 Arbiter Operation and Configuration
28.5.3.2 Conversion Start Mode
28.6 Analog Input Channel Configuration
28.6.1 Channel Parameters
28.6.2 Alias Feature
28.6.3 Conversion Modes
28.6.4 Compare with Standard Conversions (Limit Checking)
28.6.5 Utilizing Fast Compare Mode
28.6.6 Boundary Flag Control
28.6.7 Conversion Timing
28.7 Conversion Result Handling
28.7.1 Storage of Conversion Results
28.7.2 Data Alignment
28.7.3 Wait-for-Read Mode
28.7.4 Result FIFO Buffer
28.7.5 Result Event Generation
28.7.6 Data Modification
28.8 Synchronization of Conversions
28.8.1 Synchronized Conversions for Parallel Sampling
28.8.2 Equidistant Sampling
28.9 Safety Features
28.9.1 Broken Wire Detection
28.9.2 Signal Path Test Modes
28.9.3 Configuration of Test Functions
28.10 External Multiplexer Control
28.11 Service Request Generation
28.12 Implementation into the TC27x
28.12.1 Product-Specific Configuration
28.12.2 Summary of Registers and Locations
28.12.3 Analog Module Connections in the TC27x
28.12.4 Digital Module Connections in the TC27x
28.13 Use Case Example for VADC
29 Delta-Sigma Analog-to-Digital Converter (DSADC)
29.1 Introduction and Basic Structure
29.2 Configuration of General Functions
29.2.1 Module Identification
29.2.2 System Registers
29.2.3 Register Access Control
29.2.4 Global Configuration Registers
29.3 Input Channel Configuration
29.3.1 Modulator Clock Selection and Generation
29.3.2 Input Data Selection
29.3.3 On-Chip Modulator
29.3.4 Input Path Control
29.3.5 Common Mode Voltage
29.3.6 Common Mode Hold Voltage
29.3.7 Calibration Support
29.4 Main Filter Chain
29.4.1 CIC Filter
29.4.2 FIR Filters
29.4.3 Offset Compensation
29.4.4 Integrator Stage
29.5 Auxiliary Filter
29.6 Filter Configuration and Control
29.6.1 Filter Configuration Options
29.6.2 Recommended Settings
29.6.3 Group Delay
29.7 Conversion Result Handling
29.8 Service Request Generation
29.9 Resolver Support
29.9.1 Carrier Signal Generation
29.9.2 Return Signal Synchronization
29.10 Time-Stamp Support
29.11 Implementation into the TC27x
29.11.1 Product-Specific Configuration
29.11.2 Summary of Registers and Locations
29.11.3 Analog Module Connections in the TC27x
29.11.4 Digital Module Connections in the TC27x
30 Inter-Integrated Circuit Module (I2C)
30.1 Overview
30.1.1 I2C-bus Overview
30.1.2 I2C Module Overview
30.1.3 References
30.2 I2C Module Functional Specification
30.2.1 I2C Protocol
30.2.2 Clock and Timing Control
30.2.2.1 Baudrate Generation
30.2.2.2 I2C Signal Timing Adjustment
30.2.3 I2C Kernel Control Logic
30.2.4 FIFO Operation
30.2.4.1 Data Transmission
30.2.4.2 Transmit Request Generation
30.2.4.3 Transmit Data Alignment
30.2.4.4 Data Reception
30.2.4.5 Receive Request Generation
30.2.4.6 Receive Data Alignment
30.2.4.7 Switching between Transmission and Reception
30.2.5 Service Request Block Operation
30.2.5.1 Overview of Service Requests
30.2.5.2 Interrupt Service Request Structure
30.3 I2C Module Internal Registers
30.3.1 Global Module Control Registers
30.3.2 FIFO Registers
30.3.3 Basic Interrupt Registers
30.3.4 Error Interrupt Source Registers
30.3.5 Protocol Interrupt Source Registers
30.4 I2C Module Implementation
30.4.1 Interfaces of the I2C Module(s)
30.4.2 Module Clock Control
30.4.3 Bus Peripheral Interface Registers
30.4.4 I2C Module Registers Overview
30.4.5 Port and I/O Line Control
30.4.6 Interrupt Control
30.5 Module Integration
30.5.1 Integration Overview
30.5.2 BPI_SPB Module Registers
30.5.2.1 System Registers
31 Input Output Monitor (IOM)
31.1 Overview
31.2 Features
31.3 Interfaces
31.4 Kernel Description
31.5 Filter & Prescaler Channel Description
31.6 EXOR Combiner Description
31.7 Logic Analyzer Module (LAM) Description
31.8 Event Combiner Module (ECM) Description
31.9 IOM Registers
31.9.1 IOM Identification Register (IOM_ID)
31.9.2 Filter & Prescaler Cell (FPC) Registers
31.9.3 GTM Input Related Registers
31.9.4 Logic Analyzer Module (LAM) Registers
31.9.5 Event Combiner Module (ECM) Registers
31.9.6 System Registers
31.10 SoC Integration
31.11 Example Monitor/Safety Measures
31.11.1 Example 1 - Pulse or duty cycle too short
31.11.2 Example 2 - Pulse or duty cycle too long
31.11.3 Example 3 - Period too short
31.11.4 Example 4 - Period too long
31.11.5 Example 5 - Diagnosis of Command and Feedback - acceptable propagation window and/or signal consistency check
31.11.6 Example 6 - Diagnosis of Set-up and Hold times
32 Peripheral Sensor Interface (PSI5)
32.1 PSI5 Kernel Description
32.1.1 Overview
32.2 General Operation
32.3 Definitions
32.4 PSI5 Operation
32.5 Frame Formats and Definitions
32.5.1 PSI5 V1.3 Frame
32.5.2 Extended PSI5 Frame (non standard)
32.5.3 Extended Serial Data Encoding (“Slow Channel”)
32.5.4 Extended Serial Data Frame
32.6 Sync Pulses
32.6.1 Synchronous Transmission
32.6.2 ECU to Sensor Communication
32.7 Manchester Decoding
32.8 Bit Rate Generation
32.9 Digital Glitch Filter
32.10 Time Stamp Generation
32.11 Error Detection Capabilities
32.12 Interrupts
32.13 Trigger Outputs
32.14 PSI5 Kernel Registers
32.14.1 Module Control
32.14.2 Input and Output Control
32.14.3 Receiver Control Registers
32.14.4 Receive Data and Status Registers
32.14.5 Receive Data Memory
32.14.6 Sync Pulse Control
32.14.7 Interrupt Control Registers
32.15 PSI5 Module Implementation
32.15.1 Interface Connections of the PSI5 Module
32.15.1.1 On-Chip Connections
32.15.2 PSI5 Module-Related External Registers
32.15.2.1 Port Control
32.15.2.2 Timing Constraints
32.16 Revision History
33 Peripheral Sensor Interface with Serial PHY Connection (PSI5-S)
33.1 PSI5-S Description
33.1.1 Overview
33.2 Definitions
33.3 General Operation
33.4 PSI5 ECU to Sensor Operation
33.5 Frame Formats and Definitions
33.5.1 Communication between PSI5-S and PHY via UART
33.5.1.1 “Packet Frames” received from PHY
33.5.1.2 PSI5-S UART Frames transmitted to PHY
33.5.2 Communication between PHY and Sensor (PSI5 Standard)
33.5.2.1 PSI5 Standard Frame Format
33.5.2.2 PSI5 Extended Frame Format
33.5.2.3 Sync Pulses
33.6 Clock Generation
33.6.1 Overview on Clocks in the System
33.7 Time Stamp Generation
33.8 Watch Dog Timers
33.9 Send Data
33.9.1 Channel Trigger
33.9.2 Sync Pulse Control
33.9.3 Send Data Preparation
33.10 Message Generation
33.11 DMA Support
33.11.1 Single DMA, 8 dedicated DMAs
33.11.2 Two daisy chained DMAs
33.11.3 Interrupts for DMA support
33.12 Error Detection Capabilities
33.13 Special use of Channel 0
33.14 ASC Kernel Description
33.14.1 Overview
33.14.2 General Operation
33.14.3 Asynchronous Operation
33.14.3.1 Asynchronous Data Frames
33.14.3.2 Asynchronous Transmission
33.14.3.3 Asynchronous Reception
33.14.3.4 RXD/TXD Data Path Selection in Asynchronous Modes
33.14.4 Synchronous Operation
33.14.4.1 Synchronous Transmission
33.14.4.2 Synchronous Reception
33.14.4.3 Synchronous Timing
33.14.5 Baud Rate Generation
33.14.5.1 Baud Rates in Asynchronous Mode
33.14.5.2 Baud Rates in Synchronous Mode
33.14.6 Hardware Error Detection Capabilities
33.14.7 Interrupts
33.15 Interrupts
33.16 Trigger Outputs
33.17 PSI5-S Kernel Registers
33.17.1 Module Control
33.17.2 Input and Output Control
33.17.3 Receiver Control Registers
33.17.4 Receive Data and Status Registers
33.17.5 Sync Pulse Control
33.17.6 ASC Registers
33.17.7 Interrupt Control Registers
33.18 PSI5-S Module Implementation
33.18.1 Interface Connections of the PSI5-S Module
33.18.1.1 On-Chip Connections
33.18.2 PSI5-S Module-Related External Registers
33.18.2.1 Port Control
33.19 Revision History
34 Ethernet MAC (ETH)
34.1 Overview
34.1.1 General Module Description
34.1.2 System Overview
34.1.2.1 System-Level Block Diagram
34.1.2.2 Interfaces
34.1.2.3 Transmit and Receive FIFOs
34.1.3 Features List
34.1.3.1 GMAC Core Features
34.1.3.2 DMA Block Features
34.1.3.3 Transaction Layer (MTL) Features
34.1.3.4 Monitoring, Test, and Debugging Support Features
34.2 Architecture
34.2.1 Introduction
34.2.2 IEEE 1588-2002 Overview
34.2.2.1 Reference Timing Source
34.2.2.2 Transmit Path Functions
34.2.2.3 Receive Path Functions
34.2.2.4 Time Stamp Error Margin
34.2.2.5 Frequency Range of Reference Timing Clock
34.2.2.6 Advanced Time Stamp Feature Support
34.2.3 AHB Application Host Interface
34.2.4 DMA Controller
34.2.4.1 Initialization
34.2.4.2 Transmission
34.2.4.3 Reception
34.2.4.4 Interrupts
34.2.5 MAC Transaction Layer (MTL)
34.2.5.1 Transmit Path
34.2.5.2 Receive Path
34.2.6 GMAC Core
34.2.6.1 Transmission
34.2.6.2 MAC Transmit Interface Protocol
34.2.6.3 Reception
34.2.6.4 System Time Register Module
34.2.7 MAC Management Counters
34.2.7.1 Address Assignments
34.2.7.2 MMC Register Description
34.2.8 Power Management Block
34.2.8.1 PMT Block Description
34.2.8.2 Remote Wake-Up Frame Detection
34.2.8.3 Magic Packet Detection
34.2.8.4 System Considerations During Power-Down
34.2.9 Station Management Agent
34.2.9.1 Functions
34.2.9.2 MII Management Write Operation
34.2.9.3 MII Management Read Operation
34.2.10 Reduced Media Independent Interface
34.2.10.1 Block Diagram
34.2.10.2 Block Overview
34.2.10.3 Transmit Bit Ordering
34.2.10.4 RMII Transmit Timing Diagrams
34.2.11 Interrupts From the GMAC Core
34.3 Register
34.3.1 Register Maps
34.3.1.1 Register Overview
34.3.1.2 DMA Register Map
34.3.1.3 GMAC Register Map
34.3.1.4 Ethernet MAC Additional Module Control Registers
34.3.2 Register Description
34.4 Descriptors
34.4.1 Normal Descriptor Formats
34.4.1.1 Receive Descriptor
34.4.1.2 Transmit Descriptor
34.4.1.3 Descriptor Format With IEEE 1588 Time Stamping Enabled
34.4.2 Alternate or Enhanced Descriptors
34.4.2.1 Transmit Descriptor
34.4.2.2 Receive Descriptor
34.5 Ethernet MAC Module Implementation
34.5.1 Interface Connections of the Ethernet MAC Module
34.5.1.1 On-Chip Connections
34.5.1.2 Clocks
34.5.2 Ethernet MAC Module-Implementation Related Registers
34.5.2.1 Port Control
34.5.2.2 Clock Control
34.5.2.3 Additional Register
34.6 Revision History
AURIX™
TC27x D-Step
32-Bit Single-Chip Microcontroller
User’s Manual
V2.2 2014-12
Microcontrollers
Edition 2014-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
AURIX™
TC27x D-Step
32-Bit Single-Chip Microcontroller
User’s Manual
V2.2 2014-12
Microcontrollers
TC27x D-Step
TC27x User’s Manual
Revision History: V2.2 2014-12
Significant changes since previous version: TC27x-D User’s Manual V2.1
Chapter
Introduction • Removed redundant introduction sections.
Subjects (major changes since last revision)
SCU/CCU
SCU/PMC
SCU/SCU
MTU
SMU
• Enhanced OCDS introduction.
• Updated divider formula in registers CCUCON6,7,8.
• Updated table “CCU allowed Clock Ratios”.
• Updated reset value of EVRRSTCON.
• Corrected DTSCON.CAL width.
•
Removed design related register reference from “OCDS Behavior of
WDTs”.
• MCONTROL.Res4 field (bits 14:12) marked as “Must be written with
0x4” in to maintain redundancy.
• Sections “Reading a Single Memory Location” and “Writing a Single
Memory Location” should always write MCONTROL with the MS nibble
0x4 instead of 0x0.
• Design related register reference “RDR” removed.
• Corrected register long name of SMU_RTC to “Recovery Timer
Configuration”.
• DMA alarm ALM2[24] is now reserved. Alarm implemented by DMA SRI
error detection alarms.
Improved description of alarm ALM3[27].
•
• SCU alarm ALM3[28] is now reserved. Feature not implemented.
• Pre-alarms PreAlarm[129=DMA.(Safety FF Error Detection)] and
PreAlarm[130=PMU.(Safety FF Error Detection)] removed because
DMA and PMU do not implement Safety FF.
• Added configuration hints to SMU_AGCF Registers: reserved
alarms shall be configured as “No Action”.
• Enhanced description of register SMU_RMEF and SMU_RMSTS.
• Enhanced description of register SMU_PCTL with advice how to
operate it in the application.
• Changed section “SMU Integration Guidelines”.
• Explained “Register Monitor” = “Safety Flip-Flop”.
•
•
Improved Figure “SMU State Machine”.
Improved section “FSP Fault State”.
User’s Manual
V2.2, 2014-12
TC27x User’s Manual
TC27x D-Step
Revision History: V2.2 2014-12
PMU/Flash
programmed to all-1.
program UCBs.
• Noted that “Verify Erased Logical Sector Range” is not blocked on
password containing UCBs when the protection is disabled.
• Removed confusing statement that unavailable DFlash ranges can be
• Noted explicitly that the UCBs 8 to 11 are read-only.
• Clarified that both “Write Page” and “Write Burst” can be used to
• Removed statement about restricted FAR capabilities.
• Removed note from “Erase Logical Sector Range” that warned from
erasing more than 256 KByte because of increased suspend times. The
suspend times are not increasing.
• Changed note for “Erase Logical Sector Range” that described that
erase time can be much shorter than maximum times documented in
the Data Sheet. The reason was removed as there are more
dependencies.
• Documented “Test Pass Marker” in UCB_IFX.
• Removed term “Reset Class” and replaced by named resets.
• Stated explicitly that a failed HSM boot prevents device boot.
• Corrected description of LVDS pads in CMOS mode: removed
sentence “no open-drain mode available”.
• Added clarification: a pending Service Request is cleared in the Service
Request Node with the Acknowledge from the Service Provider. The
Acknowledge does not mean that the Service Request is serviced at
that time (e.g. disabled or not implemented DMA channel, Trap on CPU
prevents execution of Service Request).
• Added description of the ECC algorithm used for the IR internal Error
Detection.
PORTS
IR
ASCLIN
QSPI
MSC
MultiCAN+
• Block “Auto Baud Rate Operation” added.
• Description of register field “BRD.MEASURED” improved.
• Removed maximum baud rates from feature list as these depend on
pad speeds and PCB implementation.
• Description of “Clock Control when using the ABRA Block” improved.
• Equation of Ncycles for extended frames changed: added factor 32 to
PPDE.
• Fixed pad naming for all devices.
• CRC issue of CAN FD standard documented and recommended
additional software CRC.
User’s Manual
2
V2.2, 2014-12
TC27x User’s Manual
TC27x D-Step
Revision History: V2.2 2014-12
GTM
was corrected.
• Corrected error in BGA-416 TOUT numbering for P10.13 and P10.11.
• Connection shown in figures and register for SET5 and SET6 to MSC2
VADC
DSADC
• Updated description of bit field OCS.SUS.
• Updated description of (A)TOM SOMP Mode.
• Clarified reset behavior of debug registers.
• Corrected error for P2.11; it is connected to TIM4_4 not to TIM4_7
• Added hint how to use Pxx_PDISC for diagnostics in section “Signal
• Adjusted the position of accumulated results in section “Data
Path Test Modes”.
Alignment”.
• Changed in section “Recommended Settings” the documented full-
scale values from ±1900D to ±3800D and their dependence on operating
modes.
• Removed external modulator connections.
• Removed modulator combine mode.
• Separated rectifier and integrator, add data shift in figure DSADC
structure overview.
Subjects (major changes since last revision)
First TC27x D-Step dedicated User’s Manual, based on TC27x-C UM V2.0
• The section “Safety Concept Overview” of the Introduction chapter was
Significant changes since previous version: TC27x-C User’s Manual V2.0
Chapter
–
Introduction
/Safety
Concept
Overview
SENT
• Changed “Extended Serial Data Frame” to “Enhanced Serial Message
removed as the “Safety Manual” supersedes this section.
Frame”. Updated its description.
DSADC
• Documented changes between TC27x C-Step and D-Step:
• Added registers ICCFGx and IGCFG for “Dithering” and “Overload
Rejection”.
• Changed input line clamping of MODCFG.INCFGP/N encoding 01B.
Significant changes since previous version: TC27x User Manual V1.5
Chapter
Subjects (major changes since last revision)
User’s Manual
3
V2.2, 2014-12
TC27x User’s Manual
TC27x D-Step
Revision History: V2.2 2014-12
Introduction
/OCDS
AURIX family.
• Added section “Family Overview” showing OCDS difference in the
• Added section “Debug Access Server (DAS)”.
• Added section “Tool Interface Recommendations”.
• Added warning that bootstrap loaders wait for communication without
time-out.
• Added section “PSFDM code with inverse exit condition”.
• Some details of ESR0 handling explained.
• Added “Instruction Memory Range” and “Atomicity Information”.
• Corrected in “Lockstep Failure Signalling Test” from “LCLCON.FST” to
BootROM
CPU
LCL
RCU
PMC
PMU
“LCLTEST.LCLTx”.
HWCFG[3].
• Enhanced description of STSTAT.HWCFG with
influence of
• Correction to amount of DSPR overwritten by Firmware.
• EVRRSTCON reset value updated.
• Supply routing picture updated to reflect VAREFx mapping to DSADC
and SAR ADC.
• Updated Standby RAM handling.
• Repeated the advice to handle PVER as signal to jump to the next
word-line in the receipe for the Robust EEPROM emulation. Previously
this advice was only contained in the section “Handling Errors During
Operation”.
• Showed the ECC decoder of the BootROM in the block diagram and
described its SEC-DED capability.
• Highlighted in the description of FCON and the wait cycle description
that after System Resets and Power-On Resets the wait cycles are only
sufficient for 100 MHz.
• Noted in the “Application Hints” that the recommended sequence for
issuing “Verify Erased Logical Sector Range” is analog to “Erase”.
• Changed recommendations in the “Application Hints” for ECC test
patterns. Made the all-0/all-1 and address error patterns optional.
Recommended to store 2 of the 4 pattern sets inverse to the other 2.
Improved description of “Load Page” to make the offsets used for 32-bit
transfers more explicit.
• Added to the description of “Write Page” the clear statement that each
•
page shall be programmed only once.
User’s Manual
4
V2.2, 2014-12
TC27x User’s Manual
TC27x D-Step
Revision History: V2.2 2014-12
HSSL/
HSCT
P20.0 as signaling path.
• Added note below figure “Overview of Interface Signals” recommending
• Description of register field INIT.LHLR enhanced.
• Reset
sequence
described
for
in
note
register
field
CONFIGPHY.PHYRST.
SENT
CCU6
GPT12
• Added new section “PLL configuration and Baud Rates”.
• Changed minimum tick timer to 0.2 µs.
• Tables “Digital Connections”: changed signal name “VADC_G0BFL3”
to “VADCG0BFL3” for consistency with VADC chapter (no functional
change).
• Tables “GPT1/GPT2 Timer Parameters”: values recalculated for typical
module frequencies of 100 MHz and 66.5 MHz.
• Tables “GPT1/2 External Input Signal Limits”: “Basic Clock” replaced by
“Module Clock”, values recalculated for typical module frequencies of
100 MHz and 66.5 MHz.
DSADC
• Added section “Correction for Single-Ended Operation”.
• Corrected assignment to reference voltages.
Significant changes since previous version: TC27x User Manual V1.4
Chapter
General
Subjects (major changes since last revision)
Removed documentation of TC27x A-Step and B-Step. This manual
covers only TC27x C-Step.
Converter architecture changed to SAR. “SHS” registers removed.
VADC
MultiCAN+ Added support for CAN FD resulting in several changes to the registers.
QSPI
XXL data mode added (see register XXLCON).
SLSI inactive interrupt added.
Big endian support added (see register field ECONz.BE)
Significant changes since previous version: User Manual V1.3
Chapter
Buses
Memory
Maps
Subjects (major changes since last revision)
No significant change
No significant change
User’s Manual
5
V2.2, 2014-12
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