Genus_Basic_Lab.pdf-资料库

2015 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders. COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 2

Contents 1. Introduction ................................................................................................................................. 4 1.1 Directory Structure ................................................................................................................ 4 1.2 Tool Versions ........................................................................................................................ 4 1.3 Terminology and Typographic Conventions ......................................................................... 4 1.4 Design.................................................................................................................................... 4 1.5 LAB Sequence ....................................................................................................................... 4 1.6 Commands to Navigate Genus Database Design Hierarchy ................................................. 4 2. LAB: Base Lab for Genus........................................................................................................... 5 2.1 Objective ............................................................................................................................... 5 2.2 Lab Files ................................................................................................................................ 5 2.3 Running the Lab .................................................................................................................... 5 2.4 Understanding the Flow ........................................................................................................ 5 COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 3

1. Introduction In the following labs, you will learn how to use Genus with Legacy UI. Review the presentation document and these lab instructions before starting the labs, and use them as a reference throughout the labs. 1.1 Directory Structure This RAK contains the following directories:  Constraints/ // Contains SDC (constraints) files  LIB/ // Contains technology libraries and macro libraries  LEF/ // Contains technology lefs and macro lefs  RTL/ // Contains HDL files  LAB/ // Contains a lab-specified script to run the lab 1.2 Tool Versions The lab has been designed with the following software versions. Some of the messages and log lines explained in these instructions may not appear with different versions.  Genus 15.1 1.3 Terminology and Typographic Conventions  RAK Rapid Adoption Kit Throughout the lab, the following style is used  Anything to be typed in the command prompt is shown in “blue bold Courier font style”. Information written in a script/log/output file is shown in “black Calibri font style”.   Also, any filename is written in “black bold Courier font style”. 1.4 Design The sample testcase is a generic DTMF design. 1.5 LAB Sequence LAB - This RAK provides a lab to understand basic flow of synthesis using Genus. 1.6 Commands to Navigate Genus Database Design Hierarchy The following directories can be seen after doing below step: legacy_genus@root :> ls –l  ./ (root) // ROOT Directory COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 4

 designs/ // Contains the designs for each module loaded into Genus  hdl_libraries/ // Contains the VHDL architecture libraries  libraries/ // Contain the technology libraries that have been read in  messages/ // List of messages that are displayed during the Genus session  object_types/ //Contains list of Objects associated with the Design go into various directories above legacy_genus@root :> cd Make sure to get back to the root directory in Genus by entering: legacy_genus@root :> cd 2. LAB: Base Lab for Genus 2.1 Objective Use Genus to execute a simple compile of the DTMF design  Go to LAB Directory 2.2 Lab Files This lab uses following files:  run.tcl: This script is created by generating a simple template from Genus in Legacy UI and then modified accordingly. The following commands are used to invoke Genus in Legacy UI and create a template file : unix:> genus –legacy_ui legacy_genus@root :> write_template –outfile run.tcl If ‘-legacy_ui’ is not specified when Genus is invoked, Genus will be invoked with Common UI.  genus.log: Log file for this lab 2.3 Running the Lab You may run commands within ‘run.tcl’ script line by line in Genus session, or you may run all the commands at once using scripts with either one of following ways:  legacy_genus@root :> source run.tcl  unix:> genus –legacy_ui –f run.tcl –log genus.log 2.4 Understanding the Flow Open the run.tcl file and review the following commands in that file. COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 5

1. The following attribute is used to run Genus in Legacy UI if Genus is invoked with Common UI: ::legacy::set_attribute common_ui false / 2. The following variable specifies the name of top level design: set DESIGN dtmf_recvr_core 3. The following three variables allow you to change the effort on separate stages (synthesize to generic, to gates, and optimization) of the synthesis run: set SYN_EFF medium set MAP_EFF medium set OPT_EFF medium 4. The following commands create directories for saving reports, dbs and logfiles: set DATE [clock format [clock seconds] -format "%b%d-%T"] set _OUTPUTS_PATH outputs_${DATE} set _REPORTS_PATH reports_${DATE} set _LOG_PATH logs_${DATE} 5. The following attributes specify the search paths for cell libraries, scripts and RTL. The “/” at the end of the commands indicates that the required object type is root: set_attribute init_lib_search_path {. ../LIB} / set_attribute script_search_path {. ../scripts} / set_attribute init_hdl_search_path {. ../RTL} / 6. The following commands create the necessary output directories if they are not existing: if {![file exists ${_LOG_PATH}]} { file mkdir ${_LOG_PATH} puts "Creating directory ${_LOG_PATH}" } if {![file exists ${_OUTPUTS_PATH}]} { file mkdir ${_OUTPUTS_PATH} puts "Creating directory ${_OUTPUTS_PATH}" } if {![file exists ${_REPORTS_PATH}]} { file mkdir ${_REPORTS_PATH} puts "Creating directory ${_REPORTS_PATH}" } 7. The following attributes determines synthesizing effort for each synthesis stage: set_attribute syn_generic_effort $SYN_EFF / set_attribute syn_map_effort $MAP_EFF / set_attribute syn_opt_effort $OPT_EFF / COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 6

8. The following attribute determines how much information will be written to the log file. For debugging purposes and when providing a testcase to Cadence, set the value to 9. A good value otherwise is 7 or 5 if you want to limit the details. set_attribute information_level 9 / 9. The following attributes specify the various libraries and lefs to be used for the design: set_attribute library { ../LIB/slow.lib ../LIB/pll.lib ../LIB/CDK_S128x16.lib . ./LIB/CDK_S256x16.lib ../LIB/CDK_R512x16.lib} / set_attribute lef_library { ../LEF/gsclib045_tech.lef ../LEF/gsclib045_macro.lef ../L EF/pll.lef ../LEF/CDK_S128x16.lef ../LEF/CDK_S256x16.lef ../LEF/CDK _R512x16.lef } / You can also specify cap tables files by using: set_attribute cap_table_file / 10. The following commands load the RTL design into Genus memory, elaborate the top-level module/entity $DESIGN, report the runtime and memory used up to this stage, and prioritize the checking of unresolved instances (to ensure accuracy of the synthesis results): read_hdl " pllclk.v accum_stat.v alu_32.v arb.v data_bus_mach.v data_sample_mux.v decode_i.v decoder.v \ digit_reg.v conv_subreg.v dma.v dtmf_recvr_core.v execute_i.v m16x16.v mult_32_dp.v \ port_bus_mach.v prog_bus_mach.v ram_128x16_test.v ram_256x16_test.v results_conv.v spi.v \ tdsp_core_glue.v tdsp_core_mach.v tdsp_core.v tdsp_data_mux.v tdsp_ds_cs.v test_control.v \ ulaw_lin_conv.v power_manager.v " elaborate $DESIGN time_info Elaboration check_design -unresolved You can see the below messages in the log file after the execution of the above commands: COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 7

Info : Done Elaborating Design. [ELAB-3] : Done elaborating 'dtmf_recvr_core'. Computing net loads. Runtime & Memory after 'read_hdl' stamp 'Elaboration' being created for table 'default' Total Time (Wall) | Stage Time (Wall) | % (Wall) | Date - Time | Memory | Stage ---------------------------+---------------------------+------------------+----------------------------+---------------+---------------------- 00:00:05(00:00:00) | 00:00:00(00:00:00) | 0.0( 0.0) | 12:31:31 PM(Jul13) | 241.75 MB | init ---------------------------+---------------------------+-------------------+---------------------------+---------------+---------------------- 00:00:11(00:00:06) | 00:00:06(00:00:06) | 100.0(100.0) | 12:31:37 PM(Jul13) | 345.02 MB | Elaboration ---------------------------+---------------------------+------------------+----------------------------+---------------+---------------------- Number of super-thread servers: 0 (id: default, time_info v1.52) Info: (*N*) indicates data that was populated from previously saved time_info database Checking the design. Unresolved References & Empty Modules ------------------------------------- No unresolved references in design 'dtmf_recvr_core' No empty modules in design 'dtmf_recvr_core' Done Checking the design. Check Design Report -------------------- 11. The following command reads the sdc file, the log file shows following messages: read_sdc ../Constraints/dtmf_recvr_core_gate.sdc Reading file Statistics for commands executed by read_sdc: "create_clock" "current_design" "get_clocks" "get_pins" "get_ports" "set_case_analysis" "set_false_path" "set_input_delay" "set_max_fanout" "set_max_transition" "set_output_delay" Total runtime0 - successful - successful - successful - successful - successful - successful - successful - successful - successful - successful - successful 7 , failed 3 , failed 364 , failed 7 , failed 369 , failed 2 , failed 2 , failed 175 , failed 1 , failed 1 , failed 189 , failed 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 0 (runtime 0.00) 12. The following command generates a lint report which reports, in an abbreviated output, possible timing problems in the design: report timing -lint COPYRIGHT © 2015, CADENCE DESIGN SYSTEMS, INC. ALL RIGHTS RESERVED 8

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