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ISSCC2018文章合集.pdf
Front Cover
Title Page
Copyright
Table of Contents
Reflections
Foreword
Session 1 Overview: Plenary
Paper 1.1: Semiconductor Innovation: Is the party over, or just getting started?
Paper 1.2: Brain-Inspired Technologies: Towards Chips that Think?
Awards
Paper 1.3: Future Mobility- Enhanced Society Enabled by Semiconductor Technology
Paper 1.4: 50 years of Computer Architecture: From the Mainframe CPU to the Domain-Specific TPU and the Open RISC-V Instruction Set
Session 2 Overview: Processors
Paper 2.1: SkyLake-SP: A 14nm 28-Core Xeon® Processor
Paper 2.2: IBM z14TM: 14nm Microprocessor for the Next-Generation Mainframe
Paper 2.3 : An Energy-Efficient Graphics Processor Featuring Fine-Grain DVFS with Integrated Voltage Regulators, Execution-Unit Turbo, and Retentive Sleep in 14nm Tri-Gate CMOS
Paper 2.4: ”Zeppelin": An SoC for Multichip Architectures
Paper 2.5: An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications
Paper 2.6: A 595pW 14pJ/Cycle Microcontroller with Dual-Mode Standard Cells and Self-Startup for Battery-Indifferent Distributed Sensing
Paper 2.7: A cm-Scale Self-Powered Intelligent and Secure IoT Edge Mote Featuring an Ultra-Low-Power SoC in 14nm Tri-Gate CMOS
Session 3 Overview: Analog Techniques
Paper 3.1: A Quiet Digitally Assisted Auto-Zero-Stabilized Voltage Buffer with 0.6pA Input Current and 0.6µV Offset
Paper 3.2: A Regulation-Free Sub-0.5V 16/24MHz Crystal Oscillator for Energy-Harvesting BLE Radios with 14.2nJ Startup Energy and 31.8µW Steady-State Power
Paper 3.3: A CMOS Dual-RC Frequency Reference with ±250ppm Inaccuracy from -45°C to 85°C
Paper 3.4: A 2×20W 0.0013% THD+N Class-D Audio Amplifier with Consistent Performance up to Maximum Power Level
Paper 3.5: A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W Fully Differential Class-D Audio Amplifier with Gm Noise Cancellation and Negative Output-Common-Mode Injection Techniques
Paper 3.6: A 0.96mA Quiescent Current, 0.0032% THD+N, 1.45W Class-D Audio Amplifier with Area-Efficient PWM-Residual-Aliasing Reduction
Paper 3.7: A Low-Power 3.25GS/s 4th-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers for Wideband Analog Signal Processing
Session 4 Overview: mm-Wave Radios for 5G and Beyond
Paper 4.2: A 60GHz 144-Element Phased-Array Transceiver with 51dBm Maximum EIRP and ±60° Beam Steering for Backhaul Application
Paper 4.3: A 23-to-30GHz Hybrid Beamforming MIMO Receiver Array with Closed-Loop Multistage Front-End Beamformers for Full-FoV Dynamic and Autonomous Unknown Signal Tracking and Blocker Rejection
Paper 4.4: A 28GHz Bulk-CMOS Dual-Polarization Phased-Array Transceiver with 24 Channels for 5G User and Basestation Equipment
Paper 4.5: A Reconfigurable 28/37GHz Hybrid-Beamforming MIMO Receiver with Inter-Band Carrier Aggregation and RF-Domain LMS Weight Adaptation
Paper 4.6: A Fully Integrated Scalable W-Band Phased-Array Module with Integrated Antennas, Self-Alignment and Self-Test
Paper 4.7: A 64GHz Full-Duplex Transceiver Front-End with an On-Chip Multifeed Self-Interference-Canceling Antenna and an All-Passive Canceler Supporting 4Gb/s Modulation in One Antenna Footprint
Session 5 Overview: Image Sensors
Paper 5.1: A Back-Illuminated Global-Shutter CMOS Image Sensor with Pixel-Parallel 14b Subthreshold ADC
Paper 5.2: An 8K4K-Resolution 60fps 450ke--Saturation-Signal Organic-Photoconductive-Film Global-Shutter CMOS Image Sensor with In-Pixel Noise Canceller
Paper 5.3: A 1/2.8-inch 24Mpixel CMOS Image Sensor with 0.9μm Unit Pixels Separated by Full-Depth Deep-Trench Isolation
Paper 5.4: A 1/4-inch 3.9Mpixel Low-Power Event-Driven Back-Illuminated Stacked CMOS Image Sensor
Paper 5.5: A 1.1μm-Pitch 13.5Mpixel 3D-Stacked CMOS Image Sensor Featuring 230fps Full-High-Definition and 514fps High-Definition Videos by Reading 2 or 3 Rows Simultaneously Using a Column-Switching Matrix
Paper 5.6: A 2.1μm 33Mpixel CMOS Imager with Multi-Functional 3-Stage Pipeline ADC for 480fps High-Speed Mode and 120fps Low-Noise Mode
Paper 5.7: A 20ch TDC/ADC Hybrid SoC for 240×96-Pixel 10%-Reflection <0.125%-Precision 200m-Range Imaging LiDAR with Smart Accumulation Technique
Paper 5.8: 1Mpixel 65nm BSI 320MHz Demodulated TOF Image Sensor with 3.5μm Global Shutter Pixels and Analog Binning
Paper 5.9: 256×256 45/65nm 3D-Stacked SPAD-Based Direct TOF Image Sensor for LiDAR Applications with Optical Polar Modulation for up to 18.6dB Interference Suppression
Paper 5.10: A 32×32-Pixel Time-Resolved Single-Photon Image Sensor with 44.64μm Pitch and 19.48% Fill-Factor with On-Chip Row/Frame Skipping Features Reaching 800kHz Observation Rate for Quantum Physics Applications
Session 6 Overview: Ultra-High-Speed Wireline
Paper 6.1: A 112Gb/s PAM-4 Transmitter with 3-Tap FFE in 10nm CMOS
Paper 6.2: A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
Paper 6.3: A 4-Lane 1.25-to-28.05Gb/s Multi-Standard 6pJ/b 40dB Transceiver in 14nm FinFET with Independent TX/RX Rate Support
Paper 6.4: A Fully Adaptive 19-to-56Gb/s PAM-4 Wireline Transceiver with a Configurable ADC in 16nm FinFET
Paper 6.5: A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET
Paper 6.6: A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR Transceiver in 28nm FDSOI CMOS
Paper 6.7: A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS
Session 7 Overview: Neuromorphic, Clocking and Security Circuits
Paper 7.1: A 0.0056mm2 All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fsrms Jitter and -249dB FOM
Paper 7.2: A 0.02mm2 Fully Synthesizable Period-Jitter Sensor Using Stochastic TDC Without Reference Clock and Calibration in 10nm CMOS Technology
Paper 7.3: A 0.3-to-1.2V Frequency-Scalable Fractional-N ADPLL with a Speculative Dual-Referenced Interpolating TDC
Paper 7.4: A 55nm Time-Domain Mixed-Signal Neuromorphic Accelerator with Stochastic Synapses and Embedded Reinforcement Learning for Autonomous Micro-Robots
Paper 7.5: An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
Paper 7.6: A Secure Camouflaged Logic Family Using Post-Manufacturing Programming with a 3.6GHz Adder Prototype in 65nm CMOS at 1V Nominal VDD
Paper 7.7: A PUF Scheme Using Competing Oxide Rupture with Bit Error Rate Approaching Zero
Paper 7.8: A 445F2 Leakage-Based Physically Unclonable Function with Lossless Stabilization Through Remapping for IoT Security
Session 8 Overview: Wireless Power and Harvesting
Paper 8.1: A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering
Paper 8.2: A 70W and 90% GaN-Based Class-E Wireless-Power-Transfer System with Automatic-Matching-Point-Search Control for Zero-Voltage Switching and Zero-Voltage-Derivative Switching
Paper 8.3: A Reconfigurable Cross-Connected Wireless-Power Transceiver for Bidirectional Device-to-Device Charging with 78.1% Total Efficiency
Papr 8.4: A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power
Paper 8.5: MISIMO: A Multi-Input Single-Inductor Multi-Output Energy Harvester Employing Event-Driven MPPT Control to Achieve 89% Peak Efficiency and a 60,000× Dynamic Range in 28nm FDSOI
Paper 8.6: A 4.5-to-16µW Integrated Triboelectric Energy-Harvesting System Based on High-Voltage Dual-Input Buck Converter with MPPT and 70V Maximum Input Voltage
Paper 8.7: A Piezoelectric Energy-Harvesting Interface Circuit with Fully Autonomous Conjugate Impedance Matching, 156% Extended Bandwidth, and 0.38μW Power Consumption
Paper 8.8: A 30nA Quiescent 80nW-to-14mW Power-Range Shock-Optimized SECE-Based Piezoelectric Harvesting Interface with 420% Harvested-Energy Improvement
Paper 8.9: A Fully Integrated Split-Electrode Synchronized-Switch-Harvesting-on-Capacitors (SE-SSHC) Rectifier for Piezoelectric Energy Harvesting with Between 358% and 821% Power-Extraction Enhancement
Paper 8.10: A 13.56MHz Time-Interleaved Resonant-Voltage-Mode Wireless-Power Receiver with Isolated Resonator and Quasi-Resonant Boost Converter for Implantable Systems
Session 9 Overview: Wireless Transceivers and Techniques
Paper 9.1: A Multimode 76-to-81GHz Automotive Radar Transceiver with Autonomous Monitoring
Paper 9.2: A 253mW/Channel 4TX/4RX Pulsed Chirping Phased-Array Radar TRX in 65nm CMOS for X-Band Synthetic-Aperture Radar Imaging
Paper 9.3: A Highly Reconfigurable 65nm CMOS RF-to-Bits Transceiver for Full-Band Multicarrier TDD/FDD 2G/3G/4G/5G Macro Basestations
Paper 9.4: A 40Gb/s 6pJ/b RX Baseband in 28nm CMOS for 60GHz Polarization MIMO
Paper 9.5: A 27.8Gb/s 11.5pJ/b 60GHz Transceiver in 28nm CMOS with Polarization MIMO
Paper 9.6: A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver
Paper 9.7: A Broadband and Deep-TX Self-Interference Cancellation Technique for Full-Duplex and Frequency-Domain-Duplex Transceiver Applications
Paper 9.8: A 1.4-to-2.7GHz High-Efficiency RF Transmitter with an Automatic 3FLO-Suppression Tracking-Notch-Filter Mixer Supporting HPUE in 14nm FinFET CMOS
Paper 9.9: A High-Efficiency 28GHz Outphasing PA with 23dBm Output Power Using a Triaxial Balun Combiner
Session 10 Overview: Sensor Systems
Paper 10.1: Chopped Rate-to-Digital FM Gyroscope with 40ppm Scale Factor Accuracy and 1.2dph Bias
Paper 10.2: Personal Inertial Navigation System Employing MEMS Wearable Ground Reaction Sensor Array and Interface ASIC Achieving a Position Accuracy of 5.5m Over 3km Walking Distance Without GPS
Paper 10.3: Multi-Way Interactive Capacitive Touch System with Palm Rejection of Active Stylus for 86" Touch Screen Panels
Paper 10.4: A Noise-Immune Stylus Analog Front-End Using Adjustable Frequency Modulation and Linear-Interpolating Data Reconstruction for Both Electrically Coupled Resonance and Active Styluses
Paper 10.5: A 0.91mW/Element Pitch-Matched Front-End ASIC with Integrated Subarray Beamforming ADC for Miniature 3D Ultrasound Probes
Paper 10.6: Single-Chip Reduced-Wire Active Catheter System with Programmable Transmit Beamforming and Receive Time-Division Multiplexing for Intracardiac Echocardiography
Paper 10.7: A 0.3ppm Dual-Resonance Transformer-Based Drift-Cancelling Reference-Free Magnetic Sensor for Biosensing Applications
Paper 10.8: A 100mK-NETD 100ms-Startup-Time 80×60 Micro-Bolometer CMOS Thermal Imager Integrated with a 0.234mm2 1.89μVrms Noise 12b Biasing DAC
Session 11 Overview: SRAM
Paper 11.1: A 23.6Mb/mm2 SRAM in 10nm FinFET Technology with Pulsed PMOS TVC and Stepped-WL for Low-Voltage Applications
Paper 11.2: A 7nm FinFET SRAM Using EUV Lithography with Dual Write-Driver-Assist Circuitry for Low-Voltage Applications
Paper 11.3: A 5GHz 7nm L1 Cache Memory Compiler for High-Speed Computing and Mobile Applications
Session 12 Overview: DRAM
Paper 12.1: A 16Gb 18Gb/s/pin GDDR6 DRAM with Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Paper 12.2: A 16Gb LPDDR4X SDRAM with an NBTI-Tolerant Circuit Solution, an SWD PMOS GIDL Reduction Technique, an Adaptive Gear-Down Scheme and a Metastable-Free DQS Aligner in a 10nm Class DRAM Process
Paper 12.3: A 1.2V 64Gb 341GB/s HBM2 Stacked DRAM with Spiral Point-to-Point TSV Structure and Improved Bank Group Data Control
Paper 12.4: A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Application
Paper 12.5: A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with Improved Power Distribution and Repair Strategy
Session 13 Overview: Machine Learning and Signal Processing
Paper 13.2: QUEST: A 7.49TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM Using Inductive-Coupling Technology in 40nm CMOS
Paper 13.3: UNPU: A 50.6TOPS/W Unified Deep Neural Network Accelerator with 1b-to-16b Fully-Variable Weight Bit-Precision
Paper 13.4: A 9.02mW CNN-Stereo-Based Real-Time 3D Hand-Gesture Recognition Processor for Smart Mobile Devices
Paper 13.5: An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS
Paper 13.6: A 1.8Gb/s 70.6pJ/b 128×16 Link-Adaptive Near-Optimal Massive MIMO Detector in 28nm UTBB-FDSOI
Paper 13.7: A 232-to-1996KS/s Robust Compressive-Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
Session 14 Overview: High-Resolution ADCs
Paper 14.1: A 50MHz-BW Continuous-Time ΔΣ ADC with Dynamic Error Correction Achieving 79.8dB SNDR and 95.2dB SFDR
Paper 14.2: A 15.2-ENOB Continuous-Time ΔΣ ADC for a 7.3µW 200mVpp-Linear-Input-Range Neural Recording Front-End
Paper 14.3: A 13-ENOB 2nd-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using an Error-Feedback Structure
Paper 14.4: A 1.1mW 200kS/s Incremental ΔΣ ADC with a DR of 91.5dB Using Integrator Slicing for Dynamic Power Reduction
Paper 14.5: A 280μW Dynamic-Zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW
Paper 14.6: A 0.4V 13b 270kS/s SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator
Paper 14.7: A Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL
Session 15 Overview: RF PLLs
Paper 15.1: A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS
Paper 15.2: A 23GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Saw-Tooth Chirp Modulation
Paper 15.3: A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter
Paper 15.4: A Low-Phase-Noise Digital Bang-Bang PLL with Fast Lock Over a Wide Lock Range
Paper 15.5: A Digital Frequency Synthesizer with Dither-Assisted Pulling Mitigation for Simultaneous DCO and Reference Path Coupling
Paper 15.6: A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with -254dB FOM
Paper 15.7: A Dividerless Reference-Sampling RF PLL with -253.5dB Jitter FOM and <-67dBc Reference Spurs
Paper 15.8: An 82-to-108GHz -181dB-FOMT ADPLL Employing a DCO with Split-Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC
Session 16 Overview: Advanced Optical and Wireline Techniques
Paper 16.2: A 28Gb/s Transceiver with Chirp-Managed EDC for DML Systems
Paper 16.3: A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS
Paper 16.4: A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b Wireline Transceiver Equalizing 27dB Loss at 10Gb/s with Clock-Domain Encoding Using Integrated Pulse-Width Modulation (iPWM) in 65nm CMOS
Paper 16.5: A 20Gb/s Transceiver with Framed-Pulsewidth Modulation in 40nm CMOS
Paper 16.6: A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly Reflective Memory Interfaces
Paper 16.7: A 126mW 56Gb/s NRZ Wireline Transceiver for Synchronous Short-Reach Applications in 16nm FinFET
Paper 16.8: A 1.17pJ/b 25Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication in 16nm CMOS Using a Process- and Temperature-Adaptive Voltage Regulator
Paper 16.9: A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
Session 17 Overview: Technologies for Health and Society
Paper 17.2: 4-Camera VGA-Resolution Capsule Endoscope with 80Mb/s Body-Channel Communication Transceiver and Sub-cm Range Capsule Localization
Paper 17.3: A 0.3V Biofuel-Cell-Powered Glucose/Lactate Biosensing System Employing a 180nW 64dB SNR Passive ΔΣ ADC and a 920MHz Wireless Transmitter
Paper 17.4: A 0.28mΩ-Sensitivity 105dB-Dynamic-Range Electrochemical Impedance Spectroscopy SoC for Electrochemical Gas Detection
Paper 17.5: 50nW 5kHz-BW Opamp-Less ΔΣ Impedance Analyzer for Brain Neurochemistry Monitoring
Paper 17.6: A 200Mb/s Inductively Coupled Wireless Transcranial Transceiver Achieving 5e-11 BER and 1.5pJ/b Transmit Energy Efficiency
Paper 17.7: A 330µm×90µm Opto-Electronically Integrated Wireless System-on-Chip for Recording of Neural Activities
Paper 17.8: A 665µW Silicon Photomultiplier-Based NIRS/EEG/EIT Monitoring ASIC for Wearable Functional Brain Imaging
Paper 17.9: A Recursive-Memory Brain-State Classifier with 32-Channel Track-and-Zoom Δ2Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators
Session 18 Overview: Adaptive Circuits and Digital Regulators
Paper 18.1: Droop Mitigation Using Critical-Path Sensors and an On-Chip Distributed Power Supply Estimation Engine in the z14™ Enterprise Processor
Paper 18.2: A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor
Paper 18.3: A 2.5µW 0.0067mm2 Automatic Back-Biasing Compensation Unit Achieving 50% Leakage Reduction in FDSOI 28nm over 0.35-to-1V VDD Range
Paper 18.4: A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS
Paper 18.5: A Fully Integrated 40pF Output Capacitor Beat-Frequency-Quantizer-Based Digital LDO with Built-In Adaptive Sampling and Active Voltage Positioning
Paper 18.6: A 500mA Analog-Assisted Digital-LDO-Based On-Chip Distributed Power Delivery Grid with Cooperative Regulation and IR-Drop Reduction in 65nm CMOS
Paper 18.7: A Sub-1.55mV-Accuracy 36.9ps-FOM Digital-Low-Dropout Regulator Employing Switched-Capacitor Resistance
Paper 18.8: A High-Efficiency and Fast-Transient Digital-Low-Dropout Regulator with the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
Session 19 Overview: Sensors and Interfaces
Paper 19.1: An 8b Subthreshold Hybrid Thermal Sensor with ±1.07°C Inaccuracy and Single-Element Remote-Sensing Technique in 22nm FinFET
Paper 19.2: A 0.25mm2 Resistor-Based Temperature Sensor with an Inaccuracy of 0.12°C (3σ) from -55°C to 125°C and a Resolution FOM of 32fJ·K2
Paper 19.3: A 0.53pJ·K2 7000μm2 Resistor-Based Temperature Sensor with an Inaccuracy of ±0.35°C (3σ) in 65nm CMOS
Paper 19.4: A ±4A High-Side Current Sensor with 25V Input CM Range and 0.9% Gain Error from -40°C to 85°C Using an Analog Temperature Compensation Technique
Paper 19.5: A Current-Measurement Front-End with 160dB Dynamic Range and 7ppm INL
Paper 19.6: A 2.5nJ Duty-Cycled Bridge-to-Digital Converter Integrated in a 13mm3 Pressure-Sensing System
Paper 19.7: A 21.8b Sub-100μHz 1/f Corner 2.4μV-Offset Programmable-Gain Read-Out IC for Bridge Measurement Systems
Paper 19.8: A Phase-Domain Readout Circuit for a CMOS-Compatible Thermal-Conductivity-Based Carbon Dioxide Sensor
Session 20 Overview: Flash-Memory Solutions
Paper 20.1: A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology
Paper 20.2: A Flash Memory Controller for 15μs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3μs Read Time
Paper 20.3: A 1Tb 4b/Cell 64-Stacked-WL 3D NAND Flash Memory with 12MB/s Program Throughput
Session 21 Overview: Extending Silicon and its Applications
Paper 21.1: Mixed-Signal Programmable Non-Linear Interface for Resource-Efficient Multi-Sensor Analytics
Paper 21.2: A 1μW Voice Activity Detector Using Analog Feature Extraction and Digital Deep Neural Network
Paper 21.3: 32GHz Resonant-Fin Transistors in 14nm FinFET Technology
Paper 21.4: A 10Gb/s Si-Photonic Transceiver with 150μW 120μs-Lock-Time Digitally Supervised Analog Microring Wavelength Stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks
Paper 21.5: A 286F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack
Paper 21.6: An 8-Channel 13GHz ESR-on-a-Chip Injection-locked VCO-array achieving 200μM-Concentration Sensitivity
Session 22 Overview: Gigahertz Data Converters
Paper 22.1: A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at Nyquist in 14nm CMOS FinFET
Paper 22.2: A 16b 6GS/s Nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS
Paper 22.3: A 16b 12GS/s Single/Dual-Rate DAC with Successive Bandpass Delta-Sigma Modulator Achieving
Session 23 Overview: LO Generation
Paper 23.1: A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers
Paper 23.2: A >40dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55nm CMOS
Paper 23.3: A 22.8-to-43.2GHz Tuning-Less Injection-Locked Frequency Tripler Using Injection-Current Boosting with 76.4% Locking Range for Multiband 5G Applications
Paper 23.4: A 301.7-to-331.8GHz Source with Entirely On-Chip Feedback Loop for Frequency Stabilization in 0.13μm BiCMOS
Paper 23.5: An Inverse-Class-F CMOS VCO with Intrinsic-High-Q 1st- and 2nd-Harmonic Resonances for 1/f2-to-1/f3 Phase-Noise Suppression Achieving 196.2dBc/Hz FOM
Paper 23.6: A Quad-Core 15GHz BiCMOS VCO with -124dBc/Hz Phase Noise at 1MHz Offset, -189dBc/Hz FOM, and Robust to Multimode Concurrent Oscillations
Paper 23.7: A 7.4-to-14GHz PLL with 54fsrms Jitter in 16nm FinFET for Integrated RF-Data-Converter SoCs
Session 24 Overview: GaN Drivers and Converters
Paper 24.1: A 2MHz 150-to-400V Input Isolated DC-DC Bus Converter with Monolithic Slope-Sensing ZVS Detection Achieving 13ns Turn-On Delay and 1.6W Power Saving
Paper 24.2: A Fully Integrated Three-Level 11.6nC Gate Driver Supporting GaN Gate Injection Transistors
Paper 24.3: A 3-to-40V VIN 10-to-50MHz 12W Isolated GaN Driver with Self-Excited tdead Minimizer Achieving 0.2ns/0.3ns tdead, 7.9% Minimum Duty Ratio and 50V/ns CMTI
Session 25 Overview: Clock Generation for High-Speed Links
Paper 25.1: A 4-to-16GHz Inverter-Based Injection-Locked Quadrature Clock Generator with Phase Interpolators for Multi-Standard I/Os in 7nm FinFET
Paper 25.2: A 5GHz 370fsrms 6.5mW Clock Multiplier Using a Crystal-Oscillator Frequency Quadrupler in 65nm CMOS
Paper 25.3: A Fractional-N Digital PLL with Background-Dither-Noise-Cancellation Loop Achieving <-62.5dBc Worst-Case Near-Carrier Fractional Spurs in 65nm CMOS
Paper 25.4: A -242dB FOM and -75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC
Session 26 Overview: RF Techniques for Communication and Sensing
Paper 26.1: A 0.55-to-0.9GHz 2.7dB NF Full-Duplex Hybrid-Coupler Circulator with 56MHz 40dB TX SI Suppression
Paper 26.2: A 62-to-68GHz Linear 6Gb/s 64QAM CMOS Doherty Radiator with 27.5%/20.1% PAE at Peak/6dB-Back-off Output Power Leveraging High-Efficiency Multi-Feed Antenna-Based Active Load Modulation
Paper 26.3: A 69-to-79GHz CMOS Multiport PA/Radiator with +35.7dBm CW EIRP and Integrated PLL
Paper 26.4: A 28GHz 41%-PAE Linear CMOS Power Amplifier Using a Transformer-Based AM-PM Distortion-Correction Technique for 5G Phased Arrays
Paper 26.5: A Compact Dual-Band Digital Doherty Power Amplifier Using Parallel-Combining Transformer for Cellular NB-IoT Applications
Paper 26.6: A Continuous-Mode Harmonically Tuned 19-to-29.5GHz Ultra-Linear PA Supporting 18Gb/s at 18.4% Modulation PAE and 43.5% Peak PAE
Paper 26.7: A Coupled-RTWO-Based Subharmonic Receiver Front-End for 5G E-Band Backhaul Links in 28nm Bulk CMOS
Paper 26.8: A 12mW 70-to-100GHz Mixer-First Receiver Front-End for mm-Wave Massive-MIMO Arrays in 28nm CMOS
Paper 26.9: A 13th-Order CMOS Reconfigurable RF BPF with Adjustable Transmission Zeros for SAW-Less SDR Receivers
Paper 26.10: A 128-Pixel 0.56THz Sensing Array for Real-Time Near-Field Imaging in 0.13µm SiGe BiCMOS
Session 27 Overview: Power-Converter Techniques
Paper 27.1: A 0.22-to-2.4V-Input Fine-Grained Fully Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI) Topology Achieving 84.1% Peak Efficiency at 13.2mW/mm2
Paper 27.2: A 10MHz Time-Domain-Controlled Current-Mode Buck Converter with 8.5% to 93% Switching Duty Cycle
Paper 27.3: An 86% Efficiency SIMO DC-DC Converter with One Boost, One Buck, and a Floating Output Voltage for Car-Radio
Paper 27.4: A 97% High-Efficiency 6µs Fast-Recovery-Time Buck-Based Step-Up/Down Converter with Embedded 1/2 and 3/2 Charge-Pumps for Li-Ion Battery Management
Paper 27.5: A 95.2% Efficiency Dual-Path DC-DC Step-Up Converter with Continuous Output Current Delivery and Low Voltage Ripple
Paper 27.6: An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for 80MHz LTE-Advanced Transmitter and 31dBm PA Output Power for HPUE in 0.153μm CMOS
Paper 27.7: A 2TX Supply Modulator for Envelope-Tracking Power Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and Power Class-2 High-Power User Equipment
Paper 27.8: 94% Power-Recycle and Near-Zero Driving-Dead-Zone N-Type Low-Dropout Regulator with 20mV Undershoot at Short-Period Load Transient of Flash Memory in Smart Phone
Paper 27.9: An On-Chip Resonant-Gate-Drive Switched-Capacitor Converter for Near-Threshold Computing Achieving 70.2% Efficiency at 0.92A/mm2 Current Density and 0.4V Output
Session 28 Overview: Wireless Connectivity
Paper 28.1: An 802.11ax 4×4 Spectrum-Efficient WLAN AP Transceiver SoC Supporting 1024QAM with Frequency-Dependent IQ Calibration and Integrated Interference Analyzer
Paper 28.2: An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS
Paper 28.3: A 0.8V 0.8mm2 Bluetooth 5/BLE Digital-Intensive Transceiver with a 2.3mW Phase-Tracking RX Utilizing a Hybrid Loop Filter for Interference Resilience in 40nm CMOS
Paper 28.4: A 0.45V Sub-mW All-Digital PLL in 16nm FinFET for Bluetooth Low-Energy (BLE) Modulation and Instantaneous Channel Hopping Using 32.768kHz Reference
Paper 28.5: A 0.2V Energy-Harvesting BLE Transmitter with a Micropower Manager Achieving 25% System Efficiency at 0dBm Output and 5.2nW Sleep Power in 28nm CMOS
Paper 28.6: A -76dBm 7.4nW Wakeup Radio with Automatic Offset Compensation
Paper 28.7: A 14.5mm2 8nW -59.7dBm-Sensitivity Ultrasonic Wake-Up Receiver for Power-, Area-, and Interference-Constrained Applications
Paper 28.8: A 5.8GHz Power-Harvesting 116μm×116μm "Dielet" Near-Field Radio with On-Chip Coil Antenna
Session 29 Overview: Advanced Biomedical Systems
Paper 29.1: Creating Neural "Co-Processors" to Explore Treatments for Neurological Disorders
Paper 29.2: A Fully Immersible Deep-Brain Neural Probe with Modular Architecture and a Delta-Sigma ADC Integrated Under Each Electrode for Parallel Readout of 144 Recording Sites
Paper 29.3: A 16384-Electrode 1024-Channel Multimodal CMOS MEA for High-Throughput Intracellular Action Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications
Paper 29.4: A 0.13µm CMOS SoC for Simultaneous Multichannel Optogenetics and Electrophysiological Brain Recording
Paper 29.5: A mm-Sized Free-Floating Wirelessly Powered Implantable Optical Stimulating System-on-a-Chip
Paper 29.6: A 92dB Dynamic Range Sub-μVrms-Noise 0.8μW/ch Neural-Recording ADC Array with Predictive Digital Autoranging
Paper 29.7: A 110dB-CMRR 100dB-PSRR Multi-Channel Neural-Recording Amplifier System Using Differentially Regulated Rejection Ratio Enhancement in 0.18µm CMOS
Paper 29.8: A 43.4µW Photoplethysmogram-Based Heart-Rate Sensor Using Heart-Beat-Locked Loop
Session 30 Overview: Emerging Memories
Paper 30.1: An N40 256K×44 Embedded RRAM Macro with SL-Precharge SA and Low-Voltage Current Limiter to Improve Read and Write Performance
Paper 30.2: A 1Mb 28nm STT-MRAM with 2.8ns Read Access Time at 1.2V VDD Using Single-Cap Offset-Cancelled Sense Amplifier and In-situ Self-Write-Termination
Paper 30.3: A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access Time for Fast and Reliable Read Applications
Paper 30.4: A 20ns-Write 45ns-Read and 1014-Cycle Endurance Memory Module Composed of 60nm Crystalline Oxide Semiconductor Transistors
Session 31 Overview: Computation in Memory for Machine Learning
Paper 31.1: Conv-RAM: An Energy-Efficient SRAM with Embedded Convolution Computation for Low-Power CNN-Based Machine Learning Applications
Paper 31.2: A 42pJ/Decision 3.12TOPS/W Robust In-Memory Machine Learning Classifier with On-Chip Training
Paper 31.3: Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study
Paper 31.4: A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors
Paper 31.5: A 65nm 4Kb Algorithm-Dependent Computing-in-Memory SRAM Unit-Macro with 2.3ns and 55.8TOPS/W Fully Parallel Product-Sum Operation for Binary DNN Edge Processors
ISSCC 2018 Glossary
ISSCC Tutorials
T1: Low-Jitter PLLs for Wireless Transceivers
T2: Nonvolatile Circuits for Memory, Logic, and Artificial Intelligence
T3: Basics of Quantum Computing
T4: Error-Correcting Codes in 5G/NVM Applications
T5: Hybrid Design of Analog-to-Digital Converters
T6: Single-Photon Detection in CMOS
T7: Basics of Adaptive and Resilient Circuits
T8: Fundamentals of Switched-Mode Power-Converter Design
T9: Digital RF Transmitters
T10: ADC-Based Serial Links: Design and Analysis
ISSCC Forums
F1: Intelligent Energy-Efficient Systems at the Edge of IoT
F2: FinFETs & FDSOI – A Mixed Signal Circuit Designer’s Perspective
F3: Circuits and Architectures for Wireless Sensing, Radar and Imaging
F4: Circuit and System Techniques for mm-Wave Multi-Antenna Systems
F5: Advanced Optical Communication: From Devices, Circuits, and Architectures to Algorithms
F6: Advances in Energy Efficient Analog Design
ISSCC Evening Events
EE1: Student Research Preview (SRP)
Session 1: Communications and Power
Session 2: Deep Learning and Biomedical Circuits
Session 3: Memory, Sensors and Mixed-Signal Circuits
EE2: Workshop on Circuits for Social Good
EE3: Industry Showcase
EE4: Figures-of-Merit on Trial
EE5: Lessons Learned – Great Circuits That Didn’t Work –
EE6: Can Artificial Intelligence Replace My Job?
ISSCC Short Course: Hardware Approaches to Machine Learning and Inference
SC1: Introduction to Machine Learning and Inference
SC2: Algorithm and Implementation Co-Design for Learning and Inference
SC3: Efficient Edge Solutions for Deep Learning Applications
SC4: Efficient Alternatives and Extensions to Deep-Learning-Based Solutions
Index to Authors
ISSCC 2018 Executve Committee
ISSCC 2018 Technical Editors
ISSCC 2018 Multi-Media Coordinator
ISSCC 2018 ITPC
ISSCC European Regional Subcommittee
ISSCC Far East Regional Subcommittee
Conference Space Layout
ISSCC 2019 Call for Papers
ISSCC 2018 Timetable
Back Cover
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DIGEST
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TECHNICAL
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VOLUME SIXTY-ONE
ISSN 0193-6530
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2018 IEEE INTERNATIONAL
SOLID-STATE CIRCUITS CONFERENCE
DIGEST OF TECHNICAL PAPERS
First Edition
February 2018
IEEE Catalog Number CFP18ISS-PRT
DIGEST OF TECHNICAL PAPERS
1
2018 IEEE International Solid-State Circuits Conference
DIGEST OF TECHNICAL PAPERS
Copyright and Reprint Permission:
Abstracting is permitted with credit to the source. Libraries are permitted to
photocopy beyond the limit of U.S. copyright law for private use of patrons those
articles in this volume that carry a code at the bottom of the first page, provided
the per-copy fee indicated in the code is paid through Copyright Clearance Center,
222 Rosewood Drive, Danvers, MA 01923. For reprint or republication
permission, email to IEEE Copyrights Manager at pubs-permissions@ieee.org.
All rights reserved. Copyright ©2018 by IEEE.
PREPRESS IN THE UNITED STATES OF AMERICA
by S3 iPublishing, Inc.
Lisbon Falls, Maine
PRINTED IN THE UNITED STATES OF AMERICA
by Penmor Lithographers
Lewiston, Maine
VOLUME 61
IEEE Cat. No. CFP18ISS-PRT
ISBN Softbound 978-1-5090-4939-4
Library of Congress Number 81-644810
ISSN 0193-6530
Publisher and Managing Editor: Laura C. Fujino
Technical Editors: Jason H. Anderson, Leonid Belostotski, Dustin Dunwell, Vincent Gaudet,
Glenn Gulak, James W. Haslett, David Halupka, Kenneth C. Smith
2
2018 IEEE International Solid-State Circuits Conference
978-1-5090-4940-0/18/$31.00 ©2018 IEEE
TABLE OF CONTENTS
REFLECTIONS.................................................................................4
FOREWORD....................................................................................5
AWARDS.......................................................................................19
TUTORIALS
TUTORIALS 1-10.......................................................498
FORUMS
PAPER SESSIONS
1 Plenary Session.......................................................................6
2 Processors.............................................................................32
3 Analog Techniques.................................................................48
4 mm-Wave Radios for 5G and Beyond.....................................64
5 Image Sensors.......................................................................78
6 Ultra-High-Speed Wireline....................................................100
7 Neuromorphic, Clocking and Security Circuits.....................116
F1 Intelligent Energy-Efficient Systems at the Edge of IoT.....502
F2 FinFETs & FDSOI – ............................................................505
A Mixed Signal Circuit Designer’s Perspective
F3 Circuits and Architectures for Wireless Sensing,...............508
Radar and Imaging
F4 Circuit and System Techniques for....................................511
mm-Wave Multi-Antenna Systems
F5 Advanced Optical Communication:....................................514
From Devices, Circuits, and Architectures to Algorithms
8 Wireless Power and Harvesting............................................134
F6 Advances in Energy-Efficient Analog Design......................517
9 Wireless Transceivers and Techniques.................................156
10 Sensor Systems...................................................................176
11 SRAM...................................................................................194
12 DRAM..................................................................................202
EVENING EVENTS
EE1 Student Research Preview: Short Presentations................520
with Poster Session
13 Machine Learning and Signal Processing.............................214
EE2 Workshop on Circuits for Social Good..............................523
14 High-Resolution ADCs..........................................................228
EE3 Industry Showcase.............................................................525
15 RF PLLs................................................................................244
16 Advanced Optical and Wireline Techniques..........................262
17 Technologies for Health and Society.....................................280
18 Adaptive Circuits and Digital Regulators...............................398
19 Sensors and Interfaces........................................................316
20 Flash-Memory Solutions......................................................334
21 Extending Silicon and its Applications..................................342
22 Gigahertz Data Converters....................................................356
23 LO Generation......................................................................364
24 GaN Drivers and Converters.................................................380
25 Clock Generation for High-Speed Links................................388
26 RF Techniques for Communication and Sensing..................398
27 Power-Converter Techniques...............................................420
28 Wireless Connectivity...........................................................440
EE4 Figures-of-Merit on Trial....................................................527
EE5 Lessons Learned – Great Circuits That Didn’t Work –......529
(Oops, If Only I Had Known!)
EE6 Can Artificial Intelligence Replace My Job?.......................531
The Dawn of a New IC Industry with AI
SHORT COURSE
SC Hardware Approaches to Machine Learning and Inference..533
INDEX TO AUTHORS...................................................................535
COMMITTEES...............................................................................543
CONFERENCE LAYOUT...............................................................546
2019 CALL FOR PAPERS............................................................547
29 Advanced Biomedical Systems.............................................458
CONFERENCE TIMETABLE...........................................................548
30 Emerging Memories.............................................................476
31 Computation in Memory for Machine Learning.....................486
DIGEST OF TECHNICAL PAPERS
3
Reflections
What you see before you this year, is the result of many many years of continuous iterative refinement of the submission
process and information processing. This year, we continue to provide a simplified printed Digest, in which the continuation
pages (typically including a micrograph and occasionally summary data) are not included, but are available in the Digest
download and in IEEE Xplore. In order to be more-green, we continue to use partially recycled paper.
Again, this year, we have a technical editorial group (listed below) under the direction of a managing editor (Laura Chizuko
Fujino). Once again, we emphasize nearly full technical and language editing of most papers, as the need dictates.
In recognition of the large amount of work leading to the Digest open before you, I wish to acknowledge a great many
individuals: Alison Burdett, Eugenio Cantatore, Anantha Chandrakasan, members of the ITPC, and all of the authors, for their
individual contributions; Brad Phillips, and Mira Digital Publishing, for Web-based and other preparatory support, including
continuing improvement and facilitation of the paper-review and pre-voting process in a new double-blind world, as well as
preparation and implementation of the downloads available at the Conference; Steve Bonney, and S3 iPublishing, for author
and Session-Chair interaction, for figure layout, for paper formatting, for pre-press preparation, for printer interfacing, and for
general assistance; Melissa Widerkehr, and Widerkehr and Associates, for general interfacing, problem-solving, and coordination; Jason Anderson (University
of Toronto), Leo Belostotski (University of Calgary), Dustin Dunwell (Huawei Technologies), Vincent Gaudet (University of Waterloo), Glenn Gulak (University
of Toronto), David Halupka (Kapik Integration), James Haslett (University of Calgary), and K.C. Smith (University of Toronto), as technical editors for heroic
effort on the usual tight schedule.
My sincere thanks to you all!
Laura Chizuko Fujino
ISSCC Director of Publications and Presentations
February 2018
4
2018 IEEE International Solid-State Circuits Conference
978-1-5090-4940-0/18/$31.00 ©2018 IEEE
Foreword: Silicon Engineering a Social World
Welcome to the 65th
International Solid-State Circuits
Conference! The Conference continues its tradition of
showcasing the most-advanced and innovative work from
industry and academe around the world, in integrated circuits
and systems. The geographical distribution of the accepted
technical papers reflects the truly international character of
the Conference: 44% of the accepted papers are from North
America, 39% are from the Far East, and 17% are from
Europe. Of these papers, 60% are from academe, 27% are
from industry, 1% are from research institutions/labs, and
12% were joint submissions from industry and academe.
Continuing the practice introduced last year, the ISSCC paper
selection followed a double-blind review process with
anonymized manuscripts, which has emerged as the best-
known practice within the broader technical community.
The 2018 Conference theme is “Silicon Engineering a Social World.” This theme reflects how
continued advances in solid-state circuits and systems have brought evermore powerful
communication and computational capabilities into mobile form factors. Such ubiquitous smart
devices lie at the heart of a revolution shaping how we connect, collaborate, build relationships,
and share information. These social technologies allow people to maintain connections and
support networks that otherwise would not be possible; they provide the ability to access
information instantaneously and from any location, thereby helping to shape the world's events
and culture, empowering citizens of all nations, providing social networks allowing worldwide
communities to develop and bond with common interests. ISSCC, as the flagship conference in
solid-state circuits, will cover the latest advancements surrounding these trends.
The Conference will begin with the Plenary Session, where four innovators will share their views
on challenges and opportunities in our field. The first talk by Vince Roche of Analog Devices will
discuss challenges for semiconductor innovation within a highly competitive global environment,
where business pressures drive companies to avoid risk and to develop new products following
a model of incrementalism. Roche argues that such pressures must be resisted if the
semiconductor industry is to continue to carry the mantle of technological leadership and maintain
a bright future. Technical innovation and new discoveries are the theme of the following talk from
Barbara de Salvo of CEA-Leti, which discusses new paradigms for computing based on recent
advances in understanding of cognitive and neuro-sciences. By understanding how the human
brain processes information through distributed and connected pathways, new models of
semiconductor computing are likely to be developed to enable step-change improvements in
processing efficiency. The third talk from Yukihiro Kato of Denso, focuses on the role of
semiconductor technology in driving, a once in a lifetime transformation in the automotive
industry. Technologies once seen to be in the realm of science fiction, such as electric vehicles
and autonomous cars, are rapidly becoming a reality. Kato outlines some of the technical
challenges on the way to the future ‘mobility-enhanced society’, and describes semiconductor
innovations in progress to overcome them. The final talk from David Patterson of Google and UC
Berkeley review 50 years of innovation in computer architecture. From mainframe computers in
the 1960s to the dominant RISC architecture of recent times, Patterson gives an entertaining and
informative insight into the technical and business constraints which underpinned these rapid
developments. With the end of Moore’s Law slowing the pace of improvements due to scaling,
Patterson describes how this slowdown is actually rejuvenating innovation in computer
architectures, as future performance improvements cannot come from scaling alone.
The ISSCC 2018 Technical Program consists of 207 outstanding technical papers distributed over
31 thematic sessions which include, as well, 5 system-focussed invited talks. In addition to these
regular sessions, the Conference continues to promote educational activities in other ways: a
series of ten 90-minute introductory tutorials, as well as six full-day expert-oriented forums, and
a short course.
This year, the 5 invited talks focus on systems applications linked to silicon innovation: Thomas
Cameron from Analog Devices will discuss architectures and technologies for 5G mmWave radio
(Monday afternoon); Olivier Temam of Google will present aspects of edge machine-learning
processing (Tuesday afternoon); Ashok Krishnamoorthy of Axalume will present insights on the
anatomy of a 20Tb/s switch card (Tuesday afternoon); Katsu Watanabe of Fujitsu will outline how
IoT sensors and Cloud computing are being used for next-generation food and agriculture
production (Tuesday afternoon); Tim Denison of Medtronic will describe research towards the
creation of neural co-processors to explore treatments for neurological disorders (Wednesday
afternoon).
On Sunday, the 10 Tutorials cover a wide range of topics: “Low-Jitter PLLs for Wireless
Transceivers”, “Nonvolatile Circuits for Memory, Logic, and Artificial Intelligence”, “Basics of
Quantum Computing”, “Error-Correcting Codes in 5G/NVM Applications”, “Hybrid Design of
Analog-to-Digital Converters”, “Single-Photon Detection in CMOS”, “Basics of Adaptive and
Resilient Circuits”, “Fundamentals of Switched-Mode Power-Converter Design”, “Digital RF
Transmitters” and “ADC-Based Serial Links: Design and Analysis”. These Tutorials are given by
top experts in the field and offer an opportunity to experience an introduction to and overview of
important developments in each topic area.
The goal of our 6 all-day Forums is to update experts on advanced developments in their fields:
On Sunday, February 11th, two forums will be held in parallel: “Intelligent Energy-Efficient Systems
at the Edge of IoT” and “FinFETs & FDSOI – A Mixed Signal Circuit Designer’s Perspective”.
On Thursday, February 15th, four forums will be offered in parallel: “Circuits and Architectures for
Wireless Sensing, Radar and Imaging”, “Circuit and System Techniques for mm-Wave Multi-
Antenna Systems”, “Advanced Optical Communication: From Devices, Circuits, and Architectures
to Algorithms” and “Advances in Energy Efficient Analog Design”. Also on Thursday is an all-day
Short Course on “Hardware Approaches to Machine Learning and Inference”, which will explore
design aspects from algorithms to the implementation of efficient architectures for machine
learning.
As usual, the Conference will feature a variety of evening events that combine education on timely
topics and entertainment. On Sunday evening, a workshop co-sponsored by the IEEE Solid State
Circuits Society (SSCS) on “Circuits for Social Good” aims to highlight various ways that circuits
designers can help address some of the most important challenges facing society today, ranging
from healthcare to energy conservation. The workshop will feature keynote presentations, as well
as interactive ‘round tables’ where attendees can join in group discussions.
On Monday evening, two sessions will be held in parallel. The first panel session “Figures-of-Merit
on Trial” will probe the weaknesses and strengths of popular analog FOMs in an entertaining and
educational way, with one panellist defending the FOM, and another acting as the prosecutor, with
the audience acting as the jury. The second session, the “Industry Showcase” will highlight how
advances in silicon circuits, SoCs, and systems are fueling the most innovative industrial
applications and products of the future. The event will feature short presentations, as well as
interactive demonstrations from each of the Showcase participants. These participants were
chosen through a nomination and voting process by members of the Industry Showcase
Committee.
On Tuesday evening, an entertaining and motivating panel discussion reviews “Lessons Learned
– Great Circuits That Didn’t Work – (Oops, If Only I Had Known!)”. As well as provide a forum in
which recognized experts share their past mistakes and failures, (and disclose lessons learned),
the audience is invited to contribute “learning experiences” (in less than a minute). Also on
Tuesday evening, a panel will discuss “Can Artificial Intelligence Replace My Job? The Dawn of a
New IC Industry with AI”. Diverse experts will share their vision on the daunting new development
of AI in our business.
Two Demonstration Sessions, which have become an integral part of the Conference, will be held
during the social hours on Monday and Tuesday. These sessions provide an opportunity to witness
live demos of devices described in over 50 selected papers, and to engage in face-to-face
discussions with the authors. Also, the Student-Research Preview held on Sunday evening will
allow graduate students from around the globe to interact with each other and with attendee
technical experts from both academe and industry. The students will have the opportunity to briefly
introduce their work prior to the subsequent Poster Session, in which they will benefit from
attendee feedback.
The high standards that we associate with ISSCC are a result of the diligent volunteer work of the
International Technical-Program Committee (ITPC). This year, the ITPC consists of 156 members
from industry and academe, organized into eleven technical subcommittees. Each member has
spent a significant amount of time reviewing the submitted papers, planning and organizing
evening sessions, and educational events, preparing the Advance Program, Press-Kit, and Digest
material, and performing session-chair/organizer duties. I am especially indebted to the
Subcommittee Chairs for their leadership in overseeing these tasks: Kofi Makinwa (Analog), Un-
Ku Moon (Data Converters), Byeong-gyu Nam (Digital Architectures & Systems), Edith Beigné
(Digital Circuits), Makoto Ikeda (Imagers/MEMS/Medical/Displays), Leland Chang (Memory), Axel
Thomsen (Power Management), Piet Wambacq (RF), Makoto Nagata (Technology Directions),
Stefano Pellerano (Wireless), and Frank O'Mahony (Wireline). Also, I must thank the leadership
team of the Regional Committees: Marian Verhelst and Kostas Doris from the European Region,
and Sungdae Choi and Tai-Cheng Lee from the Far-East Region. Additionally, I have immensely
benefited from the help of the ISSCC 2018 Program Vice-Chair, Eugenio Cantatore, and the ISSCC
2017 Program Chair, Boris Murmann.
ISSCC would not be possible without the help of many other individuals that deliver high-quality
support work behind the scenes. I want to acknowledge Melissa Widerkehr and Widerkehr and
Associates for their invaluable support with Conference operations and arrangements. I am grateful
to Brad Phillips and MIRA Digital Publishing for their assistance with the electronic manuscript
submission, pre-voting, and assembly of the Advance Program, as well as the Digest, and to Steve
Bonney and S3 iPublishing for page layout and facilities coordination. I must also thank the
Technical Editors: Jason Anderson, Leo Belostotski, Dustin Dunwell, Vincent Gaudet, Glenn Gulak,
James Haslett, and Dave Halupka both as an Editor and multi-media-coordinator. Also, special
thanks go to Laura Fujino and Kenneth Smith for their unrelenting help with many aspects of the
Conference, including the paper submission process, preparation of the Advance Program, the
Press Kit, the Digest, and Tutorial and Short Course DVDs, as well as editing and presentation
preparation. Also thanks to Denis Daly for his leading role in the Press Kit preparation, to Ali
Sheikholeslami for his coordination of the Tutorials and Short Course, to Dan Friedman for
organizing the Short Course, to Andreia Cathelin for leading the Forums, to SeongHwan Cho for
organizing the Student-Research Preview, to Uming Ko for organizing the Demonstration Sessions,
to Trudy Stetzler for managing the Conference website and A/V coordination, and to Bryant Griffin
for his financial oversight for the Conference.
We are indebted as well to an unusual group of volunteer graduate students from the University
of Toronto, who through their individual technical expertise ensure the orderly conduct of the
presentations in each session, as well as countless other behind-the-scene activities.
Finally, my special acknowledgement goes to Anantha Chandrakasan, the ISSCC Conference Chair,
for his attentive and visionary leadership, and for the many conference improvements that he has
initiated and overseen over the past several years. His selfless dedication to maintain excellence
in all aspects of ISSCC has been a true inspiration and reward in my years serving on the Technical
Program Committee.
I look forward to seeing you at the Conference and wish you an enjoyable ISSCC 2018!
Alison Burdett
ISSCC 2018 International Technical-Program Chair
DIGEST OF TECHNICAL PAPERS
5
ISSCC 2018 / SESSION 1 / PLENARY / OVERVIEW
Session 1 Overview
Plenary Session
Chair: Anantha Chandrakasan
Massachusetts Institute of Technology, Cambridge, MA
ISSCC Conference Chair
Associate Chair: Alison Burdett
Sensium Healthcare, Abingdon, United Kingdom
ISSCC International Technical Program Chair
The Plenary Session will begin with welcome remarks, and an introduction from the Conference Chair, Anantha Chandrakasan. Then, Alison Burdett, the Technical
Program Chair, will provide a summary of the 2018 Technical Program. The Plenary Session features four keynote speakers, who are leaders in their respective
fields and collectively represent the broad spectrum of our industry. An Awards Ceremony that recognizes major technical and professional accomplishments,
presented by the IEEE, Solid-State-Circuits Society (SSCS), and ISSCC, will take place following second Plenary talk.
Overall, the four Plenary talks address a wide variety of topical issues:
In today’s highly competitive global environment, business pressures are driving the semiconductor industry to avoid risk and to develop new products following
a model of incrementalism and consolidation. Vince Roche, CEO of Analog Devices argues that such pressures must be resisted if the semiconductor industry is
to continue to carry the mantle of technological leadership and maintain a bright future. He concludes that application challenges such as the spread of pervasive
ubiquitous sensing, rapid advances in artificial intelligence, heterogeneous integration, and the continued impact of digitization on virtually every industry on earth,
will require more, not less, semiconductor innovation.
Recent developments in cognitive and neuro-sciences are bringing new understanding as to how the human brain processes information through distributed and
connected pathways. Barbara de Salvo, Deputy Director for Science and Long-Term Research for CEA-Leti, discusses how these new discoveries are driving new
models of semiconductor computing, which have the potential to enable step-change improvements in processing efficiency. She outlines a research strategy
encompassing algorithms, circuits, and components, that aims to develop brain-inspired technologies to meet the needs of 21st-century applications.
The automotive industry is undergoing a once-in-a-lifetime transformation, where technologies once seen to be in the realm of science fiction, such as electric
vehicles and autonomous cars, are rapidly becoming a reality. Yukihiro Kato, Executive Director of Denso explains how the semiconductor industry has a vital role
to play in solving many of the technical challenges (ranging from efficient energy conversion and smart sensing, to real-time communication and decision making)
that must be overcome to enable the reality of this future ‘mobility-enhanced society’.
Our modern society has been revolutionised by the development of powerful and ubiquitous computing devices. David Patterson of Google and UC Berkeley reviews
50 years of innovation in computer architectures, from mainframe computers in the 1960s to the dominant RISC architecture of recent times. With the end of
Moore’s Law slowing the pace of improvements due to scaling, Patterson describes how this slowdown is actually rejuvenating innovation in computer architectures,
as future performance improvements cannot come from scaling alone.
With this line-up of speakers, the Plenary Session covers a wide range of topics, ranging from semiconductor industry challenges and brain-inspired computing,
to future automotive transportation and the history and future of computer architectures. We hope that you will find the presentations of our distinguished speakers
informative and inspiring. Enjoy!
FORMAL OPENING OF THE CONFERENCE
1.1 Semiconductor Innovation: Is the party over or just getting started?
Vincent Roche, President & CEO, Analog Devices, Norwood, MA
The future pace of semiconductor innovation is by no means certain. A little more than a decade ago, Dennard scaling ground to a halt.
Symposia and media outlets have been speculating on what comes after Moore’s Law for years now. Beyond these technology challenges,
business challenges, as well, are putting pressure on traditional semiconductor innovation: semiconductor prices continue their steady
decline while small geometry wafer fab facilities now cost close to $10B to build.
8:30 AM
8:45 AM
In this environment, is there any room for continued innovation or is the future of the semiconductor industry defined by incrementalism,
commoditization, and financial engineering? If our future is the latter, how will we meet the demands of a world where businesses,
governments, and societies are digitizing at a blazing pace? The spread of pervasive ubiquitous sensing, rapid advances in artificial intelligence,
heterogeneous integration, and the continued impact of digitization on virtually every industry on earth will require more, not less,
semiconductor innovation.
The physicist and philosopher Thomas Kuhn might describe our situation as the crisis that catalyzes a new paradigm. So what is the next
paradigm for semiconductor innovation? What is our path forward as scientists, technologists, and an industry?
6
• 2018 IEEE International Solid-State Circuits Conference
978-1-5090-4940-0/18/$31.00 ©2018 IEEE
ISSCC 2018 / February 12, 2018 / 8:30 AM
1.2 Brain-Inspired Technologies: Towards Chips that Think
Barbara De Salvo, Deputy Director for Science and Long Term Research, CEA-Leti, Grenoble, France
9:20 AM
1
Since the late 50s, brain-inspired computing has been regarded as an interesting alternative to conventional computational paradigms.
Today, the omnipresence of “big data” and worldwide social interactions requires technologies capable of analyzing complex objects (such
as sounds, images, or videos), in real time, and interact with humans in a cognitive way. The demand for computational efficiency and
“intelligent” features has gone well beyond what can be achieved with traditional solutions. The advent of the Internet-of-Things has also
introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics
processing should be done at the edge and at the end-devices instead of in the cloud. Specialized low-power architectures, inspired by the
human brain, have thus recently become one of the most active research areas in the computing landscape, offering tremendous
opportunities for novel applications. To map the embedded systems requirements, new challenges in brain-inspired technologies should
be addressed, in particular automatic sensor fusion, system fault tolerance and data-privacy while achieving high recognition accuracy,
low power consumption, and reducing cost.
In this talk, we will illustrate a research strategy – one encompassing algorithms, circuits, and components – to develop brain-inspired
technologies and meet the needs of 21st-century applications. To explore the architecture of neural networks, an open software platform
has been created and several neural network circuits conceived and fabricated. The use of innovative components, such as emerging
resistive memories, advanced CMOS, and 3D technologies has been explored to allow for the implementation of cognitive tasks in neural
networks. Those novel components bring memory closer to the processing unit and offer extraordinary potential to implement “intelligent”
features, approaching the way knowledge is created and processed in the human brain. Several concrete examples will be given to illustrate
how brain-inspired technologies are developed using a holistic research approach, where process development and integration, circuit
design, system architecture, and learning algorithms are simultaneously optimized, opening the door to new disruptive applications.
ISSCC, SSCS, IEEE AWARD PRESENTATIONS
BREAK
9:55 AM
10:20 AM
10:45 AM
1.3 Future Mobile Society Enabled by Semiconductor Technology
Yukihiro Kato, Executive Director, DENSO, Aichi, Japan
The automotive industry is in the midst of a once-in-a-century greatest transformation. The transformation of the automobile is a
consequence of three technology trends: (1) electrification, (2) driving automation, and (3) vehicle interconnection. All three of these require
dramatic advancement within semiconductor technologies. In this talk, our vision of the future mobile society is presented, focusing
especially on automotive semiconductor electronics. To promote the electrification of the car, power semiconductors are a key technology.
The energy conversion efficiency of the motor has been increased by IGBTs, and next-generation SiC MOSFETs will further increase
efficiency. However, to put automated driving to practical use, both advanced sensors and intelligent SoCs are required. Improved
performance of sensors, such as cameras, LIDARs, and millimeter-wave radars, with increased range and resolution are required to precisely
monitor the total environment of the car. Path planning for automated driving involves recognizing the vehicle’s proximity to nearby objects
and the free space available. In this process, deep learning is an exceedingly useful method and highly sophisticated SoCs with GPUs are
essential for its implementation. Finally, from the viewpoint of a connected vehicle, cars will shift from lumps of metal into something like
a giant smartphone! Of course, in the connected vehicle, you can make a phone call, receive and/or transmit emails, do shopping, make
payments, and so on. As well, updated maps are constantly available. But, also, each vehicle must be constantly aware of the status and
intent of nearby vehicles. Clearly, to implement the intricacies of such an interconnected vehicle network, we need a myriad of
semiconductors including communication ICs.
1.4 50 Years of Computer Architecture:
From Mainframe CPUs to Neural-Network TPUs
11:15 AM
David Patterson, Google, Mountain View, CA, University of California, Berkeley, CA
This talk reviews a half-century of computer architecture: We start with the IBM System 360, which in 1964 introduced the concept of
“binary compatibility”. Next, came the idea of the “dominant microprocessor architecture”, for which the early candidate was the Intel 432
which was shortly replaced by the emergency introduction of the Intel 80x86 in 1978. However, for the next 20 years, the Reduced Instruction
Set Computers (RISC) became dominant. Then, the Very-Long-Instruction-Word (VLIW) HP/Intel Itanium architecture was heralded as
their replacement in 2001, but instead the role was usurped by AMD’s introduction of the 64 bit 80x86. Thus, while the 80x86 dominated
the PC-Era, RISCs have led thereafter, currently with 20B shipped annually (versus 0.4B 80x86s). Since the ending of Moore’s Law and
Dennard scaling has stalled performance of general-purpose microprocessors, domain-specific computer architectures are the only option
left. An early example of this trend introduced by Google in 2015 is the Tensor Processing Unit (TPU) for cloud-based deep neural
networking .
PRESENTATION TO PLENARY SPEAKERS
CONCLUSION
11:50 AM
11:55 AM
DIGEST OF TECHNICAL PAPERS •
7
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