F1C100s 数据手册Datasheet V1

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Declaration Declaration T HIS D O C U M E N TAT I O N IS T HE ORIGINAL WORK AND COPY RIGHT ED PROPE RTY OF AL L WINNE R TE CHNOL OGY (“AL L WINNER”). REP RODU CTION IN W HOLE OR IN P A RT MU ST OBTA IN THE W RIT TEN A P P ROVA L OF A LLW IN N ER A N D GIVE CLEA R ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER. THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION. THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE. F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 2

Revision History Revision V1.0 Revision History Date Nov.10,2015 Description Initial Release Version F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 3

Table of Contents Table of Contents 1. Overview ............................................................................................................................................................ 5 Features ............................................................................................................................................................. 6 2. 2.1. CPU Architecture.................................................................................................................................... 6 2.2. Memory Subsystem ............................................................................................................................... 6 System Peripheral .................................................................................................................................. 6 2.3. Display Subsystem.................................................................................................................................. 7 2.4. Video Engine .......................................................................................................................................... 7 2.5. 2.6. Image Subsystem ................................................................................................................................... 8 Audio Subsystem .................................................................................................................................... 8 2.7. System Peripherals ................................................................................................................................. 8 2.8. 2.9. Package ................................................................................................................................................ 10 3. Block Diagram .................................................................................................................................................. 11 4. Pin Description ................................................................................................................................................. 12 4.1. Pin Characteristics ................................................................................................................................ 12 4.2. GPIO Multiplexing Functions ............................................................................................................... 14 4.3. Detailed Pin Description ...................................................................................................................... 15 Electrical Characteristics .................................................................................................................................. 18 Absolute Maximum Ratings ................................................................................................................. 18 5.1. 5.2. Recommended Operating Conditions .................................................................................................. 18 5.3. DC Electrical Characteristics ................................................................................................................. 18 5.4. Oscillator Electrical Characteristics ...................................................................................................... 19 5.5. Power Up/Down Sequence .................................................................................................................. 19 6. Pin Assignment ................................................................................................................................................ 20 Pin Map ................................................................................................................................................ 20 Package Dimension .............................................................................................................................. 21 6.1. 6.2. 5. F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 4

Overview 1. Overview The F1C100s processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of video boombox markets. F1C100s processor is based on the ARM9 CPU architecture with a high degree of functional integration. F1C100s supports Full HD video playback, including H.264,H.263,MPEG1/2/4 decoder. Integrated audio codec and I2S/PCM interface provide end users with a good audio experience. TV-IN interface enables video input by connecting to video devices such as camera, and TV-OUT interface enables video output by connecting to TV devices. To reduce the BOM costs, F1C100s built-in DDR1 memory , and packed with general-purpose peripherals such as USB OTG, UART, SPI, TWI, TP, SD/MMC,CSI etc. F1C100s perfectly supports various applications of mainstream operating systems such as Andriod, Linux,etc. F1C100s outperforms competitors in terms of its powerful performance, low power consumption, and flexible scalability. Applications: ● Video Playback ● Audio Playback ● FM F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 5

Features 2. Features 2.1. CPU Architecture The F1C100s platform is based on ARM9 CPU architecture. ● Five-stage pipeline architecture ● Support 16KByte D-Cache ● Support 32KByte I-Cache 2.2. Memory Subsystem This section consists of internal memory and external memory: ● Boot ROM ● SDRAM ● SD/MMC Interface Boot ROM ● Internal memory ● On-Chip ROM boot loader ● Support system boot from SPI Nor/Nand Flash, and SD/TF card ● Support system code download through USB OTG SDRAM ● SIP DDR1 SD/MMC Interface ● External memory ● Support secure digital memory protocol commands (up to SD2.0) ● Support secure digital I/O protocol commands (up to SDIO2.0) ● Support multimedia card protocol commands (up to eMMC4.41) ● Support one SD (Verson1.0 to 2.0) or MMC (version 3.3 to eMMC4.41) ● Support hardware CRC generation and error detection ● Support host pull-up control ● Support SDIO interrupts in 1-bit and 4-bit modes ● Support SDIO suspend and resume operation ● Support SDIO read wait ● Support block size of 1 to 65535 bytes ● Support descriptor-based internal DMA controller ● Internal 128 bytes FIFO for data transfer ● Support 3.3V IO pad 2.3. System Peripheral This section includes: ● Timer ● INTC ● CCU ● DMA ● PWM Timer ● Three timers F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 6

Features ● Support watchdog reset ● Support audio and video synchronize counter INTC ● Support up to 64 interrupts ● Support 4-level priority ● Support interrupt mask ● Support interrupt fast forcing ● Support one external interrupt CCU ● Support 6 PLLs ● Control of clock generation, division, distribution and gating ● Control of device software reset DMA ● Support Normal DMA and Dedicated DMA ● Support two kinds of interrupt ● Support hardware continuous transfer mode PWM ● Support two PWM outputs ● Support cycle mode and pulse mode ● Support 24MHz maximum output frequency 2.4. Display Subsystem This section includes: ● Display Engine ● Display Output Display Engine ● Support four layers overlay, each layer size up to 2048x2048 pixels ● Support Alpha blending / color key ● Support multi-format input formats  1/2/4/8/16/32 bpp color  YUV444/YUV422/YUV420/YUV411 ● Support hardware cursor ● Support scaling function for one layer Input and output size up to 1280x720 pixels  ARGB8888/YUV444/YUV420/YUV422/YUV411   Resize ratio from 1/16X to 32X  4-tap 32-phase anti-aliasing filter in horizontal and vertical direction  Scaler supports write-back to memory function Display Output ● LCD RGB interface, TTL interface, up to 1280x720@60fps ● LCD Serial RGB interface, CCIR656 interface, up to 720x576@60fps ● LCD i8080 interface with 18/16/9/8 bit, up to 800x480@60fps ● LCD Dither function, support RGB666/RGB565 interface ● TV CVBS output, support NTSC/PAL, with auto plug detecting 2.5. Video Engine ● Support H.264 BP/MP/HP up to 1280x720@30fps decoding F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 7

● Support format MPEG1 and MPEG2 up to 1280x720@30fps decoding ● Support format MPEG4 SP/ASP GMC and H.263 including Sorenson Spark up to 1280x720@30fps decoding ● Support MJPEG encode up to 1280x720@30fps ● Support JPEG encode size up to 8192 x 8192 ● Support JPEG decode size up to 16384 x 16384 Features 2.6. Image Subsystem This section includes: ● CSI ● CVBS Input CSI ● Support 8-bit CMOS-sensor interface ● Support YUV camera up to 5Mega pixel ● Support CCIR656 protocol for NTSC and PAL CVBS Input ● Support NTSC/PAL ● Support 3D comb filter ● Support two TV CVBS channels:TVIN0,TVIN1 2.7. Audio Subsystem Audio Codec ● Two audio digital-to-analog(DAC) channels ● Stereo capless headphone drivers:  Up to 100dB DR  Supports DAC Sample Rates from 8KHz to 192KHz ● Support analog/ digital volume control ● Analog low-power loop from FM/ line-in /microphone to headphone outputs ● Three audio inputs:  One microphone input  Stereo FM left/right input  One Line-in input ● One audio analog-to-digital(ADC) channel  96dB SNR@A-weight  Supports ADC Sample Rates from 8KHz to 48KHz  Support Auto Gain Control(AGC) 2.8. System Peripherals This section includes: ● USB 2.0 OTG ● KEYADC ● TP ● Digital Audio Interface ● UART ● SPI ● TWI ● IR ● RSBTM F1C100s Datasheet(Revision 1.0) Copyright © 2015 Allwinner Technology Co., Ltd. All Rights Reserved Page 8

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