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armv8官方手册（英文）.pdf
ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
Contents
Preface
About this manual
Using this manual
Part A, Introduction and Architecture Overview
Part B, The AArch64 Application Level Architecture
Part C, The A64 Instruction Set
Part D, The AArch64 System Level Architecture
Part E, The AArch32 Application Level Architecture
Part F, The AArch32 Instruction Sets
Part G, The AArch32 System Level Architecture
Part H, External Debug
Part I, Memory-mapped Components of the ARMv8 Architecture
Part J, Appendixes
Conventions
Typographic conventions
Signals
Numbers
Pseudocode descriptions
Assembler syntax descriptions
Additional reading
ARM publications
Other publications
Feedback
Feedback on this manual
Part A: ARMv8 Architecture Introduction and Overview
A1: Introduction to the ARMv8 Architecture
A1.1 About the ARM architecture
A1.2 Architecture profiles
A1.2.1 Debug architecture versions
A1.3 ARMv8 architectural concepts
A1.3.1 Execution state
A1.3.2 The ARM instruction sets
A1.3.3 System registers
The ARM Generic Interrupt Controller CPU interface
A1.3.4 ARMv8 Debug
A1.4 Supported data types
A1.4.1 Vector formats
Vector formats in AArch64 state
Vector formats in AArch32 state
A1.4.2 Half-precision floating-point formats
A1.4.3 Single-precision floating-point format
A1.4.4 Double-precision floating-point format
A1.4.5 Fixed-point format
A1.4.6 Conversion between floating-point and fixed-point values
A1.4.7 Polynomial arithmetic over {0, 1}
Pseudocode details of polynomial multiplication
A1.5 Floating-point and Advanced SIMD support
A1.5.1 Instruction support
A1.5.2 Floating-point standards, and terminology
A1.5.3 ARM standard floating-point input and output values
A1.5.4 Flush-to-zero
A1.5.5 NaN handling and the Default NaN
A1.6 Cryptographic Extension
A1.7 The ARM memory model
Part B: The AArch64 Application Level Architecture
B1: The AArch64 Application Level Programmers’ Model
B1.1 About the Application level programmers’ model
B1.2 Registers in AArch64 Execution state
B1.2.1 Registers in AArch64 state
Pseudocode details of registers in AArch64 state
B1.2.2 Process state, PSTATE
B1.2.3 System registers
Performance Monitors support
B1.3 Software control features and EL0
B1.3.1 Exception handling
B1.3.2 Wait for Interrupt and Wait for Event
B1.3.3 The YIELD instruction
B1.3.4 Application level cache management
B1.3.5 Debug events
B2: The AArch64 Application Level Memory Model
B2.1 Address space
B2.2 Memory type overview
B2.3 Caches and memory hierarchy
B2.3.1 Introduction to caches
B2.3.2 Memory hierarchy
The cacheability and shareability memory attributes
B2.3.3 Application level cache instructions
B2.3.4 Implication of caches for the application programmer
Data coherency issues
Synchronization and coherency issues between data and instruction accesses
B2.3.5 Preloading caches
B2.4 Alignment support
B2.4.1 Instruction alignment
B2.4.2 Alignment of data accesses
B2.4.3 Unaligned data access restrictions
B2.5 Endian support
B2.5.1 General description of endianness in the ARM architecture
B2.5.2 Instruction endianness
B2.5.3 Data endianness
Instructions to reverse bytes in a general-purpose register or a SIMD and floating-point register
Endianness in SIMD operations
B2.6 Atomicity in the ARM architecture
B2.6.1 Single-copy atomicity
B2.6.2 Multi-copy atomicity
B2.6.3 Requirements for single-copy atomicity
B2.6.4 Requirements for multi-copy atomicity
B2.6.5 Concurrent modification and execution of instructions
B2.7 Memory ordering
B2.7.1 Observability and completion
Completion of side-effects of accesses to Device memory
B2.7.2 Ordering requirements
Address dependencies and order
B2.7.3 Memory barriers
Instruction Synchronization Barrier (ISB)
Data Memory Barrier (DMB)
Data Synchronization Barrier (DSB)
Shareability and access limitations on the data barrier operations
Load-Acquire, Store-Release
B2.8 Memory types and attributes
B2.8.1 Normal memory
Shareable Normal memory
Non-shareable Normal memory
Concurrent modification and execution of instructions
Multi-register loads and stores that access Normal memory
B2.8.2 Device memory
Gathering
Reordering
Early Write Acknowledgement
Multi-register loads and stores that access Device memory
B2.9 Mismatched memory attributes
B2.10 Synchronization and semaphores
B2.10.1 Exclusive access instructions and Non-shareable memory locations
Changes to the local monitor state resulting from speculative execution
B2.10.2 Exclusive access instructions and Shareable memory locations
Operation of the global monitor
B2.10.3 Marking and the size of the marked memory block
B2.10.4 Context switch support
B2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
B2.10.6 Use of WFE and SEV instructions by spin-locks
Part C: The AArch64 Instruction Set
C1: The A64 Instruction Set
C1.1 Introduction
C1.2 Structure of the A64 assembler language
C1.2.1 Common syntax terms
C1.2.2 Instruction Mnemonics
C1.2.3 Condition Code
C1.2.4 Register names
General-purpose register file and the stack pointer
SIMD and floating-point register file
SIMD and floating-point scalar register names
SIMD vector register names
SIMD vector element names
C1.3 Address generation
C1.3.1 Register indexed addressing
C1.3.2 PC-relative addressing
C1.3.3 Load/Store addressing modes
Address calculation
C1.4 Instruction aliases
C2: A64 Instruction Set Overview
C2.1 Branches, Exception generating, and System instructions
C2.1.1 Conditional branch
C2.1.2 Unconditional branch (immediate)
C2.1.3 Unconditional branch (register)
C2.1.4 Exception generation and return
Exception generating
Exception return
Debug state
C2.1.5 System register instructions
C2.1.6 System instructions
C2.1.7 Hint instructions
C2.1.8 Barriers and CLREX instructions
C2.2 Loads and stores
C2.2.1 Load/Store register
C2.2.2 Load/Store register (unscaled offset)
C2.2.3 Load/Store Pair
C2.2.4 Load/Store Non-temporal Pair
C2.2.5 Load/Store Unprivileged
C2.2.6 Load-Exclusive/Store-Exclusive
C2.2.7 Load-Acquire/Store-Release
C2.2.8 Load/Store scalar SIMD and floating-point
Load/Store scalar SIMD and floating-point register
Load/Store scalar SIMD and floating-point register (unscaled offset)
Load/Store SIMD and Floating-point register pair
Load/Store SIMD and Floating-point Non-temporal pair
C2.2.9 Load/Store Vector
Load/Store structures
Load single structure and replicate
C2.2.10 Prefetch memory
C2.3 Data processing - immediate
C2.3.1 Arithmetic (immediate)
C2.3.2 Logical (immediate)
C2.3.3 Move (wide immediate)
C2.3.4 Move (immediate)
C2.3.5 PC-relative address calculation
C2.3.6 Bitfield move
C2.3.7 Bitfield insert and extract
C2.3.8 Extract register
C2.3.9 Shift (immediate)
C2.3.10 Sign-extend and Zero-extend
C2.4 Data processing - register
C2.4.1 Arithmetic (shifted register)
C2.4.2 Arithmetic (extended register)
C2.4.3 Arithmetic with carry
C2.4.4 Logical (shifted register)
C2.4.5 Move (register)
C2.4.6 Shift (register)
C2.4.7 Multiply and divide
Multiply
Divide
C2.4.8 CRC32
C2.4.9 Bit operation
C2.4.10 Conditional select
C2.4.11 Conditional comparison
C2.5 Data processing - SIMD and floating-point
C2.5.1 Common features of SIMD instructions
C2.5.2 Floating-point move (register)
C2.5.3 Floating-point move (immediate)
C2.5.4 Floating-point conversion
Convert floating-point precision
Convert between floating-point and integer or fixed-point
C2.5.5 Floating-point round to integral
C2.5.6 Floating-point multiply-add
C2.5.7 Floating-point arithmetic (one source)
C2.5.8 Floating-point arithmetic (two sources)
C2.5.9 Floating-point minimum and maximum
C2.5.10 Floating-point comparison
C2.5.11 Floating-point conditional select
C2.5.12 SIMD move
C2.5.13 SIMD arithmetic
C2.5.14 SIMD compare
C2.5.15 SIMD widening and narrowing arithmetic
C2.5.16 SIMD unary arithmetic
C2.5.17 SIMD by element arithmetic
C2.5.18 SIMD permute
C2.5.19 SIMD immediate
C2.5.20 SIMD shift (immediate)
C2.5.21 SIMD floating-point and integer conversion
C2.5.22 SIMD reduce (across vector lanes)
C2.5.23 SIMD pairwise arithmetic
C2.5.24 SIMD table lookup
C2.5.25 Cryptography extensions
C3: A64 Instruction Set Encoding
C3.1 A64 instruction index by encoding
C3.2 Branches, exception generating and system instructions
C3.2.1 Compare & branch (immediate)
C3.2.2 Conditional branch (immediate)
C3.2.3 Exception generation
C3.2.4 System
C3.2.5 Test & branch (immediate)
C3.2.6 Unconditional branch (immediate)
C3.2.7 Unconditional branch (register)
C3.3 Loads and stores
C3.3.1 AdvSIMD load/store multiple structures
C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
C3.3.3 AdvSIMD load/store single structure
C3.3.4 AdvSIMD load/store single structure (post-indexed)
C3.3.5 Load register (literal)
C3.3.6 Load/store exclusive
C3.3.7 Load/store no-allocate pair (offset)
C3.3.8 Load/store register (immediate post-indexed)
C3.3.9 Load/store register (immediate pre-indexed)
C3.3.10 Load/store register (register offset)
C3.3.11 Load/store register (unprivileged)
C3.3.12 Load/store register (unscaled immediate)
C3.3.13 Load/store register (unsigned immediate)
C3.3.14 Load/store register pair (offset)
C3.3.15 Load/store register pair (post-indexed)
C3.3.16 Load/store register pair (pre-indexed)
C3.4 Data processing - immediate
C3.4.1 Add/subtract (immediate)
C3.4.2 Bitfield
C3.4.3 Extract
C3.4.4 Logical (immediate)
C3.4.5 Move wide (immediate)
C3.4.6 PC-rel. addressing
C3.5 Data processing - register
C3.5.1 Add/subtract (extended register)
C3.5.2 Add/subtract (shifted register)
C3.5.3 Add/subtract (with carry)
C3.5.4 Conditional compare (immediate)
C3.5.5 Conditional compare (register)
C3.5.6 Conditional select
C3.5.7 Data-processing (1 source)
C3.5.8 Data-processing (2 source)
C3.5.9 Data-processing (3 source)
C3.5.10 Logical (shifted register)
C3.6 Data processing - SIMD and floating point
C3.6.1 AdvSIMD EXT
C3.6.2 AdvSIMD TBL/TBX
C3.6.3 AdvSIMD ZIP/UZP/TRN
C3.6.4 AdvSIMD across lanes
C3.6.5 AdvSIMD copy
C3.6.6 AdvSIMD modified immediate
C3.6.7 AdvSIMD scalar copy
C3.6.8 AdvSIMD scalar pairwise
C3.6.9 AdvSIMD scalar shift by immediate
C3.6.10 AdvSIMD scalar three different
C3.6.11 AdvSIMD scalar three same
C3.6.12 AdvSIMD scalar two-reg misc
C3.6.13 AdvSIMD scalar x indexed element
C3.6.14 AdvSIMD shift by immediate
C3.6.15 AdvSIMD three different
C3.6.16 AdvSIMD three same
C3.6.17 AdvSIMD two-reg misc
C3.6.18 AdvSIMD vector x indexed element
C3.6.19 Crypto AES
C3.6.20 Crypto three-reg SHA
C3.6.21 Crypto two-reg SHA
C3.6.22 Floating-point compare
C3.6.23 Floating-point conditional compare
C3.6.24 Floating-point conditional select
C3.6.25 Floating-point data-processing (1 source)
C3.6.26 Floating-point data-processing (2 source)
C3.6.27 Floating-point data-processing (3 source)
C3.6.28 Floating-point immediate
C3.6.29 Floating-point<->fixed-point conversions
C3.6.30 Floating-point<->integer conversions
C4: The AArch64 System Instruction Class
C4.1 About the System instruction and System register descriptions
C4.1.1 Fixed values in instruction and register descriptions
C4.2 The System instruction class encoding space
C4.2.1 Principles of the System instruction class encoding
C4.2.2 System instruction class encoding overview
UNDEFINED behaviors
C4.2.3 Op0==0b00, architectural hints, barriers and CLREX, and PSTATE access
Architectural hint instructions
Barriers and CLREX
Instructions for accessing the PSTATE fields
C4.2.4 Op0==0b01, cache maintenance, TLB maintenance, and address translation instructions
Cache maintenance instructions, and data cache zero
Address translation instructions
TLB maintenance instructions
C4.2.5 Op0==0b10, Moves to and from debug, trace, and Execution environment System registers
Instructions for accessing debug System registers
Instructions for accessing AArch32 Execution environment registers
C4.2.6 Op0==0b11, Moves to and from non-debug System registers and special-purpose registers
Instructions for accessing non-debug System registers
Instructions for accessing special-purpose registers
C4.2.7 Reserved control space for IMPLEMENTATION DEFINED functionality
C4.3 PSTATE and special purpose registers
C4.3.1 CurrentEL, Current Exception Level
Accessing the CurrentEL:
C4.3.2 DAIF, Interrupt Mask Bits
Accessing the DAIF:
C4.3.3 DLR_EL0, Debug Link Register
C4.3.4 DSPSR_EL0, Debug Saved Program Status Register
C4.3.5 ELR_EL1, Exception Link Register (EL1)
Accessing the ELR_EL1:
C4.3.6 ELR_EL2, Exception Link Register (EL2)
Accessing the ELR_EL2:
C4.3.7 ELR_EL3, Exception Link Register (EL3)
Accessing the ELR_EL3:
C4.3.8 FPCR, Floating-point Control Register
Accessing the FPCR:
C4.3.9 FPSR, Floating-point Status Register
Accessing the FPSR:
C4.3.10 NZCV, Condition Flags
Accessing the NZCV:
C4.3.11 SP_EL0, Stack Pointer (EL0)
Accessing the SP_EL0:
C4.3.12 SP_EL1, Stack Pointer (EL1)
Accessing the SP_EL1:
C4.3.13 SP_EL2, Stack Pointer (EL2)
Accessing the SP_EL2:
C4.3.14 SP_EL3, Stack Pointer (EL3)
C4.3.15 SPSel, Stack Pointer Select
Accessing the SPSel:
C4.3.16 SPSR_abt, Saved Program Status Register (Abort mode)
Accessing the SPSR_abt:
C4.3.17 SPSR_EL1, Saved Program Status Register (EL1)
When exception taken from AArch32:
When exception taken from AArch64:
Accessing the SPSR_EL1:
C4.3.18 SPSR_EL2, Saved Program Status Register (EL2)
When exception taken from AArch32:
When exception taken from AArch64:
Accessing the SPSR_EL2:
C4.3.19 SPSR_EL3, Saved Program Status Register (EL3)
When exception taken from AArch32:
When exception taken from AArch64:
Accessing the SPSR_EL3:
C4.3.20 SPSR_fiq, Saved Program Status Register (FIQ mode)
Accessing the SPSR_fiq:
C4.3.21 SPSR_irq, Saved Program Status Register (IRQ mode)
Accessing the SPSR_irq:
C4.3.22 SPSR_und, Saved Program Status Register (Undefined mode)
Accessing the SPSR_und:
C4.4 A64 system instructions for cache maintenance
C4.4.1 DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way
Performing the DC CISW operation:
C4.4.2 DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC
Performing the DC CIVAC operation:
C4.4.3 DC CSW, Data or unified Cache line Clean by Set/Way
Performing the DC CSW operation:
C4.4.4 DC CVAC, Data or unified Cache line Clean by VA to PoC
Performing the DC CVAC operation:
C4.4.5 DC CVAU, Data or unified Cache line Clean by VA to PoU
Performing the DC CVAU operation:
C4.4.6 DC ISW, Data or unified Cache line Invalidate by Set/Way
Performing the DC ISW operation:
C4.4.7 DC IVAC, Data or unified Cache line Invalidate by VA to PoC
Performing the DC IVAC operation:
C4.4.8 DC ZVA, Data Cache Zero by VA
Performing the DC ZVA operation:
C4.4.9 IC IALLU, Instruction Cache Invalidate All to PoU
Performing the IC IALLU operation:
C4.4.10 IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
Performing the IC IALLUIS operation:
C4.4.11 IC IVAU, Instruction Cache line Invalidate by VA to PoU
Performing the IC IVAU operation:
C4.5 A64 system instructions for address translation
C4.5.1 AT S12E0R, Address Translate Stages 1 and 2 EL0 Read
Performing the AT S12E0R operation:
C4.5.2 AT S12E0W, Address Translate Stages 1 and 2 EL0 Write
Performing the AT S12E0W operation:
C4.5.3 AT S12E1R, Address Translate Stages 1 and 2 EL1 Read
Performing the AT S12E1R operation:
C4.5.4 AT S12E1W, Address Translate Stages 1 and 2 EL1 Write
Performing the AT S12E1W operation:
C4.5.5 AT S1E0R, Address Translate Stage 1 EL0 Read
Performing the AT S1E0R operation:
C4.5.6 AT S1E0W, Address Translate Stage 1 EL0 Write
Performing the AT S1E0W operation:
C4.5.7 AT S1E1R, Address Translate Stage 1 EL1 Read
Performing the AT S1E1R operation:
C4.5.8 AT S1E1W, Address Translate Stage 1 EL1 Write
Performing the AT S1E1W operation:
C4.5.9 AT S1E2R, Address Translate Stage 1 EL2 Read
Performing the AT S1E2R operation:
C4.5.10 AT S1E2W, Address Translate Stage 1 EL2 Write
Performing the AT S1E2W operation:
C4.5.11 AT S1E3R, Address Translate Stage 1 EL3 Read
Performing the AT S1E3R operation:
C4.5.12 AT S1E3W, Address Translate Stage 1 EL3 Write
Performing the AT S1E3W operation:
C4.6 A64 system instructions for TLB maintenance
C4.6.1 TLBI ALLE1, TLB Invalidate All entries, EL1
Performing the TLBI ALLE1 operation:
C4.6.2 TLBI ALLE1IS, TLB Invalidate All entries, EL1, Inner Shareable
Performing the TLBI ALLE1IS operation:
C4.6.3 TLBI ALLE2, TLB Invalidate All entries, EL2
Performing the TLBI ALLE2 operation:
C4.6.4 TLBI ALLE2IS, TLB Invalidate All entries, EL2, Inner Shareable
Performing the TLBI ALLE2IS operation:
C4.6.5 TLBI ALLE3, TLB Invalidate All entries, EL3
Performing the TLBI ALLE3 operation:
C4.6.6 TLBI ALLE3IS, TLB Invalidate All entries, EL3, Inner Shareable
Performing the TLBI ALLE3IS operation:
C4.6.7 TLBI ASIDE1, TLB Invalidate by ASID, EL1
Performing the TLBI ASIDE1 operation:
C4.6.8 TLBI ASIDE1IS, TLB Invalidate by ASID, EL1, Inner Shareable
Performing the TLBI ASIDE1IS operation:
C4.6.9 TLBI IPAS2E1, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
Performing the TLBI IPAS2E1 operation:
C4.6.10 TLBI IPAS2E1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
Performing the TLBI IPAS2E1IS operation:
C4.6.11 TLBI IPAS2LE1, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
Performing the TLBI IPAS2LE1 operation:
C4.6.12 TLBI IPAS2LE1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
Performing the TLBI IPAS2LE1IS operation:
C4.6.13 TLBI VAAE1, TLB Invalidate by VA, All ASID, EL1
Performing the TLBI VAAE1 operation:
C4.6.14 TLBI VAAE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
Performing the TLBI VAAE1IS operation:
C4.6.15 TLBI VAALE1, TLB Invalidate by VA, All ASID, Last level, EL1
Performing the TLBI VAALE1 operation:
C4.6.16 TLBI VAALE1IS, TLB Invalidate by VA, All ASID, EL1, Inner Shareable
Performing the TLBI VAALE1IS operation:
C4.6.17 TLBI VAE1, TLB Invalidate by VA, EL1
Performing the TLBI VAE1 operation:
C4.6.18 TLBI VAE1IS, TLB Invalidate by VA, EL1, Inner Shareable
Performing the TLBI VAE1IS operation:
C4.6.19 TLBI VAE2, TLB Invalidate by VA, EL2
Performing the TLBI VAE2 operation:
C4.6.20 TLBI VAE2IS, TLB Invalidate by VA, EL2, Inner Shareable
Performing the TLBI VAE2IS operation:
C4.6.21 TLBI VAE3, TLB Invalidate by VA, EL3
Performing the TLBI VAE3 operation:
C4.6.22 TLBI VAE3IS, TLB Invalidate by VA, EL3, Inner Shareable
Performing the TLBI VAE3IS operation:
C4.6.23 TLBI VALE1, TLB Invalidate by VA, Last level, EL1
Performing the TLBI VALE1 operation:
C4.6.24 TLBI VALE1IS, TLB Invalidate by VA, Last level, EL1, Inner Shareable
Performing the TLBI VALE1IS operation:
C4.6.25 TLBI VALE2, TLB Invalidate by VA, Last level, EL2
Performing the TLBI VALE2 operation:
C4.6.26 TLBI VALE2IS, TLB Invalidate by VA, Last level, EL2, Inner Shareable
Performing the TLBI VALE2IS operation:
C4.6.27 TLBI VALE3, TLB Invalidate by VA, Last level, EL3
Performing the TLBI VALE3 operation:
C4.6.28 TLBI VALE3IS, TLB Invalidate by VA, Last level, EL3, Inner Shareable
Performing the TLBI VALE3IS operation:
C4.6.29 TLBI VMALLE1, TLB Invalidate by VMID, All entries at stage 1, EL1
Performing the TLBI VMALLE1 operation:
C4.6.30 TLBI VMALLE1IS, TLB Invalidate by VMID, All entries at stage 1, EL1, Inner Shareable
Performing the TLBI VMALLE1IS operation:
C4.6.31 TLBI VMALLS12E1, TLB Invalidate by VMID, All entries at Stage 1 and 2, EL1
Performing the TLBI VMALLS12E1 operation:
C4.6.32 TLBI VMALLS12E1IS, TLB Invalidate by VMID, All entries at Stage 1 and 2, EL1, Inner Shareable
Performing the TLBI VMALLS12E1IS operation:
C5: A64 Base Instruction Descriptions
C5.1 Introduction
C5.2 Register size
C5.3 Use of the PC
C5.4 Use of the stack pointer
C5.5 Condition flags and related instructions
C5.6 Alphabetical list of instructions
C5.6.1 ADC
Assembler Symbols
Operation
C5.6.2 ADCS
Assembler Symbols
Operation
C5.6.3 ADD (extended register)
Assembler Symbols
Operation
C5.6.4 ADD (immediate)
Alias conditions
Assembler Symbols
Operation
C5.6.5 ADD (shifted register)
Assembler Symbols
Operation
C5.6.6 ADDS (extended register)
Alias conditions
Assembler Symbols
Operation
C5.6.7 ADDS (immediate)
Alias conditions
Assembler Symbols
Operation
C5.6.8 ADDS (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.9 ADR
Assembler Symbols
Operation
C5.6.10 ADRP
Assembler Symbols
Operation
C5.6.11 AND (immediate)
Assembler Symbols
Operation
C5.6.12 AND (shifted register)
Assembler Symbols
Operation
C5.6.13 ANDS (immediate)
Alias conditions
Assembler Symbols
Operation
C5.6.14 ANDS (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.15 ASR (register)
Assembler Symbols
C5.6.16 ASR (immediate)
Assembler Symbols
C5.6.17 ASRV
Assembler Symbols
Operation
C5.6.18 AT
Assembler Symbols
C5.6.19 B.cond
Assembler Symbols
Operation
C5.6.20 B
Assembler Symbols
Operation
C5.6.21 BFI
Assembler Symbols
C5.6.22 BFM
Alias conditions
Assembler Symbols
Operation
C5.6.23 BFXIL
Assembler Symbols
C5.6.24 BIC (shifted register)
Assembler Symbols
Operation
C5.6.25 BICS (shifted register)
Assembler Symbols
Operation
C5.6.26 BL
Assembler Symbols
Operation
C5.6.27 BLR
Assembler Symbols
Operation
C5.6.28 BR
Assembler Symbols
Operation
C5.6.29 BRK
Assembler Symbols
Operation
C5.6.30 CBNZ
Assembler Symbols
Operation
C5.6.31 CBZ
Assembler Symbols
Operation
C5.6.32 CCMN (immediate)
Assembler Symbols
Operation
C5.6.33 CCMN (register)
Assembler Symbols
Operation
C5.6.34 CCMP (immediate)
Assembler Symbols
Operation
C5.6.35 CCMP (register)
Assembler Symbols
Operation
C5.6.36 CINC
Assembler Symbols
C5.6.37 CINV
Assembler Symbols
C5.6.38 CLREX
Assembler Symbols
Operation
C5.6.39 CLS
Assembler Symbols
Operation
C5.6.40 CLZ
Assembler Symbols
Operation
C5.6.41 CMN (extended register)
Assembler Symbols
C5.6.42 CMN (immediate)
Assembler Symbols
C5.6.43 CMN (shifted register)
Assembler Symbols
C5.6.44 CMP (extended register)
Assembler Symbols
C5.6.45 CMP (immediate)
Assembler Symbols
C5.6.46 CMP (shifted register)
Assembler Symbols
C5.6.47 CNEG
Assembler Symbols
C5.6.48 CRC32B, CRC32H, CRC32W, CRC32X
Assembler Symbols
Operation
C5.6.49 CRC32CB, CRC32CH, CRC32CW, CRC32CX
Assembler Symbols
Operation
C5.6.50 CSEL
Assembler Symbols
Operation
C5.6.51 CSET
Assembler Symbols
C5.6.52 CSETM
Assembler Symbols
C5.6.53 CSINC
Alias conditions
Assembler Symbols
Operation
C5.6.54 CSINV
Alias conditions
Assembler Symbols
Operation
C5.6.55 CSNEG
Alias conditions
Assembler Symbols
Operation
C5.6.56 DC
Assembler Symbols
C5.6.57 DCPS1
Assembler Symbols
Operation
C5.6.58 DCPS2
Assembler Symbols
Operation
C5.6.59 DCPS3
Assembler Symbols
Operation
C5.6.60 DMB
Assembler Symbols
Operation
C5.6.61 DRPS
Operation
C5.6.62 DSB
Assembler Symbols
Operation
C5.6.63 EON (shifted register)
Assembler Symbols
Operation
C5.6.64 EOR (immediate)
Assembler Symbols
Operation
C5.6.65 EOR (shifted register)
Assembler Symbols
Operation
C5.6.66 ERET
Operation
C5.6.67 EXTR
Alias conditions
Assembler Symbols
Operation
C5.6.68 HINT
Alias conditions
Assembler Symbols
Operation
C5.6.69 HLT
Assembler Symbols
Operation
C5.6.70 HVC
Assembler Symbols
Operation
C5.6.71 IC
Assembler Symbols
C5.6.72 ISB
Assembler Symbols
Operation
C5.6.73 LDAR
Assembler Symbols
Operation
C5.6.74 LDARB
Assembler Symbols
Operation
C5.6.75 LDARH
Assembler Symbols
Operation
C5.6.76 LDAXP
Assembler Symbols
Operation
C5.6.77 LDAXR
Assembler Symbols
Operation
C5.6.78 LDAXRB
Assembler Symbols
Operation
C5.6.79 LDAXRH
Assembler Symbols
Operation
C5.6.80 LDNP
Assembler Symbols
Shared decode for all variants
Operation
C5.6.81 LDP
Post-index
Pre-index
Signed offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.82 LDPSW
Post-index
Pre-index
Signed offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.83 LDR (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.84 LDR (literal)
Assembler Symbols
Operation
C5.6.85 LDR (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.86 LDRB (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.87 LDRB (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.88 LDRH (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.89 LDRH (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.90 LDRSB (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.91 LDRSB (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.92 LDRSH (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.93 LDRSH (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.94 LDRSW (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.95 LDRSW (literal)
Assembler Symbols
Operation
C5.6.96 LDRSW (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.97 LDTR
Assembler Symbols
Shared decode for all variants
Operation
C5.6.98 LDTRB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.99 LDTRH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.100 LDTRSB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.101 LDTRSH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.102 LDTRSW
Assembler Symbols
Shared decode for all variants
Operation
C5.6.103 LDUR
Assembler Symbols
Shared decode for all variants
Operation
C5.6.104 LDURB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.105 LDURH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.106 LDURSB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.107 LDURSH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.108 LDURSW
Assembler Symbols
Shared decode for all variants
Operation
C5.6.109 LDXP
Assembler Symbols
Operation
C5.6.110 LDXR
Assembler Symbols
Operation
C5.6.111 LDXRB
Assembler Symbols
Operation
C5.6.112 LDXRH
Assembler Symbols
Operation
C5.6.113 LSL (register)
Assembler Symbols
C5.6.114 LSL (immediate)
Assembler Symbols
C5.6.115 LSLV
Assembler Symbols
Operation
C5.6.116 LSR (register)
Assembler Symbols
C5.6.117 LSR (immediate)
Assembler Symbols
C5.6.118 LSRV
Assembler Symbols
Operation
C5.6.119 MADD
Alias conditions
Assembler Symbols
Operation
C5.6.120 MNEG
Assembler Symbols
C5.6.121 MOV (to/from SP)
Assembler Symbols
C5.6.122 MOV (inverted wide immediate)
Assembler Symbols
C5.6.123 MOV (wide immediate)
Assembler Symbols
C5.6.124 MOV (bitmask immediate)
Assembler Symbols
C5.6.125 MOV (register)
Assembler Symbols
C5.6.126 MOVK
Assembler Symbols
Operation
C5.6.127 MOVN
Alias conditions
Assembler Symbols
Operation
C5.6.128 MOVZ
Alias conditions
Assembler Symbols
Operation
C5.6.129 MRS
Assembler Symbols
Operation
C5.6.130 MSR (immediate)
Assembler Symbols
Operation
C5.6.131 MSR (register)
Assembler Symbols
Operation
C5.6.132 MSUB
Alias conditions
Assembler Symbols
Operation
C5.6.133 MUL
Assembler Symbols
C5.6.134 MVN
Assembler Symbols
C5.6.135 NEG
Assembler Symbols
C5.6.136 NEGS
Assembler Symbols
C5.6.137 NGC
Assembler Symbols
C5.6.138 NGCS
Assembler Symbols
C5.6.139 NOP
C5.6.140 ORN (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.141 ORR (immediate)
Alias conditions
Assembler Symbols
Operation
C5.6.142 ORR (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.143 PRFM (immediate)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.144 PRFM (literal)
Assembler Symbols
Operation
C5.6.145 PRFM (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.146 PRFUM
Assembler Symbols
Shared decode for all variants
Operation
C5.6.147 RBIT
Assembler Symbols
Operation
C5.6.148 RET
Assembler Symbols
Operation
C5.6.149 REV
Assembler Symbols
Operation
C5.6.150 REV16
Assembler Symbols
Operation
C5.6.151 REV32
Assembler Symbols
Operation
C5.6.152 ROR (immediate)
Assembler Symbols
C5.6.153 ROR (register)
Assembler Symbols
C5.6.154 RORV
Assembler Symbols
Operation
C5.6.155 SBC
Alias conditions
Assembler Symbols
Operation
C5.6.156 SBCS
Alias conditions
Assembler Symbols
Operation
C5.6.157 SBFIZ
Assembler Symbols
C5.6.158 SBFM
Alias conditions
Assembler Symbols
Operation
C5.6.159 SBFX
Assembler Symbols
C5.6.160 SDIV
Assembler Symbols
Operation
C5.6.161 SEV
C5.6.162 SEVL
C5.6.163 SMADDL
Alias conditions
Assembler Symbols
Operation
C5.6.164 SMC
Assembler Symbols
Operation
C5.6.165 SMNEGL
Assembler Symbols
C5.6.166 SMSUBL
Alias conditions
Assembler Symbols
Operation
C5.6.167 SMULH
Assembler Symbols
Operation
C5.6.168 SMULL
Assembler Symbols
C5.6.169 STLR
Assembler Symbols
Operation
C5.6.170 STLRB
Assembler Symbols
Operation
C5.6.171 STLRH
Assembler Symbols
Operation
C5.6.172 STLXP
Assembler Symbols
Operation
C5.6.173 STLXR
Assembler Symbols
Operation
C5.6.174 STLXRB
Assembler Symbols
Operation
C5.6.175 STLXRH
Assembler Symbols
Operation
C5.6.176 STNP
Assembler Symbols
Shared decode for all variants
Operation
C5.6.177 STP
Post-index
Pre-index
Signed offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.178 STR (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.179 STR (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.180 STRB (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.181 STRB (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.182 STRH (immediate)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C5.6.183 STRH (register)
Assembler Symbols
Shared decode for all variants
Operation
C5.6.184 STTR
Assembler Symbols
Shared decode for all variants
Operation
C5.6.185 STTRB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.186 STTRH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.187 STUR
Assembler Symbols
Shared decode for all variants
Operation
C5.6.188 STURB
Assembler Symbols
Shared decode for all variants
Operation
C5.6.189 STURH
Assembler Symbols
Shared decode for all variants
Operation
C5.6.190 STXP
Assembler Symbols
Operation
C5.6.191 STXR
Assembler Symbols
Operation
C5.6.192 STXRB
Assembler Symbols
Operation
C5.6.193 STXRH
Assembler Symbols
Operation
C5.6.194 SUB (extended register)
Assembler Symbols
Operation
C5.6.195 SUB (immediate)
Assembler Symbols
Operation
C5.6.196 SUB (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.197 SUBS (extended register)
Alias conditions
Assembler Symbols
Operation
C5.6.198 SUBS (immediate)
Alias conditions
Assembler Symbols
Operation
C5.6.199 SUBS (shifted register)
Alias conditions
Assembler Symbols
Operation
C5.6.200 SVC
Assembler Symbols
Operation
C5.6.201 SXTB
Assembler Symbols
C5.6.202 SXTH
Assembler Symbols
C5.6.203 SXTW
Assembler Symbols
C5.6.204 SYS
Alias conditions
Assembler Symbols
Operation
C5.6.205 SYSL
Assembler Symbols
Operation
C5.6.206 TBNZ
Assembler Symbols
Operation
C5.6.207 TBZ
Assembler Symbols
Operation
C5.6.208 TLBI
Assembler Symbols
C5.6.209 TST (immediate)
Assembler Symbols
C5.6.210 TST (shifted register)
Assembler Symbols
C5.6.211 UBFIZ
Assembler Symbols
C5.6.212 UBFM
Alias conditions
Assembler Symbols
Operation
C5.6.213 UBFX
Assembler Symbols
C5.6.214 UDIV
Assembler Symbols
Operation
C5.6.215 UMADDL
Alias conditions
Assembler Symbols
Operation
C5.6.216 UMNEGL
Assembler Symbols
C5.6.217 UMSUBL
Alias conditions
Assembler Symbols
Operation
C5.6.218 UMULH
Assembler Symbols
Operation
C5.6.219 UMULL
Assembler Symbols
C5.6.220 UXTB
Assembler Symbols
C5.6.221 UXTH
Assembler Symbols
C5.6.222 WFE
C5.6.223 WFI
C5.6.224 YIELD
C6: A64 SIMD and Floating-point Instruction Descriptions
C6.1 Introduction
C6.2 About the SIMD and floating-point instructions
C6.2.1 Register size
C6.2.2 Data types
C6.2.3 Condition flags and related instructions
C6.2.4 General capabilities
C6.3 Alphabetical list of floating-point and Advanced SIMD instructions
C6.3.1 ABS
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.2 ADD (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.3 ADDHN, ADDHN2
Assembler Symbols
Operation
C6.3.4 ADDP (scalar)
Assembler Symbols
Operation
C6.3.5 ADDP (vector)
Assembler Symbols
Operation
C6.3.6 ADDV
Assembler Symbols
Operation
C6.3.7 AESD
Assembler Symbols
Operation
C6.3.8 AESE
Assembler Symbols
Operation
C6.3.9 AESIMC
Assembler Symbols
Operation
C6.3.10 AESMC
Assembler Symbols
Operation
C6.3.11 AND (vector)
Assembler Symbols
Operation
C6.3.12 BIC (vector, immediate)
Assembler Symbols
Operation
C6.3.13 BIC (vector, register)
Assembler Symbols
Operation
C6.3.14 BIF
Assembler Symbols
Operation
C6.3.15 BIT
Assembler Symbols
Operation
C6.3.16 BSL
Assembler Symbols
Operation
C6.3.17 CLS (vector)
Assembler Symbols
Operation
C6.3.18 CLZ (vector)
Assembler Symbols
Operation
C6.3.19 CMEQ (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.20 CMEQ (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.21 CMGE (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.22 CMGE (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.23 CMGT (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.24 CMGT (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.25 CMHI (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.26 CMHS (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.27 CMLE (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.28 CMLT (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.29 CMTST
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.30 CNT
Assembler Symbols
Operation
C6.3.31 DUP (element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.32 DUP (general)
Assembler Symbols
Operation
C6.3.33 EOR (vector)
Assembler Symbols
Operation
C6.3.34 EXT
Assembler Symbols
Operation
C6.3.35 FABD
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.36 FABS (vector)
Assembler Symbols
Operation
C6.3.37 FABS (scalar)
Assembler Symbols
Operation
C6.3.38 FACGE
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.39 FACGT
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.40 FADD (vector)
Assembler Symbols
Operation
C6.3.41 FADD (scalar)
Assembler Symbols
Operation
C6.3.42 FADDP (scalar)
Assembler Symbols
Operation
C6.3.43 FADDP (vector)
Assembler Symbols
Operation
C6.3.44 FCCMP
Assembler Symbols
Operation
C6.3.45 FCCMPE
Assembler Symbols
Operation
C6.3.46 FCMEQ (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.47 FCMEQ (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.48 FCMGE (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.49 FCMGE (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.50 FCMGT (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.51 FCMGT (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.52 FCMLE (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.53 FCMLT (zero)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.54 FCMP
Assembler Symbols
Operation
C6.3.55 FCMPE
Assembler Symbols
Operation
C6.3.56 FCSEL
Assembler Symbols
Operation
C6.3.57 FCVT
Assembler Symbols
Operation
C6.3.58 FCVTAS (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.59 FCVTAS (scalar)
Assembler Symbols
Operation
C6.3.60 FCVTAU (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.61 FCVTAU (scalar)
Assembler Symbols
Operation
C6.3.62 FCVTL, FCVTL2
Assembler Symbols
Operation
C6.3.63 FCVTMS (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.64 FCVTMS (scalar)
Assembler Symbols
Operation
C6.3.65 FCVTMU (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.66 FCVTMU (scalar)
Assembler Symbols
Operation
C6.3.67 FCVTN, FCVTN2
Assembler Symbols
Operation
C6.3.68 FCVTNS (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.69 FCVTNS (scalar)
Assembler Symbols
Operation
C6.3.70 FCVTNU (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.71 FCVTNU (scalar)
Assembler Symbols
Operation
C6.3.72 FCVTPS (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.73 FCVTPS (scalar)
Assembler Symbols
Operation
C6.3.74 FCVTPU (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.75 FCVTPU (scalar)
Assembler Symbols
Operation
C6.3.76 FCVTXN, FCVTXN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.77 FCVTZS (vector, fixed-point)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.78 FCVTZS (vector, integer)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.79 FCVTZS (scalar, fixed-point)
Assembler Symbols
Operation
C6.3.80 FCVTZS (scalar, integer)
Assembler Symbols
Operation
C6.3.81 FCVTZU (vector, fixed-point)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.82 FCVTZU (vector, integer)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.83 FCVTZU (scalar, fixed-point)
Assembler Symbols
Operation
C6.3.84 FCVTZU (scalar, integer)
Assembler Symbols
Operation
C6.3.85 FDIV (vector)
Assembler Symbols
Operation
C6.3.86 FDIV (scalar)
Assembler Symbols
Operation
C6.3.87 FMADD
Assembler Symbols
Operation
C6.3.88 FMAX (vector)
Assembler Symbols
Operation
C6.3.89 FMAX (scalar)
Assembler Symbols
Operation
C6.3.90 FMAXNM (vector)
Assembler Symbols
Operation
C6.3.91 FMAXNM (scalar)
Assembler Symbols
Operation
C6.3.92 FMAXNMP (scalar)
Assembler Symbols
Operation
C6.3.93 FMAXNMP (vector)
Assembler Symbols
Operation
C6.3.94 FMAXNMV
Assembler Symbols
Operation
C6.3.95 FMAXP (scalar)
Assembler Symbols
Operation
C6.3.96 FMAXP (vector)
Assembler Symbols
Operation
C6.3.97 FMAXV
Assembler Symbols
Operation
C6.3.98 FMIN (vector)
Assembler Symbols
Operation
C6.3.99 FMIN (scalar)
Assembler Symbols
Operation
C6.3.100 FMINNM (vector)
Assembler Symbols
Operation
C6.3.101 FMINNM (scalar)
Assembler Symbols
Operation
C6.3.102 FMINNMP (scalar)
Assembler Symbols
Operation
C6.3.103 FMINNMP (vector)
Assembler Symbols
Operation
C6.3.104 FMINNMV
Assembler Symbols
Operation
C6.3.105 FMINP (scalar)
Assembler Symbols
Operation
C6.3.106 FMINP (vector)
Assembler Symbols
Operation
C6.3.107 FMINV
Assembler Symbols
Operation
C6.3.108 FMLA (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.109 FMLA (vector)
Assembler Symbols
Operation
C6.3.110 FMLS (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.111 FMLS (vector)
Assembler Symbols
Operation
C6.3.112 FMOV (vector, immediate)
Assembler Symbols
Operation
C6.3.113 FMOV (register)
Assembler Symbols
Operation
C6.3.114 FMOV (general)
Assembler Symbols
Operation
C6.3.115 FMOV (scalar, immediate)
Assembler Symbols
Operation
C6.3.116 FMSUB
Assembler Symbols
Operation
C6.3.117 FMUL (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.118 FMUL (vector)
Assembler Symbols
Operation
C6.3.119 FMUL (scalar)
Assembler Symbols
Operation
C6.3.120 FMULX (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.121 FMULX
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.122 FNEG (vector)
Assembler Symbols
Operation
C6.3.123 FNEG (scalar)
Assembler Symbols
Operation
C6.3.124 FNMADD
Assembler Symbols
Operation
C6.3.125 FNMSUB
Assembler Symbols
Operation
C6.3.126 FNMUL
Assembler Symbols
Operation
C6.3.127 FRECPE
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.128 FRECPS
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.129 FRECPX
Assembler Symbols
Operation
C6.3.130 FRINTA (vector)
Assembler Symbols
Operation
C6.3.131 FRINTA (scalar)
Assembler Symbols
Operation
C6.3.132 FRINTI (vector)
Assembler Symbols
Operation
C6.3.133 FRINTI (scalar)
Assembler Symbols
Operation
C6.3.134 FRINTM (vector)
Assembler Symbols
Operation
C6.3.135 FRINTM (scalar)
Assembler Symbols
Operation
C6.3.136 FRINTN (vector)
Assembler Symbols
Operation
C6.3.137 FRINTN (scalar)
Assembler Symbols
Operation
C6.3.138 FRINTP (vector)
Assembler Symbols
Operation
C6.3.139 FRINTP (scalar)
Assembler Symbols
Operation
C6.3.140 FRINTX (vector)
Assembler Symbols
Operation
C6.3.141 FRINTX (scalar)
Assembler Symbols
Operation
C6.3.142 FRINTZ (vector)
Assembler Symbols
Operation
C6.3.143 FRINTZ (scalar)
Assembler Symbols
Operation
C6.3.144 FRSQRTE
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.145 FRSQRTS
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.146 FSQRT (vector)
Assembler Symbols
Operation
C6.3.147 FSQRT (scalar)
Assembler Symbols
Operation
C6.3.148 FSUB (vector)
Assembler Symbols
Operation
C6.3.149 FSUB (scalar)
Assembler Symbols
Operation
C6.3.150 INS (element)
Assembler Symbols
Operation
C6.3.151 INS (general)
Assembler Symbols
Operation
C6.3.152 LD1 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.153 LD1 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.154 LD1R
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.155 LD2 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.156 LD2 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.157 LD2R
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.158 LD3 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.159 LD3 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.160 LD3R
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.161 LD4 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.162 LD4 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.163 LD4R
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.164 LDNP (SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.165 LDP (SIMD&FP)
Post-index
Pre-index
Signed offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.166 LDR (immediate, SIMD&FP)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.167 LDR (literal, SIMD&FP)
Assembler Symbols
Operation
C6.3.168 LDR (register, SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.169 LDUR (SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.170 MLA (by element)
Assembler Symbols
Operation
C6.3.171 MLA (vector)
Assembler Symbols
Operation
C6.3.172 MLS (by element)
Assembler Symbols
Operation
C6.3.173 MLS (vector)
Assembler Symbols
Operation
C6.3.174 MOV (scalar)
Assembler Symbols
C6.3.175 MOV (element)
Assembler Symbols
C6.3.176 MOV (from general)
Assembler Symbols
C6.3.177 MOV (vector)
Assembler Symbols
C6.3.178 MOV (to general)
Assembler Symbols
C6.3.179 MOVI
Assembler Symbols
Operation
C6.3.180 MUL (by element)
Assembler Symbols
Operation
C6.3.181 MUL (vector)
Assembler Symbols
Operation
C6.3.182 MVN
Assembler Symbols
C6.3.183 MVNI
Assembler Symbols
Operation
C6.3.184 NEG (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.185 NOT
Assembler Symbols
Operation
C6.3.186 ORN (vector)
Assembler Symbols
Operation
C6.3.187 ORR (vector, immediate)
Assembler Symbols
Operation
C6.3.188 ORR (vector, register)
Alias conditions
Assembler Symbols
Operation
C6.3.189 PMUL
Assembler Symbols
Operation
C6.3.190 PMULL, PMULL2
Assembler Symbols
Operation
C6.3.191 RADDHN, RADDHN2
Assembler Symbols
Operation
C6.3.192 RBIT (vector)
Assembler Symbols
Operation
C6.3.193 REV16 (vector)
Assembler Symbols
Operation
C6.3.194 REV32 (vector)
Assembler Symbols
Operation
C6.3.195 REV64
Assembler Symbols
Operation
C6.3.196 RSHRN, RSHRN2
Assembler Symbols
Operation
C6.3.197 RSUBHN, RSUBHN2
Assembler Symbols
Operation
C6.3.198 SABA
Assembler Symbols
Operation
C6.3.199 SABAL, SABAL2
Assembler Symbols
Operation
C6.3.200 SABD
Assembler Symbols
Operation
C6.3.201 SABDL, SABDL2
Assembler Symbols
Operation
C6.3.202 SADALP
Assembler Symbols
Operation
C6.3.203 SADDL, SADDL2
Assembler Symbols
Operation
C6.3.204 SADDLP
Assembler Symbols
Operation
C6.3.205 SADDLV
Assembler Symbols
Operation
C6.3.206 SADDW, SADDW2
Assembler Symbols
Operation
C6.3.207 SCVTF (vector, fixed-point)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.208 SCVTF (vector, integer)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.209 SCVTF (scalar, fixed-point)
Assembler Symbols
Operation
C6.3.210 SCVTF (scalar, integer)
Assembler Symbols
Operation
C6.3.211 SHA1C
Assembler Symbols
Operation
C6.3.212 SHA1H
Assembler Symbols
Operation
C6.3.213 SHA1M
Assembler Symbols
Operation
C6.3.214 SHA1P
Assembler Symbols
Operation
C6.3.215 SHA1SU0
Assembler Symbols
Operation
C6.3.216 SHA1SU1
Assembler Symbols
Operation
C6.3.217 SHA256H2
Assembler Symbols
Operation
C6.3.218 SHA256H
Assembler Symbols
Operation
C6.3.219 SHA256SU0
Assembler Symbols
Operation
C6.3.220 SHA256SU1
Assembler Symbols
Operation
C6.3.221 SHADD
Assembler Symbols
Operation
C6.3.222 SHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.223 SHLL, SHLL2
Assembler Symbols
Operation
C6.3.224 SHRN, SHRN2
Assembler Symbols
Operation
C6.3.225 SHSUB
Assembler Symbols
Operation
C6.3.226 SLI
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.227 SMAX
Assembler Symbols
Operation
C6.3.228 SMAXP
Assembler Symbols
Operation
C6.3.229 SMAXV
Assembler Symbols
Operation
C6.3.230 SMIN
Assembler Symbols
Operation
C6.3.231 SMINP
Assembler Symbols
Operation
C6.3.232 SMINV
Assembler Symbols
Operation
C6.3.233 SMLAL, SMLAL2 (by element)
Assembler Symbols
Operation
C6.3.234 SMLAL, SMLAL2 (vector)
Assembler Symbols
Operation
C6.3.235 SMLSL, SMLSL2 (by element)
Assembler Symbols
Operation
C6.3.236 SMLSL, SMLSL2 (vector)
Assembler Symbols
Operation
C6.3.237 SMOV
Assembler Symbols
Operation
C6.3.238 SMULL, SMULL2 (by element)
Assembler Symbols
Operation
C6.3.239 SMULL, SMULL2 (vector)
Assembler Symbols
Operation
C6.3.240 SQABS
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.241 SQADD
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.242 SQDMLAL, SQDMLAL2 (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.243 SQDMLAL, SQDMLAL2 (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.244 SQDMLSL, SQDMLSL2 (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.245 SQDMLSL, SQDMLSL2 (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.246 SQDMULH (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.247 SQDMULH (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.248 SQDMULL, SQDMULL2 (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.249 SQDMULL, SQDMULL2 (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.250 SQNEG
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.251 SQRDMULH (by element)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.252 SQRDMULH (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.253 SQRSHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.254 SQRSHRN, SQRSHRN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.255 SQRSHRUN, SQRSHRUN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.256 SQSHL (immediate)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.257 SQSHL (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.258 SQSHLU
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.259 SQSHRN, SQSHRN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.260 SQSHRUN, SQSHRUN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.261 SQSUB
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.262 SQXTN, SQXTN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.263 SQXTUN, SQXTUN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.264 SRHADD
Assembler Symbols
Operation
C6.3.265 SRI
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.266 SRSHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.267 SRSHR
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.268 SRSRA
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.269 SSHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.270 SSHLL, SSHLL2
Alias conditions
Assembler Symbols
Operation
C6.3.271 SSHR
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.272 SSRA
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.273 SSUBL, SSUBL2
Assembler Symbols
Operation
C6.3.274 SSUBW, SSUBW2
Assembler Symbols
Operation
C6.3.275 ST1 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.276 ST1 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.277 ST2 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.278 ST2 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.279 ST3 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.280 ST3 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.281 ST4 (multiple structures)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.282 ST4 (single structure)
No offset
Post-index
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.283 STNP (SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.284 STP (SIMD&FP)
Post-index
Pre-index
Signed offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.285 STR (immediate, SIMD&FP)
Post-index
Pre-index
Unsigned offset
Assembler Symbols
Shared decode for all variants
Operation for all classes
C6.3.286 STR (register, SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.287 STUR (SIMD&FP)
Assembler Symbols
Shared decode for all variants
Operation
C6.3.288 SUB (vector)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.289 SUBHN, SUBHN2
Assembler Symbols
Operation
C6.3.290 SUQADD
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.291 SXTL
Assembler Symbols
C6.3.292 TBL
Assembler Symbols
Operation
C6.3.293 TBX
Assembler Symbols
Operation
C6.3.294 TRN1
Assembler Symbols
Operation
C6.3.295 TRN2
Assembler Symbols
Operation
C6.3.296 UABA
Assembler Symbols
Operation
C6.3.297 UABAL, UABAL2
Assembler Symbols
Operation
C6.3.298 UABD
Assembler Symbols
Operation
C6.3.299 UABDL, UABDL2
Assembler Symbols
Operation
C6.3.300 UADALP
Assembler Symbols
Operation
C6.3.301 UADDL, UADDL2
Assembler Symbols
Operation
C6.3.302 UADDLP
Assembler Symbols
Operation
C6.3.303 UADDLV
Assembler Symbols
Operation
C6.3.304 UADDW, UADDW2
Assembler Symbols
Operation
C6.3.305 UCVTF (vector, fixed-point)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.306 UCVTF (vector, integer)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.307 UCVTF (scalar, fixed-point)
Assembler Symbols
Operation
C6.3.308 UCVTF (scalar, integer)
Assembler Symbols
Operation
C6.3.309 UHADD
Assembler Symbols
Operation
C6.3.310 UHSUB
Assembler Symbols
Operation
C6.3.311 UMAX
Assembler Symbols
Operation
C6.3.312 UMAXP
Assembler Symbols
Operation
C6.3.313 UMAXV
Assembler Symbols
Operation
C6.3.314 UMIN
Assembler Symbols
Operation
C6.3.315 UMINP
Assembler Symbols
Operation
C6.3.316 UMINV
Assembler Symbols
Operation
C6.3.317 UMLAL, UMLAL2 (by element)
Assembler Symbols
Operation
C6.3.318 UMLAL, UMLAL2 (vector)
Assembler Symbols
Operation
C6.3.319 UMLSL, UMLSL2 (by element)
Assembler Symbols
Operation
C6.3.320 UMLSL, UMLSL2 (vector)
Assembler Symbols
Operation
C6.3.321 UMOV
Assembler Symbols
Operation
C6.3.322 UMULL, UMULL2 (by element)
Assembler Symbols
Operation
C6.3.323 UMULL, UMULL2 (vector)
Assembler Symbols
Operation
C6.3.324 UQADD
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.325 UQRSHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.326 UQRSHRN, UQRSHRN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.327 UQSHL (immediate)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.328 UQSHL (register)
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.329 UQSHRN
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.330 UQSUB
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.331 UQXTN, UQXTN2
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.332 URECPE
Assembler Symbols
Operation
C6.3.333 URHADD
Assembler Symbols
Operation
C6.3.334 URSHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.335 URSHR
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.336 URSQRTE
Assembler Symbols
Operation
C6.3.337 URSRA
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.338 USHL
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.339 USHLL, USHLL2
Alias conditions
Assembler Symbols
Operation
C6.3.340 USHR
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.341 USQADD
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.342 USRA
Scalar
Vector
Assembler Symbols
Operation for all classes
C6.3.343 USUBL, USUBL2
Assembler Symbols
Operation
C6.3.344 USUBW, USUBW2
Assembler Symbols
Operation
C6.3.345 UXTL
Assembler Symbols
C6.3.346 UZP1
Assembler Symbols
Operation
C6.3.347 UZP2
Assembler Symbols
Operation
C6.3.348 XTN, XTN2
Assembler Symbols
Operation
C6.3.349 ZIP1
Assembler Symbols
Operation
C6.3.350 ZIP2
Assembler Symbols
Operation
Part D: The AArch64 System Level Architecture
D1: The AArch64 System Level Programmers’ Model
D1.1 Exception levels
D1.1.1 Typical Exception level usage model
D1.2 Exception terminology
D1.2.1 Terminology for taking an exception
D1.2.2 Terminology for returning from an exception
D1.2.3 Exception levels
D1.2.4 Definition of a precise exception
D1.2.5 Definitions of synchronous and asynchronous exceptions
D1.3 Execution state
D1.4 Security state
D1.4.1 The ARMv8-A security model
Security model when EL3 is using AArch64
D1.5 Virtualization
D1.5.1 The effect of implementing EL2 on the Exception model
Virtual interrupts
D1.6 Registers for instruction processing and exception handling
D1.6.1 The general purpose registers, R0-R30
D1.6.2 The stack pointer registers
Stack pointer register selection
D1.6.3 The SIMD and floating-point registers, V0-V31
D1.6.4 Saved Program Status Registers (SPSRs)
SPSR format for exceptions taken to AArch64 state
D1.6.5 Exception Link Registers (ELRs)
D1.7 Process state, PSTATE
D1.8 Program counter and stack pointer alignment
D1.8.1 PC alignment checking
D1.8.2 Stack pointer alignment checking
D1.9 Reset
D1.9.1 PE state on reset to AArch64 state
D1.9.2 Code sequence to request a Warm reset as a result of RMR_ELx.RR
D1.10 Exception entry
D1.10.1 Preferred exception return address
D1.10.2 Exception vectors
D1.10.3 Pseudocode description of exception entry to AArch64 state
D1.10.4 Exception classes
EC encodings when routing general exceptions to EL2
Exceptions taken for an unknown reason, EC encoding 0x00
D1.11 Exception return
D1.11.1 Pseudocode description of exception return
D1.11.2 Exception return and PC alignment
D1.11.3 Illegal return events
D1.12 The Exception level hierarchy
D1.12.1 The hierarchy of configuration and routing control
Controls provided at EL3
Controls provided at EL2
Controls provided at EL1
D1.12.2 Control of SIMD, floating-point and trace functionality
D1.12.3 Control of IMPLEMENTATION DEFINED features
D1.13 Synchronous exception types, routing and priorities
D1.13.1 Routing general exceptions to EL2
D1.13.2 Synchronous exception prioritization
D1.13.3 Effect of Data Aborts
D1.13.4 Floating-point Exception traps
D1.14 Asynchronous exception types, routing, masking and priorities
D1.14.1 Asynchronous exception routing
D1.14.2 Asynchronous exception masking
D1.14.3 Virtual interrupts
D1.14.4 Prioritization and recognition of asynchronous exceptions
D1.14.5 Taking an interrupt during a multiple-register load or store
D1.15 Trapping functionality to higher Exception levels
D1.15.1 Trapping to EL1 using AArch64
Traps to EL1 of EL0 accesses to cache maintenance operations
Traps to EL1 of EL0 execution of WFE and WFI instructions
Traps to EL1 of EL0 execution of DC ZVA instructions
Traps to EL1 of EL0 accesses to the PSTATE.{D, A, I, F} interrupt masks
Traps to EL1 of EL0 accesses to AArch32 deprecated functionality
Traps to EL1 of EL1 and EL0 System register accesses to the trace registers
Traps to EL1 of EL1 and EL0 accesses to SIMD and floating-point functionality
Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers
Traps to EL1 of EL0 accesses to Performance Monitors registers
D1.15.2 Trapping to EL2 using AArch64
Traps to EL2 of System register access instructions
Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers
Disabling Non-secure state execution of HVC instructions
Traps to EL2 of Non-secure EL1 and EL0 execution of DC ZVA instructions
Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions
Traps to EL2 of Non-secure EL1 and EL0 execution of cache maintenance instructions
Traps to EL2 of Non-secure EL1 and EL0 accesses to the Auxiliary Control Register
Traps to EL2 of Non-secure EL1 and EL0 accesses to lockdown, DMA, and TCM operations
Traps to EL2 of Non-secure EL1 execution of SMC instructions
Traps to EL2 of Non-secure EL1 and EL0 reads of ID registers
Traps to EL2 of Non-secure EL1 and EL0 execution of WFE and WFI instructions
Traps to EL2 of Non-secure EL1 accesses to SIMD and floating-point functionality
Traps to EL2 of EL2, and Non-secure EL1 and EL0, System register accesses to the trace registers
Traps to EL2 of Non-secure EL1 and EL0 accesses to the T32EE configuration registers, from AArch32 state only
Generic trapping to EL2 of Non-secure EL1 and EL0 accesses to System registers, from AArch32 state only
Traps to EL2 of Non-secure EL1 and EL0 System register accesses to debug registers
Traps to EL2 of Non-secure EL1 and EL0 accesses to Performance Monitors registers
D1.15.3 Trapping to EL3 using AArch64
Traps to EL3 of System register access instructions
Traps to EL3 of monitor functionality from Secure EL1 using AArch32
Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions
Traps to EL3 of Secure EL1 accesses to the Counter-timer Physical Secure timer registers
Enabling EL3, EL2, and EL1 execution of HVC instructions
Disabling EL3, EL2, and EL1 execution of SMC instructions
Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL1 and EL0 accesses to the CPACR_EL1 or CPACR
Traps to EL3 of all System register accesses to the trace registers
Traps to EL3 of all accesses to the SIMD and floating-point registers
Traps to EL3 of EL2, EL1, and EL0 System register accesses to debug registers
Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers
D1.16 System calls
D1.17 Use of the ESR_EL1, ESR_EL2, and ESR_EL3
D1.17.1 Encoding of ISS[24:20] when used for a condition code and valid bit
D1.17.2 Exceptions with an unknown reason
D1.17.3 Exception from a WFI or WFE instruction, from AArch32 or AArch64 state
D1.17.4 Exception from an MCR or MRC access from AArch32 state
D1.17.5 Exception from an MCRR or MRRC access from AArch32 state
D1.17.6 Exception from an LDC or STC access to CP14 from AArch32 state
D1.17.7 Exception from an access to SIMD or floating-point registers, from AArch32 or AArch64
D1.17.8 Exception from an illegal Execution state, misaligned PC, or misaligned stack pointer
D1.17.9 Exception from HVC or SVC instruction execution
D1.17.10 Exception from SMC instruction execution in AArch32 state
D1.17.11 Exception from SMC instruction execution in AArch64 state
D1.17.12 Exception from MSR, MRS, or System instruction execution in AArch64 state
D1.17.13 Exception from an Instruction abort
D1.17.14 Exception from a Data abort
D1.17.15 Floating-point exceptions
D1.17.16 SError interrupt
D1.17.17 Breakpoint exception or Vector Catch exception
D1.17.18 Watchpoint exception
D1.17.19 Software Step exception
D1.17.20 Software Breakpoint Instruction exception
D1.18 Mechanisms for entering a low-power state
D1.18.1 Wait for Event mechanism and Send event
The Event Register
The Wait For Event instruction
WFE wake-up events in AArch64 state
The Send Event instructions
Pseudocode details of the Wait For Event mechanism
D1.18.2 Wait For Interrupt
WFI wake-up events
Using WFI to indicate an idle state on bus interfaces
Pseudocode details of Wait For Interrupt
D1.19 Self-hosted debug
D1.19.1 Debug exceptions
D1.19.2 The PSTATE debug mask bit, D
D1.20 Performance Monitors extension
D1.21 Interprocessing
D1.21.1 Register mappings between AArch32 state and AArch64 state
Mapping of the general-purpose registers between the Execution states
Mapping of the SIMD and floating-point registers between the Execution states
Mapping of the System registers between the Execution states
D1.21.2 State of the general-purpose registers on taking an exception to AArch64 state
D1.21.3 SPSR, ELR, and AArch64 SP relationships on changing Execution state
D1.22 Supported configurations
D1.22.1 Implication of Exception levels implemented
D1.22.2 Support for Exception levels and Execution states
D1.22.3 Implementations not including Advanced SIMD and floating-point instructions
D1.22.4 The effects of supporting fewer than four Exception levels
Behavior when EL2 is not implemented
Behavior when EL3 is not implemented
Behavior when only EL1 and EL0 are implemented
D2: Debug Exceptions
D2.1 Introduction to debug exceptions
D2.2 Legacy debug exceptions
D2.3 Understanding the descriptions for AArch64 state and AArch32 state
D2.4 Software Breakpoint Instruction exceptions
D2.4.1 About Software Breakpoint Instruction exceptions
D2.4.2 Breakpoint instructions in the ARMv8-A architecture
About whether breakpoint instructions are conditional
D2.4.3 Exception syndrome information provided by the PE
D2.4.4 Breakpoint instructions as the first instruction in an IT block
D2.4.5 Pseudocode description of Software Breakpoint Instruction exceptions
D2.5 Breakpoint exceptions
D2.5.1 About Breakpoint exceptions
D2.5.2 Enable controls for Breakpoint exceptions
D2.5.3 Conditions for generating a Breakpoint exception
D2.5.4 About Breakpoint Control Registers
General properties of a breakpoint, defined by its control register
Execution conditions that a breakpoint generates Breakpoint exceptions for
D2.5.5 Breakpoint types and linking of breakpoints
Breakpoint types defined by DBGBCRn_EL1.BT or DBGBCRn.BT
D2.5.6 Instruction address comparisons for Breakpoint exception generation
Address Match breakpoints
Address Mismatch breakpoints in an AArch32 stage 1 translation regime
D2.5.7 Specifying the halfword-aligned address that an address comparison is successful on
Using the BAS field in Address Match breakpoints
Using the BAS field in Address Mismatch breakpoints, in an AArch32 stage 1 translation regime
D2.5.8 Context comparisons for Breakpoint exception generation
D2.5.9 Linked comparisons for Breakpoint exception generation
A linked comparison for an address match and a context match
A linked comparison for an address mismatch and a context match, in an AArch32 stage 1 translation regime
D2.5.10 Using breakpoints
Using an Address Mismatch breakpoint to single-step an instruction
Address breakpoints on the first instruction in an IT block
Constraints on programming hardware breakpoints
D2.5.11 Summary of breakpoint matching for different breakpoint types
Using the tables
Condition definitions
D2.5.12 Pseudocode descriptions of Breakpoint exceptions taken from AArch64 state
D2.5.13 Pseudocode descriptions of Breakpoint exceptions taken from AArch32 state
D2.6 Watchpoint exceptions
D2.6.1 About Watchpoint exceptions
D2.6.2 Enable controls for Watchpoint exceptions
D2.6.3 Conditions for generating a Watchpoint exception
D2.6.4 About Watchpoint Control Registers
General properties of a watchpoint, defined by its control register
Execution conditions a watchpoint generates Watchpoint exceptions for
D2.6.5 Linking of watchpoints
D2.6.6 Data address comparisons for Watchpoint exception generation
D2.6.7 Taking into account the size of the data access
D2.6.8 Programming a watchpoint with eight bytes or fewer
D2.6.9 Programming a watchpoint with eight or more bytes
D2.6.10 Programming dependencies of the BAS and MASK fields
D2.6.11 Linked comparisons for Watchpoint exception generation
D2.6.12 Determining the memory location that caused a Watchpoint debug event
Address recorded for Watchpoint debug events generated by instructions other than Data Cache instructions
Address recorded for Watchpoint debug events generated by Data Cache instructions
D2.6.13 Using watchpoints
Watchpoint behavior on accesses caused by prefetch instructions
Watchpoint behavior on accesses caused by Store-Exclusive instructions
Watchpoint behavior on accesses caused by cache maintenance instructions
Constraints on programming watchpoints
D2.6.14 Summary of watchpoint matching
Using the table
Condition definitions
D2.6.15 Pseudocode description of Watchpoint exceptions taken from AArch64 state
D2.6.16 Pseudocode description of Watchpoint exceptions taken from AArch32 state
D2.7 Vector Catch exceptions
D2.7.1 About Vector Catch exceptions
D2.7.2 Enable controls for Vector Catch exceptions
D2.7.3 Exception vectors that Vector Catch exceptions can be enabled for
D2.7.4 Generation of Vector Catch exceptions
Address-matching
Exception-trapping
D2.7.5 Constraints to consider when programming vector catch
Conditions that apply to both forms of vector catch
Conditions that apply only to the address-matching form
D2.7.6 Pseudocode description of Vector Catch exceptions
D2.8 Software Step exceptions
D2.8.1 About Software Step exceptions
D2.8.2 Enable controls for software step
D2.8.3 The software step state machine
D2.8.4 Rules for enabling software step
D2.8.5 Entering the active-not-pending state
D2.8.6 Behavior in the active-not-pending state
If an exception is taken to an Exception level that is using AArch64
If the exception is taken to an Exception level that is using AArch32
Summary of behavior in the active-not-pending state
D2.8.7 Entering the active-pending state
D2.8.8 Behavior in the active-pending state
D2.8.9 Stepping T32 IT instructions
D2.8.10 Syndrome information that the PE provides
D2.8.11 Additional considerations
Behavior when an ERET instruction is an illegal exception return
Behavior when the instruction stepped writes a misaligned PC value
Stepping code that uses exclusive monitors
Synchronization and the software step state machine
D2.8.12 Pseudocode description of Software Step exceptions
D2.9 Synchronization and debug exceptions
D2.9.1 State and mode changes without explicit context synchronization operations
D3: The Debug Exception Model
D3.1 About debug exceptions
D3.2 The debug exceptions enable controls
D3.3 Routing debug exceptions
D3.3.1 Pseudocode description of routing debug exceptions
D3.4 Enabling debug exceptions from current Exception level and Security state
D3.4.1 Enabling debug exceptions from the current Exception level
If the current Exception level is ELD using AArch64
If the current Exception level is ELD is using AArch32
D3.4.2 Enabling debug exceptions from the current Security state
The secure debug disable bit
The Secure Privileged Debug and Secure User Invasive Debug Enable fields
D3.4.3 Pseudocode descriptions of enabling debug exceptions
From AArch64 state
From AArch32 state
D3.5 The effect of powerdown on debug exceptions
D3.6 Summary of permitted routing and enabling of debug exceptions
D3.6.1 If ELD is using AArch64
D3.6.2 If ELD is using AArch32
D3.7 Debug exception behavior
D3.7.1 The effect of taking debug exceptions to AArch64 on system registers
D3.7.2 Preferred return addresses
D3.8 Pseudocode descriptions of debug exceptions
D4: The AArch64 System Level Memory Model
D4.1 About the memory system architecture
D4.1.1 Form of the memory system architecture
D4.1.2 Memory attributes
D4.2 Address space
D4.2.1 Address space overflow or underflow
Instruction address space overflow
D4.3 Mixed-endian support
D4.4 Cache support
D4.4.1 General behavior of the caches
D4.4.2 Cache identification
D4.4.3 Cacheability, cache allocation hints, and cache transient hints
D4.4.4 Behavior of caches at reset
D4.4.5 Cache enabling and disabling
D4.4.6 Non-cacheable accesses and instruction caches
D4.4.7 Cache maintenance operations
Terms used in describing the maintenance instructions
The ARMv8 abstraction of the cache hierarchy
D4.4.8 Cache maintenance instructions
Instruction cache maintenance instructions (IC*)
Data cache maintenance instructions (DC*)
General requirements for the scope of maintenance instructions
Effects of instructions that operate to the point of coherency
Effects of instructions that do not operate to the point of coherency
Effects of virtualization and security on the cache maintenance instructions
Boundary conditions for cache maintenance instructions
Ordering and completion of data and instruction cache instructions
Performing cache maintenance instructions
D4.4.9 Data cache zero instruction
D4.4.10 Cache lockdown
The interaction of cache lockdown with cache maintenance instructions
D4.4.11 System level caches
D4.4.12 Branch prediction
D4.5 External aborts
D4.5.1 External abort on an instruction fetch
D4.5.2 External abort on data read or write
D4.5.3 Provision for the classification of external aborts
D4.5.4 Parity error reporting
D4.6 Memory barrier instructions
D4.6.1 EL2 control of the shareability of data barrier instructions executed at Non-secure EL0 or EL1
D4.7 Pseudocode details of general memory system instructions
D4.7.1 Memory data type definitions
D4.7.2 Basic memory access
D4.7.3 Aligned memory access
D4.7.4 Unaligned memory access
D4.7.5 Exclusive monitors operations
D4.7.6 Access permission checking
D4.7.7 Abort exceptions
D4.7.8 Memory barriers
D5: The AArch64 Virtual Memory System Architecture
D5.1 About the Virtual Memory System Architecture (VMSA)
D5.1.1 Address tagging in AArch64 state
D5.2 The VMSAv8-64 address translation system
D5.2.1 About the VMSAv8-64 address translation system
ARMv8 VMSA naming
VMSA address types and address spaces
About address translation
The VMSAv8-64 translation table format
D5.2.2 Controlling address translation stages
System control registers relevant to MMU operation
Address size configuration
D5.2.3 Memory translation granule size
How the granule size affects the address translation process
Effect of granule size on translation table addressing and indexing
D5.2.4 Translation tables and the translation process
Translation table walks
Security state of translation table lookups
Control of translation table walks
D5.2.5 Overview of the VMSAv8-64 address translation stages
Overview of VMSAv8-64 address translation using the 4KB translation granule
Overview of VMSAv8-64 address translation using the 16KB translation granule
Overview of VMSAv8-64 address translation using the 64KB translation granule
D5.2.6 The VMSAv8-64 translation table format
Translation granule size and associate block and page sizes
Selection between TTBR0 and TTBR1
Concatenated translation tables for the initial stage 2 lookup
Possible translation table registers programming errors
D5.2.7 The algorithm for finding the translation table entries
Finding the translation table entry when using the 4KB translation granule
Finding the translation table entry when using the 16KB translation granule
Finding the translation table descriptor when using the 64KB translation granule
D5.2.8 The effects of disabling a stage of address translation
Behavior when stage 1 address translation is disabled
Behavior when stage 2 address translation is disabled
Behavior of instruction fetches when all associated stages of translation are disabled
D5.2.9 The implemented Exception levels and the resulting translation stages and regimes
D5.2.10 Pseudocode details of VMSAv8-64 address translation
Definitions required for address translation
Performing the full address translation
Stage 1 translation
Stage 2 translation
Translation table walk
Support functions
D5.2.11 Address translation operations
Address translation instructions, AT*
D5.3 Translation table walk examples
D5.3.1 Examples of performing the initial lookup
Performing the initial lookup using the 4KB translation granule
Performing the initial lookup using the 16KB granule
Performing the initial lookup using the 64KB translation granule
D5.3.2 Full translation flows for VMSAv8-64 address translation
The address and properties fields shown in the translation flows
Full translation flow using the 4KB granule and starting at the zero level
Full translation flow using the 4KB granule and starting at the first level
Full translation flow using the 64KB granule and starting at the first level
Full translation flow using the 64KB granule and starting at the second level
D5.4 VMSAv8-64 translation table format descriptors
D5.4.1 VMSAv8-64 translation table zero-level, first-level, and second-level descriptor formats
Descriptor encodings, ARMv8 zero-level, first-level, and second-level formats
D5.4.2 ARMv8 translation table third-level descriptor formats
D5.4.3 Memory attribute fields in the VMSAv8-64 translation table format descriptors
Next-level attributes in stage 1 VMSAv8-64 Table descriptors
Attribute fields in stage 1 VMSAv8-64 Block and Page descriptors
Attribute fields in stage 2 VMSAv8-64 Block and Page descriptors
D5.4.4 Control of Secure or Non-secure memory access
Hierarchical control of Secure or Non-secure memory accesses
D5.5 Access controls and memory region attributes
D5.5.1 Memory access control
About the access permissions
The data access permission controls
Access permissions for instruction execution
The Access flag
D5.5.2 Memory region attributes
The memory region attributes for stage 1 translations
The memory region attributes for stage 2 translations, EL1&0 translation regime
Other fields in the VMSAv8-64 translation table format descriptors
D5.5.3 Combining the stage 1 and stage 2 attributes, Non-secure EL1&0 translation regime
Combining the stage 1 and stage 2 data access permissions
Combining the stage 1 and stage 2 instruction execution permissions
Combining the stage 1 and stage 2 memory type attributes
Combining the stage 1 and stage 2 cacheability attributes for Normal memory
Combining the stage 1 and stage 2 shareability attributes for Normal memory
D5.6 MMU faults
D5.6.1 Types of MMU faults
Permission fault
Translation fault
Address size fault
External abort on a translation table walk
Access flag fault
D5.6.2 The MMU fault-checking sequence
Stage 2 fault on a stage 1 translation table walk
D5.6.3 Prioritization of synchronous aborts from a single stage of address translation
D5.6.4 Pseudocode details of the MMU faults
D5.7 Translation Lookaside Buffers (TLBs)
D5.7.1 About ARMv8 Translation Lookaside Buffers (TLBs)
Global and process-specific translation table entries
TLB matching
TLB behavior at reset
TLB lockdown
TLB conflict aborts
D5.7.2 TLB maintenance requirements and the TLB maintenance instructions
General TLB maintenance requirements
TLB maintenance instructions
Maintenance requirements on changing System register values
Atomicity of register changes on changing virtual machine
D5.8 Caches in a VMSA implementation
D5.8.1 Data and unified caches
D5.8.2 Instruction caches
PIPT instruction caches
VIPT instruction caches
ASID and VMID tagged VIVT instruction caches
The IVIPT Extension
D5.8.3 Cache maintenance requirement created by changing translation table attributes
D6: The Performance Monitors Extension
D6.1 About the Performance Monitors
D6.1.1 Interaction with trace
D6.1.2 Interaction with power saving operations
D6.2 Accuracy of the Performance Monitors
D6.2.1 Non-invasive behavior
D6.2.2 A reasonable degree of inaccuracy
D6.3 Behavior on overflow
D6.3.1 Generating overflow interrupt requests
D6.3.2 Pseudocode details overflow interrupt requests
D6.4 Attributability
D6.5 Effect of EL3 and EL2
D6.5.1 Interaction with EL3
D6.5.2 Interaction with EL2
D6.6 Event filtering
D6.6.1 Filtering by Exception level and state
D6.6.2 Accuracy of event filtering
Exception-related events
Software increment events
Pseudocode details of event filtering
D6.7 Performance Monitors and Debug state
D6.8 Counter enables
D6.9 Counter access
D6.9.1 Access at EL0
D6.9.2 PMNx event counters
D6.9.3 CCNT cycle counter
D6.10 Event numbers and mnemonics
D6.10.1 Definition of terms
D6.10.2 Common event numbers
D6.10.3 Common architectural event numbers
D6.10.4 Common microarchitectural event numbers
D6.10.5 Required events
D6.10.6 IMPLEMENTATION DEFINED event numbers
D6.11 Performance Monitors Extension registers
D6.11.1 Relationship between AArch32 and AArch64 Performance Monitors registers
D6.11.2 Access permissions
D6.12 Pseudocode details
D7: The Generic Timer
D7.1 About the Generic Timer
D7.1.1 System counter
Initializing and reading the system counter frequency
Memory-mapped controls of the system counter
D7.1.2 The physical counter
Accessing the physical counter
D7.1.3 The virtual counter
Accessing the virtual counter
D7.1.4 Event streams
D7.1.5 Timers
Accessing the timer registers
Operation of the CompareValue views of the timers
Operation of the TimerValue views of the timers
D7.2 About the Generic Timer registers
D7.2.1 Status of the CNTVOFF register
D8: AArch64 System Register Descriptions
D8.1 About the AArch64 System registers
D8.1.1 Fixed values in the System register descriptions
D8.1.2 General behavior of accesses to the System registers
Synchronization requirements for system registers
D8.2 General system control registers
D8.2.1 ACTLR_EL1, Auxiliary Control Register (EL1)
Accessing the ACTLR_EL1:
D8.2.2 ACTLR_EL2, Auxiliary Control Register (EL2)
Accessing the ACTLR_EL2:
D8.2.3 ACTLR_EL3, Auxiliary Control Register (EL3)
Accessing the ACTLR_EL3:
D8.2.4 AFSR0_EL1, Auxiliary Fault Status Register 0 (EL1)
Accessing the AFSR0_EL1:
D8.2.5 AFSR0_EL2, Auxiliary Fault Status Register 0 (EL2)
Accessing the AFSR0_EL2:
D8.2.6 AFSR0_EL3, Auxiliary Fault Status Register 0 (EL3)
Accessing the AFSR0_EL3:
D8.2.7 AFSR1_EL1, Auxiliary Fault Status Register 1 (EL1)
Accessing the AFSR1_EL1:
D8.2.8 AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)
Accessing the AFSR1_EL2:
D8.2.9 AFSR1_EL3, Auxiliary Fault Status Register 1 (EL3)
Accessing the AFSR1_EL3:
D8.2.10 AIDR_EL1, Auxiliary ID Register
Accessing the AIDR_EL1:
D8.2.11 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register (EL1)
Accessing the AMAIR_EL1:
D8.2.12 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)
Accessing the AMAIR_EL2:
D8.2.13 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register (EL3)
Accessing the AMAIR_EL3:
D8.2.14 CCSIDR_EL1, Current Cache Size ID Register
Accessing the CCSIDR_EL1:
D8.2.15 CLIDR_EL1, Cache Level ID Register
Accessing the CLIDR_EL1:
D8.2.16 CONTEXTIDR_EL1, Context ID Register
Accessing the CONTEXTIDR_EL1:
D8.2.17 CPACR_EL1, Architectural Feature Access Control Register
Accessing the CPACR_EL1:
D8.2.18 CPTR_EL2, Architectural Feature Trap Register (EL2)
Accessing the CPTR_EL2:
D8.2.19 CPTR_EL3, Architectural Feature Trap Register (EL3)
Accessing the CPTR_EL3:
D8.2.20 CSSELR_EL1, Cache Size Selection Register
Accessing the CSSELR_EL1:
D8.2.21 CTR_EL0, Cache Type Register
Accessing the CTR_EL0:
D8.2.22 DACR32_EL2, Domain Access Control Register
Accessing the DACR32_EL2:
D8.2.23 DCZID_EL0, Data Cache Zero ID register
Accessing the DCZID_EL0:
D8.2.24 ESR_EL1, Exception Syndrome Register (EL1)
Accessing the ESR_EL1:
D8.2.25 ESR_EL2, Exception Syndrome Register (EL2)
Accessing the ESR_EL2:
D8.2.26 ESR_EL3, Exception Syndrome Register (EL3)
Accessing the ESR_EL3:
D8.2.27 FAR_EL1, Fault Address Register (EL1)
Accessing the FAR_EL1:
D8.2.28 FAR_EL2, Fault Address Register (EL2)
Accessing the FAR_EL2:
D8.2.29 FAR_EL3, Fault Address Register (EL3)
Accessing the FAR_EL3:
D8.2.30 FPEXC32_EL2, Floating-point Exception Control register
Accessing the FPEXC32_EL2:
D8.2.31 HACR_EL2, Hypervisor Auxiliary Control Register
Accessing the HACR_EL2:
D8.2.32 HCR_EL2, Hypervisor Configuration Register
Accessing the HCR_EL2:
D8.2.33 HPFAR_EL2, Hypervisor IPA Fault Address Register
Accessing the HPFAR_EL2:
D8.2.34 HSTR_EL2, Hypervisor System Trap Register
Accessing the HSTR_EL2:
D8.2.35 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
Accessing the ID_AA64AFR0_EL1:
D8.2.36 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
Accessing the ID_AA64AFR1_EL1:
D8.2.37 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0
Accessing the ID_AA64DFR0_EL1:
D8.2.38 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1
Accessing the ID_AA64DFR1_EL1:
D8.2.39 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0
Accessing the ID_AA64ISAR0_EL1:
D8.2.40 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1
Accessing the ID_AA64ISAR1_EL1:
D8.2.41 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0
Accessing the ID_AA64MMFR0_EL1:
D8.2.42 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1
Accessing the ID_AA64MMFR1_EL1:
D8.2.43 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0
Accessing the ID_AA64PFR0_EL1:
D8.2.44 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1
Accessing the ID_AA64PFR1_EL1:
D8.2.45 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0
Accessing the ID_AFR0_EL1:
D8.2.46 ID_DFR0_EL1, AArch32 Debug Feature Register 0
Accessing the ID_DFR0_EL1:
D8.2.47 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0
Accessing the ID_ISAR0_EL1:
D8.2.48 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1
Accessing the ID_ISAR1_EL1:
D8.2.49 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2
Accessing the ID_ISAR2_EL1:
D8.2.50 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3
Accessing the ID_ISAR3_EL1:
D8.2.51 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4
Accessing the ID_ISAR4_EL1:
D8.2.52 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5
Accessing the ID_ISAR5_EL1:
D8.2.53 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0
Accessing the ID_MMFR0_EL1:
D8.2.54 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1
Accessing the ID_MMFR1_EL1:
D8.2.55 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2
Accessing the ID_MMFR2_EL1:
D8.2.56 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3
Accessing the ID_MMFR3_EL1:
D8.2.57 ID_PFR0_EL1, AArch32 Processor Feature Register 0
Accessing the ID_PFR0_EL1:
D8.2.58 ID_PFR1_EL1, AArch32 Processor Feature Register 1
Accessing the ID_PFR1_EL1:
D8.2.59 IFSR32_EL2, Instruction Fault Status Register (EL2)
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the IFSR32_EL2:
D8.2.60 ISR_EL1, Interrupt Status Register
Accessing the ISR_EL1:
D8.2.61 MAIR_EL1, Memory Attribute Indirection Register (EL1)
Accessing the MAIR_EL1:
D8.2.62 MAIR_EL2, Memory Attribute Indirection Register (EL2)
Accessing the MAIR_EL2:
D8.2.63 MAIR_EL3, Memory Attribute Indirection Register (EL3)
Accessing the MAIR_EL3:
D8.2.64 MIDR_EL1, Main ID Register
Accessing the MIDR_EL1:
D8.2.65 MPIDR_EL1, Multiprocessor Affinity Register
Accessing the MPIDR_EL1:
D8.2.66 MVFR0_EL1, Media and VFP Feature Register 0
Accessing the MVFR0_EL1:
D8.2.67 MVFR1_EL1, Media and VFP Feature Register 1
Accessing the MVFR1_EL1:
D8.2.68 MVFR2_EL1, Media and VFP Feature Register 2
Accessing the MVFR2_EL1:
D8.2.69 PAR_EL1, Physical Address Register
When PAR_EL1.F==0:
When PAR_EL1.F==1:
Accessing the PAR_EL1:
D8.2.70 REVIDR_EL1, Revision ID Register
Accessing the REVIDR_EL1:
D8.2.71 RMR_EL1, Reset Management Register (if EL2 and EL3 not implemented)
Accessing the RMR_EL1:
D8.2.72 RMR_EL2, Reset Management Register (if EL3 not implemented)
Accessing the RMR_EL2:
D8.2.73 RMR_EL3, Reset Management Register (if EL3 implemented)
Accessing the RMR_EL3:
D8.2.74 RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented)
Accessing the RVBAR_EL1:
D8.2.75 RVBAR_EL2, Reset Vector Base Address Register (if EL3 not implemented)
Accessing the RVBAR_EL2:
D8.2.76 RVBAR_EL3, Reset Vector Base Address Register (if EL3 implemented)
Accessing the RVBAR_EL3:
D8.2.77 S3____, IMPLEMENTATION DEFINED registers
Accessing the S3____:
D8.2.78 SCR_EL3, Secure Configuration Register
Accessing the SCR_EL3:
D8.2.79 SCTLR_EL1, System Control Register (EL1)
Accessing the SCTLR_EL1:
D8.2.80 SCTLR_EL2, System Control Register (EL2)
Accessing the SCTLR_EL2:
D8.2.81 SCTLR_EL3, System Control Register (EL3)
Accessing the SCTLR_EL3:
D8.2.82 TCR_EL1, Translation Control Register (EL1)
Accessing the TCR_EL1:
D8.2.83 TCR_EL2, Translation Control Register (EL2)
Accessing the TCR_EL2:
D8.2.84 TCR_EL3, Translation Control Register (EL3)
Accessing the TCR_EL3:
D8.2.85 TEECR32_EL1, T32EE Configuration Register
Accessing the TEECR32_EL1:
D8.2.86 TEEHBR32_EL1, T32EE Handler Base Register
Accessing the TEEHBR32_EL1:
D8.2.87 TPIDR_EL0, Thread Pointer / ID Register (EL0)
Accessing the TPIDR_EL0:
D8.2.88 TPIDR_EL1, Thread Pointer / ID Register (EL1)
Accessing the TPIDR_EL1:
D8.2.89 TPIDR_EL2, Thread Pointer / ID Register (EL2)
Accessing the TPIDR_EL2:
D8.2.90 TPIDR_EL3, Thread Pointer / ID Register (EL3)
Accessing the TPIDR_EL3:
D8.2.91 TPIDRRO_EL0, Thread Pointer / ID Register, Read-Only (EL0)
Accessing the TPIDRRO_EL0:
D8.2.92 TTBR0_EL1, Translation Table Base Register 0 (EL1)
Accessing the TTBR0_EL1:
D8.2.93 TTBR0_EL2, Translation Table Base Register 0 (EL2)
Accessing the TTBR0_EL2:
D8.2.94 TTBR0_EL3, Translation Table Base Register 0 (EL3)
Accessing the TTBR0_EL3:
D8.2.95 TTBR1_EL1, Translation Table Base Register 1
Accessing the TTBR1_EL1:
D8.2.96 VBAR_EL1, Vector Base Address Register (EL1)
Accessing the VBAR_EL1:
D8.2.97 VBAR_EL2, Vector Base Address Register (EL2)
Accessing the VBAR_EL2:
D8.2.98 VBAR_EL3, Vector Base Address Register (EL3)
Accessing the VBAR_EL3:
D8.2.99 VMPIDR_EL2, Virtualization Multiprocessor ID Register
Accessing the VMPIDR_EL2:
D8.2.100 VPIDR_EL2, Virtualization Processor ID Register
Accessing the VPIDR_EL2:
D8.2.101 VTCR_EL2, Virtualization Translation Control Register
Accessing the VTCR_EL2:
D8.2.102 VTTBR_EL2, Virtualization Translation Table Base Register
Accessing the VTTBR_EL2:
D8.3 Debug registers
D8.3.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
Accessing the DBGAUTHSTATUS_EL1:
D8.3.2 DBGBCR_EL1, Debug Breakpoint Control Registers, n = 0 - 15
Accessing the DBGBCR_EL1:
D8.3.3 DBGBVR_EL1, Debug Breakpoint Value Registers, n = 0 - 15
When DBGBCR_EL1.BT==0b0x0x:
When DBGBCR_EL1.BT==0b0x1x:
When DBGBCR_EL1.BT==0b1x0x and EL2 implemented:
When DBGBCR_EL1.BT==0x1x1x and EL2 implemented:
Accessing the DBGBVR_EL1:
D8.3.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
Accessing the DBGCLAIMCLR_EL1:
D8.3.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
Accessing the DBGCLAIMSET_EL1:
D8.3.6 DBGDTR_EL0, Debug Data Transfer Register, half-duplex
Accessing the DBGDTR_EL0:
D8.3.7 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
Accessing the DBGDTRRX_EL0:
D8.3.8 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
Accessing the DBGDTRTX_EL0:
D8.3.9 DBGPRCR_EL1, Debug Power Control Register
Accessing the DBGPRCR_EL1:
D8.3.10 DBGVCR32_EL2, Debug Vector Catch Register
When EL3 implemented and using AArch64:
When EL3 not implemented:
Accessing the DBGVCR32_EL2:
D8.3.11 DBGWCR_EL1, Debug Watchpoint Control Registers, n = 0 - 15
Accessing the DBGWCR_EL1:
D8.3.12 DBGWVR_EL1, Debug Watchpoint Value Registers, n = 0 - 15
Accessing the DBGWVR_EL1:
D8.3.13 DLR_EL0, Debug Link Register
Accessing the DLR_EL0:
D8.3.14 DSPSR_EL0, Debug Saved Program Status Register
When entering Debug state from AArch32:
When entering Debug state from AArch64:
Accessing the DSPSR_EL0:
D8.3.15 MDCCINT_EL1, Monitor DCC Interrupt Enable Register
Accessing the MDCCINT_EL1:
D8.3.16 MDCCSR_EL0, Monitor DCC Status Register
Accessing the MDCCSR_EL0:
D8.3.17 MDCR_EL2, Monitor Debug Configuration Register (EL2)
Accessing the MDCR_EL2:
D8.3.18 MDCR_EL3, Monitor Debug Configuration Register (EL3)
Accessing the MDCR_EL3:
D8.3.19 MDRAR_EL1, Monitor Debug ROM Address Register
Accessing the MDRAR_EL1:
D8.3.20 MDSCR_EL1, Monitor Debug System Control Register
Accessing the MDSCR_EL1:
D8.3.21 OSDLR_EL1, OS Double Lock Register
Accessing the OSDLR_EL1:
D8.3.22 OSDTRRX_EL1, OS Lock Data Transfer Register, Receive
Accessing the OSDTRRX_EL1:
D8.3.23 OSDTRTX_EL1, OS Lock Data Transfer Register, Transmit
Accessing the OSDTRTX_EL1:
D8.3.24 OSECCR_EL1, OS Lock Exception Catch Control Register
When OSLSR.OSLK==1:
Accessing the OSECCR_EL1:
D8.3.25 OSLAR_EL1, OS Lock Access Register
Accessing the OSLAR_EL1:
D8.3.26 OSLSR_EL1, OS Lock Status Register
Accessing the OSLSR_EL1:
D8.3.27 SDER32_EL3, AArch32 Secure Debug Enable Register
Accessing the SDER32_EL3:
D8.4 Performance Monitors registers
D8.4.1 PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register
Accessing the PMCCFILTR_EL0:
D8.4.2 PMCCNTR_EL0, Performance Monitors Cycle Count Register
Accessing the PMCCNTR_EL0:
D8.4.3 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
Accessing the PMCEID0_EL0:
D8.4.4 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
Accessing the PMCEID1_EL0:
D8.4.5 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
Accessing the PMCNTENCLR_EL0:
D8.4.6 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
Accessing the PMCNTENSET_EL0:
D8.4.7 PMCR_EL0, Performance Monitors Control Register
Accessing the PMCR_EL0:
D8.4.8 PMEVCNTR_EL0, Performance Monitors Event Count Registers, n = 0 - 30
Accessing the PMEVCNTR_EL0:
D8.4.9 PMEVTYPER_EL0, Performance Monitors Event Type Registers, n = 0 - 30
Accessing the PMEVTYPER_EL0:
D8.4.10 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
Accessing the PMINTENCLR_EL1:
D8.4.11 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
Accessing the PMINTENSET_EL1:
D8.4.12 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear Register
Accessing the PMOVSCLR_EL0:
D8.4.13 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
Accessing the PMOVSSET_EL0:
D8.4.14 PMSELR_EL0, Performance Monitors Event Counter Selection Register
Accessing the PMSELR_EL0:
D8.4.15 PMSWINC_EL0, Performance Monitors Software Increment register
Accessing the PMSWINC_EL0:
D8.4.16 PMUSERENR_EL0, Performance Monitors User Enable Register
Accessing the PMUSERENR_EL0:
D8.4.17 PMXEVCNTR_EL0, Performance Monitors Selected Event Count Register
Accessing the PMXEVCNTR_EL0:
D8.4.18 PMXEVTYPER_EL0, Performance Monitors Selected Event Type Register
Accessing the PMXEVTYPER_EL0:
D8.5 Generic Timer registers
D8.5.1 CNTFRQ_EL0, Counter-timer Frequency register
Accessing the CNTFRQ_EL0:
D8.5.2 CNTHCTL_EL2, Counter-timer Hypervisor Control register
Accessing the CNTHCTL_EL2:
D8.5.3 CNTHP_CTL_EL2, Counter-timer Hypervisor Physical Timer Control register
Accessing the CNTHP_CTL_EL2:
D8.5.4 CNTHP_CVAL_EL2, Counter-timer Hypervisor Physical Timer CompareValue register
Accessing the CNTHP_CVAL_EL2:
D8.5.5 CNTHP_TVAL_EL2, Counter-timer Hypervisor Physical Timer TimerValue register
Accessing the CNTHP_TVAL_EL2:
D8.5.6 CNTKCTL_EL1, Counter-timer Kernel Control register
Accessing the CNTKCTL_EL1:
D8.5.7 CNTP_CTL_EL0, Counter-timer Physical Timer Control register
Accessing the CNTP_CTL_EL0:
D8.5.8 CNTP_CVAL_EL0, Counter-timer Physical Timer CompareValue register
Accessing the CNTP_CVAL_EL0:
D8.5.9 CNTP_TVAL_EL0, Counter-timer Physical Timer TimerValue register
Accessing the CNTP_TVAL_EL0:
D8.5.10 CNTPCT_EL0, Counter-timer Physical Count register
Accessing the CNTPCT_EL0:
D8.5.11 CNTPS_CTL_EL1, Counter-timer Physical Secure Timer Control register
Accessing the CNTPS_CTL_EL1:
D8.5.12 CNTPS_CVAL_EL1, Counter-timer Physical Secure Timer CompareValue register
Accessing the CNTPS_CVAL_EL1:
D8.5.13 CNTPS_TVAL_EL1, Counter-timer Physical Secure Timer TimerValue register
Accessing the CNTPS_TVAL_EL1:
D8.5.14 CNTV_CTL_EL0, Counter-timer Virtual Timer Control register
Accessing the CNTV_CTL_EL0:
D8.5.15 CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register
Accessing the CNTV_CVAL_EL0:
D8.5.16 CNTV_TVAL_EL0, Counter-timer Virtual Timer TimerValue register
Accessing the CNTV_TVAL_EL0:
D8.5.17 CNTVCT_EL0, Counter-timer Virtual Count register
Accessing the CNTVCT_EL0:
D8.5.18 CNTVOFF_EL2, Counter-timer Virtual Offset register
Accessing the CNTVOFF_EL2:
D8.6 Generic Interrupt Controller CPU interface registers
D8.6.1 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Register (0,0)
Accessing the ICC_AP0R0_EL1:
D8.6.2 ICC_AP0R1_EL1, Interrupt Controller Active Priorities Register (0,1)
Accessing the ICC_AP0R1_EL1:
D8.6.3 ICC_AP0R2_EL1, Interrupt Controller Active Priorities Register (0,2)
Accessing the ICC_AP0R2_EL1:
D8.6.4 ICC_AP0R3_EL1, Interrupt Controller Active Priorities Register (0,3)
Accessing the ICC_AP0R3_EL1:
D8.6.5 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Register (1,0)
Accessing the ICC_AP1R0_EL1:
D8.6.6 ICC_AP1R1_EL1, Interrupt Controller Active Priorities Register (1,1)
Accessing the ICC_AP1R1_EL1:
D8.6.7 ICC_AP1R2_EL1, Interrupt Controller Active Priorities Register (1,2)
Accessing the ICC_AP1R2_EL1:
D8.6.8 ICC_AP1R3_EL1, Interrupt Controller Active Priorities Register (1,3)
Accessing the ICC_AP1R3_EL1:
D8.6.9 ICC_ASGI1R_EL1, Interrupt Controller Alias Software Generated Interrupt group 1 Register
Accessing the ICC_ASGI1R_EL1:
D8.6.10 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0
Accessing the ICC_BPR0_EL1:
D8.6.11 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1
Accessing the ICC_BPR1_EL1:
D8.6.12 ICC_CTLR_EL1, Interrupt Controller Control Register (EL1)
Accessing the ICC_CTLR_EL1:
D8.6.13 ICC_CTLR_EL3, Interrupt Controller Control Register (EL3)
Accessing the ICC_CTLR_EL3:
D8.6.14 ICC_DIR_EL1, Interrupt Controller Deactivate Interrupt Register
Accessing the ICC_DIR_EL1:
D8.6.15 ICC_EOIR0_EL1, Interrupt Controller End Of Interrupt Register 0
Accessing the ICC_EOIR0_EL1:
D8.6.16 ICC_EOIR1_EL1, Interrupt Controller End Of Interrupt Register 1
Accessing the ICC_EOIR1_EL1:
D8.6.17 ICC_HPPIR0_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 0
Accessing the ICC_HPPIR0_EL1:
D8.6.18 ICC_HPPIR1_EL1, Interrupt Controller Highest Priority Pending Interrupt Register 1
Accessing the ICC_HPPIR1_EL1:
D8.6.19 ICC_IAR0_EL1, Interrupt Controller Interrupt Acknowledge Register 0
Accessing the ICC_IAR0_EL1:
D8.6.20 ICC_IAR1_EL1, Interrupt Controller Interrupt Acknowledge Register 1
Accessing the ICC_IAR1_EL1:
D8.6.21 ICC_IGRPEN0_EL1, Interrupt Controller Interrupt Group 0 Enable register
Accessing the ICC_IGRPEN0_EL1:
D8.6.22 ICC_IGRPEN1_EL1, Interrupt Controller Interrupt Group 1 Enable register
Accessing the ICC_IGRPEN1_EL1:
D8.6.23 ICC_IGRPEN1_EL3, Interrupt Controller Interrupt Group 1 Enable register (EL3)
Accessing the ICC_IGRPEN1_EL3:
D8.6.24 ICC_PMR_EL1, Interrupt Controller Interrupt Priority Mask Register
Accessing the ICC_PMR_EL1:
D8.6.25 ICC_RPR_EL1, Interrupt Controller Running Priority Register
Accessing the ICC_RPR_EL1:
D8.6.26 ICC_SEIEN_EL1, Interrupt Controller System Error Interrupt Enable register
Accessing the ICC_SEIEN_EL1:
D8.6.27 ICC_SGI0R_EL1, Interrupt Controller Software Generated Interrupt group 0 Register
Accessing the ICC_SGI0R_EL1:
D8.6.28 ICC_SGI1R_EL1, Interrupt Controller Software Generated Interrupt group 1 Register
Accessing the ICC_SGI1R_EL1:
D8.6.29 ICC_SRE_EL1, Interrupt Controller System Register Enable register (EL1)
Accessing the ICC_SRE_EL1:
D8.6.30 ICC_SRE_EL2, Interrupt Controller System Register Enable register (EL2)
Accessing the ICC_SRE_EL2:
D8.6.31 ICC_SRE_EL3, Interrupt Controller System Register Enable register (EL3)
Accessing the ICC_SRE_EL3:
D8.6.32 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Register (0,0)
Accessing the ICH_AP0R0_EL2:
D8.6.33 ICH_AP0R1_EL2, Interrupt Controller Hyp Active Priorities Register (0,1)
Accessing the ICH_AP0R1_EL2:
D8.6.34 ICH_AP0R2_EL2, Interrupt Controller Hyp Active Priorities Register (0,2)
Accessing the ICH_AP0R2_EL2:
D8.6.35 ICH_AP0R3_EL2, Interrupt Controller Hyp Active Priorities Register (0,3)
Accessing the ICH_AP0R3_EL2:
D8.6.36 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Register (1,0)
Accessing the ICH_AP1R0_EL2:
D8.6.37 ICH_AP1R1_EL2, Interrupt Controller Hyp Active Priorities Register (1,1)
Accessing the ICH_AP1R1_EL2:
D8.6.38 ICH_AP1R2_EL2, Interrupt Controller Hyp Active Priorities Register (1,2)
Accessing the ICH_AP1R2_EL2:
D8.6.39 ICH_AP1R3_EL2, Interrupt Controller Hyp Active Priorities Register (1,3)
Accessing the ICH_AP1R3_EL2:
D8.6.40 ICH_EISR_EL2, Interrupt Controller End of Interrupt Status Register
Accessing the ICH_EISR_EL2:
D8.6.41 ICH_ELSR_EL2, Interrupt Controller Empty List Register Status Register
Accessing the ICH_ELSR_EL2:
D8.6.42 ICH_HCR_EL2, Interrupt Controller Hyp Control Register
Accessing the ICH_HCR_EL2:
D8.6.43 ICH_LR_EL2, Interrupt Controller List Registers, n = 0 - 15
Accessing the ICH_LR_EL2:
D8.6.44 ICH_MISR_EL2, Interrupt Controller Maintenance Interrupt State Register
Accessing the ICH_MISR_EL2:
D8.6.45 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register
Accessing the ICH_VMCR_EL2:
D8.6.46 ICH_VSEIR_EL2, Interrupt Controller Virtual System Error Interrupt Register
Accessing the ICH_VSEIR_EL2:
D8.6.47 ICH_VTR_EL2, Interrupt Controller VGIC Type Register
Accessing the ICH_VTR_EL2:
Part E: The AArch32 Application Level Architecture
E1: The AArch32 Application Level Programmers’ Model
E1.1 About the Application level programmers’ model
E1.2 Additional information about the programmers’ model in AArch32 state
E1.2.1 Instruction sets, arithmetic operations, and register files
E1.2.2 Core data types and arithmetic in AArch32 state
Integer arithmetic
E1.2.3 The general-purpose registers, and the PC, in AArch32 state
Writing to the PC
Pseudocode details of operations on the AArch32 general-purpose registers and the PC
E1.2.4 The Application Program Status Register (APSR)
E1.2.5 Execution state registers
Instruction set state register, ISETSTATE
IT block state register, ITSTATE
Endianness mapping register, ENDIANSTATE
E1.2.6 Jazelle support
E1.3 Advanced SIMD and floating-point instructions
E1.3.1 Floating-point standards, and terminology
E1.3.2 The Advanced SIMD and floating-point register file
Advanced SIMD views of the register file
Floating-point views of the register file
Advanced SIMD and Floating-point register mapping
Pseudocode details of the Advanced SIMD and Floating-point register file
E1.3.3 Data types supported by the Advanced SIMD implementation
Advanced SIMD vectors
E1.3.4 Advanced SIMD and Floating-point system registers
E1.3.5 Trapping of floating-point exception
E1.3.6 Floating-point data types and arithmetic
E1.3.7 Floating-point exceptions
Combinations of exceptions
E1.3.8 Implications of not including Advanced SIMD and floating-point support
E1.3.9 Pseudocode details of floating-point operations
Generation of specific floating-point values
Floating-point negation and absolute value
Floating-point value unpacking
Floating-point exception and NaN handling
Floating-point rounding
Selection of ARM standard floating-point arithmetic
Floating-point comparisons
Floating-point maximum and minimum
Floating-point addition and subtraction
Floating-point multiplication and division
Floating-point fused multiply-add
Floating-point reciprocal estimate and step
Floating-point square root
Floating-point reciprocal square root estimate and step
Floating-point conversions
E1.4 Coprocessor support
E1.5 Exceptions and debug events
E2: The AArch32 Application Level Memory Model
E2.1 Address space
E2.2 Memory type overview
E2.3 Caches and memory hierarchy
E2.3.1 Introduction to caches
E2.3.2 Memory hierarchy
The cacheability and shareability memory attributes
E2.3.3 Implication of caches for the application programmer
Data coherency issues
Synchronization and coherency issues between data and instruction accesses
E2.3.4 Preloading caches
E2.4 Alignment support
E2.4.1 Instruction alignment
E2.4.2 Unaligned data access
E2.4.3 Cases where unaligned accesses are UNPREDICTABLE
E2.4.4 Unaligned data access restrictions
E2.5 Endian support
E2.5.1 General description of endianness in the ARM architecture
E2.5.2 Instruction endianness
E2.5.3 Data endianness
Instructions to reverse bytes in a general-purpose register or Advanced SIMD register
Endianness in SIMD
E2.6 Atomicity in the ARM architecture
E2.6.1 Single-copy atomicity
E2.6.2 Requirements for single-copy atomicity
E2.6.3 Multi-copy atomicity
E2.6.4 Requirements for multi-copy atomicity
E2.6.5 Concurrent modification and execution of instructions
E2.7 Memory ordering
E2.7.1 Observability and completion
Completion of side-effects of accesses to Device memory
E2.7.2 Ordering requirements
Address dependencies and order
E2.7.3 Memory barriers
Instruction Synchronization Barrier (ISB)
Data Memory Barrier (DMB)
Data Synchronization Barrier (DSB)
Shareability and access limitations on the data barrier operations
Load-Acquire, Store-Release
E2.8 Memory types and attributes
E2.8.1 Normal memory
Shareable Normal memory
Non-shareable Normal memory
Concurrent modification and execution of instructions
Multi-register loads and stores that access Normal memory
E2.8.2 Device memory
Gathering
Reordering
Early Write Acknowledgement
Multi-register loads and stores that access Device memory
E2.9 Mismatched memory attributes
E2.10 Synchronization and semaphores
E2.10.1 Exclusive access instructions and Non-shareable memory locations
Changes to the local monitor state resulting from speculative execution
E2.10.2 Exclusive access instructions and Shareable memory locations
Operation of the global monitor
E2.10.3 Marking and the size of the marked memory block
E2.10.4 Context switch support
E2.10.5 Load-Exclusive and Store-Exclusive instruction usage restrictions
E2.10.6 Use of WFE and SEV instructions by spin-locks
Part F: The AArch32 Instruction Sets
F1: The AArch32 Instruction Sets Overview
F1.1 Unified Assembler Language
F1.1.1 Conditional instructions
F1.1.2 Use of labels in UAL instruction syntax
F1.2 Branch instructions
F1.3 Data-processing instructions
F1.3.1 Standard data-processing instructions
F1.3.2 Shift instructions
F1.3.3 Multiply instructions
F1.3.4 Saturating instructions
F1.3.5 Saturating addition and subtraction instructions
F1.3.6 Packing and unpacking instructions
F1.3.7 Parallel addition and subtraction instructions
F1.3.8 Divide instructions
F1.3.9 Miscellaneous data-processing instructions
F1.4 Status register access instructions
F1.4.1 Banked register access instructions
F1.5 Load/store instructions
F1.5.1 Loads to the PC
F1.5.2 Halfword and byte loads and stores
F1.5.3 Load unprivileged and Store unprivileged
F1.5.4 Exclusive loads and stores
F1.5.5 Addressing modes
F1.6 Load/store multiple instructions
F1.6.1 Loads to the PC
F1.7 Miscellaneous instructions
F1.7.1 The Yield instruction
F1.8 Exception-generating and exception-handling instructions
F1.9 Coprocessor instructions
F1.10 Advanced SIMD and floating-point load/store instructions
F1.10.1 Element and structure load/store instructions
F1.11 Advanced SIMD and floating-point register transfer instructions
F1.12 Advanced SIMD data-processing instructions
F1.12.1 Advanced SIMD parallel addition and subtraction
F1.12.2 Bitwise Advanced SIMD data-processing instructions
F1.12.3 Advanced SIMD comparison instructions
F1.12.4 Advanced SIMD shift instructions
F1.12.5 Advanced SIMD multiply instructions
F1.12.6 Miscellaneous Advanced SIMD data-processing instructions
F1.13 Floating-point data-processing instructions
F2: About the T32 and A32 Instruction Descriptions
F2.1 Format of instruction descriptions
F2.1.1 Instruction section title
F2.1.2 Introduction to the instruction
F2.1.3 Instruction encodings
F2.1.4 Assembler syntax
Assembler syntax prototype line conventions
F2.1.5 Pseudocode describing how the instruction operates
F2.1.6 Exception information
F2.1.7 Notes
F2.2 Standard assembler syntax fields
F2.3 Conditional execution
F2.3.1 Pseudocode details of conditional execution
F2.4 Shifts applied to a register
F2.4.1 Constant shifts
Encoding
F2.4.2 Register controlled shifts
F2.4.3 Pseudocode details of instruction-specified shifts and rotates
F2.5 Memory accesses
F2.6 Integer arithmetic in the T32 and A32 instruction sets
F2.6.1 Shift and rotate operations
F2.6.2 Pseudocode details of addition and subtraction
F2.6.3 Pseudocode details of saturation
F2.7 Encoding of lists of general-purpose registers and the PC
F2.8 Additional pseudocode support for instruction descriptions
F2.8.1 Pseudocode details of coprocessor operations
F2.8.2 Calling the supervisor
F3: T32 Base Instruction Set Encoding
F3.1 T32 instruction set encoding
F3.1.1 UNDEFINED and UNPREDICTABLE instruction set space
F3.1.2 Use of the PC, and use of 0b1111 as a register specifier
F3.1.3 Use of the SP, and use of 0b1101 as a register specifier
F3.2 16-bit T32 instruction encoding
F3.2.1 Shift (immediate), add, subtract, move, and compare
F3.2.2 Data-processing
F3.2.3 Special data instructions and branch and exchange
F3.2.4 Load/store single data item
F3.2.5 Miscellaneous 16-bit instructions
If-Then, and hints
F3.2.6 Conditional branch, and Supervisor Call
F3.3 32-bit T32 instruction encoding
F3.3.1 Data-processing (modified immediate)
F3.3.2 Modified immediate constants in T32 instructions
Carry out
Operation of modified immediate constants, T32 instructions
F3.3.3 Data-processing (plain binary immediate)
F3.3.4 Branches and miscellaneous control
Change Processor State, and hints
Miscellaneous control instructions
F3.3.5 Load/store multiple
F3.3.6 Load/store dual, load/store exclusive, table branch
F3.3.7 Load word
F3.3.8 Load halfword, memory hints
F3.3.9 Load byte, memory hints
F3.3.10 Store single data item
F3.3.11 Data-processing (shifted register)
Move register and immediate shifts
F3.3.12 Data-processing (register)
F3.3.13 Parallel addition and subtraction, signed
F3.3.14 Parallel addition and subtraction, unsigned
F3.3.15 Miscellaneous operations
F3.3.16 Multiply, multiply accumulate, and absolute difference
F3.3.17 Long multiply, long multiply accumulate, and divide
F3.3.18 Coprocessor, Advanced SIMD, and floating-point instructions
F4: A32 Base Instruction Set Encoding
F4.1 A32 instruction set encoding
F4.1.1 The condition code field
F4.1.2 UNDEFINED and UNPREDICTABLE instruction set space
F4.1.3 The PC and the use of 0b1111 as a register specifier
F4.1.4 The SP and the use of 0b1101 as a register specifier
F4.2 Data-processing and miscellaneous instructions
F4.2.1 Data-processing (register)
F4.2.2 Data-processing (register-shifted register)
F4.2.3 Data-processing (immediate)
F4.2.4 Modified immediate constants in A32 instructions
Carry out
Constants with multiple encodings
Operation of modified immediate constants, A32 instructions
F4.2.5 Multiply and multiply accumulate
F4.2.6 Saturating addition and subtraction
F4.2.7 Halfword multiply and multiply accumulate
F4.2.8 Extra load/store instructions
F4.2.9 Extra load/store instructions, unprivileged
F4.2.10 Synchronization primitives
F4.2.11 MSR (immediate), and hints
F4.2.12 Miscellaneous instructions
F4.3 Load/store word and unsigned byte
F4.4 Media instructions
F4.4.1 Parallel addition and subtraction, signed
F4.4.2 Parallel addition and subtraction, unsigned
F4.4.3 Packing, unpacking, saturation, and reversal
F4.4.4 Signed multiply, signed and unsigned divide
F4.5 Branch, branch with link, and block data transfer
F4.6 Coprocessor instructions, and Supervisor Call
F4.7 Unconditional instructions
F4.7.1 Memory hints, Advanced SIMD instructions, and miscellaneous instructions
F5: T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings
F5.1 Overview
F5.1.1 Advanced SIMD
F5.1.2 Floating-point
F5.2 Advanced SIMD and floating-point instruction syntax
F5.2.1 Advanced SIMD instruction modifiers
F5.2.2 Advanced SIMD operand shapes
F5.2.3 Data type specifiers
Syntax flexibility
F5.2.4 Register specifiers
F5.2.5 Register lists
Syntax flexibility
F5.3 Register encoding
F5.3.1 Advanced SIMD scalars
F5.4 Advanced SIMD data-processing instructions
F5.4.1 Three registers of the same length
F5.4.2 Three registers of different lengths
F5.4.3 Two registers and a scalar
F5.4.4 Two registers and a shift amount
F5.4.5 Two registers, miscellaneous
F5.4.6 One register and a modified immediate value
Advanced SIMD expand immediate pseudocode
F5.5 Floating-point data-processing instructions
F5.5.1 Operation of modified immediate constants, floating-point
F5.6 Extension register load/store instructions
F5.7 Advanced SIMD element or structure load/store instructions
F5.7.1 Advanced SIMD addressing mode
F5.8 8, 16, and 32-bit transfer between general-purpose and extension registers
F5.9 64-bit transfers between general-purpose and extension registers
F6: ARMv8 Changes to the T32 and A32 Instruction Sets
F6.1 The A32 and T32 instruction sets
F6.2 Partial Deprecation of IT
F6.3 New A32 and T32 Load-Acquire/Store-Release instructions
F6.3.1 A32 and T32 Load-Acquire/Store-Release (non-exclusive) instructions
F6.3.2 A32 and T32 Load-Acquire/Store-Release Exclusive instructions
F6.4 New A32 and T32 scalar floating-point instructions
F6.4.1 A32 and T32 floating-point conditional select
F6.4.2 A32 and T32 floating-point minimum and maximum numeric
F6.4.3 A32 and T32 floating-point to integer conversion
F6.4.4 A32 and T32 floating-point conversion between half-precision and double-precision
F6.4.5 A32 and T32 floating-point round to integral
F6.5 New A32 and T32 Advanced SIMD floating-point instructions
F6.5.1 A32 and T32 floating-point minimum and maximum numeric
F6.5.2 A32 and T32 floating-point conversion
F6.5.3 A32 and T32 floating-point round to integral
F6.6 New A32 and T32 cryptography instructions
F6.7 New A32 and T32 System instructions
F6.7.1 External Debug
F6.7.2 Barriers and hints
F6.7.3 TLB Maintenance
F7: T32 and A32 Base Instruction Set Instruction Descriptions
F7.1 Alphabetical list of T32 and A32 base instruction set instructions
F7.1.1 ADC (immediate)
Assembler syntax
Operation
F7.1.2 ADC (register)
Assembler syntax
Operation
F7.1.3 ADC (register-shifted register)
Assembler syntax
Operation
F7.1.4 ADD (immediate, T32)
Assembler syntax
Operation
F7.1.5 ADD (immediate, A32)
Assembler syntax
Operation
F7.1.6 ADD (register, T32)
Assembler syntax
Operation
F7.1.7 ADD (register, A32)
Assembler syntax
Operation
F7.1.8 ADD (register-shifted register)
Assembler syntax
Operation
F7.1.9 ADD (SP plus immediate)
Assembler syntax
Operation
F7.1.10 ADD (SP plus register, T32)
Assembler syntax
Operation
F7.1.11 ADD (SP plus register, A32)
Assembler syntax
Operation
F7.1.12 ADR
Assembler syntax
Operation
F7.1.13 AND (immediate)
Assembler syntax
Operation
F7.1.14 AND (register)
Assembler syntax
Operation
F7.1.15 AND (register-shifted register)
Assembler syntax
Operation
F7.1.16 ASR (immediate)
Assembler syntax
Operation
F7.1.17 ASR (register)
Assembler syntax
Operation
F7.1.18 B
Assembler syntax
Operation
F7.1.19 BFC
Assembler syntax
Operation
F7.1.20 BFI
Assembler syntax
Operation
F7.1.21 BIC (immediate)
Assembler syntax
Operation
F7.1.22 BIC (register)
Assembler syntax
Operation
F7.1.23 BIC (register-shifted register)
Assembler syntax
Operation
F7.1.24 BKPT
Assembler syntax
Operation
F7.1.25 BL, BLX (immediate)
Assembler syntax
Operation
F7.1.26 BLX (register)
Assembler syntax
Operation
F7.1.27 BX
Assembler syntax
Operation
F7.1.28 BXJ
Assembler syntax
Operation
F7.1.29 CBNZ, CBZ
Assembler syntax
Operation
F7.1.30 CDP, CDP2
Assembler syntax
Operation
F7.1.31 CLREX
Assembler syntax
Operation
F7.1.32 CLZ
Assembler syntax
Operation
F7.1.33 CMN (immediate)
Assembler syntax
Operation
F7.1.34 CMN (register)
Assembler syntax
Operation
F7.1.35 CMN (register-shifted register)
Assembler syntax
Operation
F7.1.36 CMP (immediate)
Assembler syntax
Operation
F7.1.37 CMP (register)
Assembler syntax
Operation
F7.1.38 CMP (register-shifted register)
Assembler syntax
Operation
F7.1.39 CPS
F7.1.40 CPY
Assembler syntax
F7.1.41 CRC32, CRC32C
Assembler syntax
Operation
F7.1.42 DBG
Assembler syntax
Operation
F7.1.43 DCPS1, DCPS2, DCPS3
Assembler syntax
Operation
F7.1.44 DMB
Assembler syntax
Operation
F7.1.45 DSB
Assembler syntax
Operation
F7.1.46 EOR (immediate)
Assembler syntax
Operation
F7.1.47 EOR (register)
Assembler syntax
Operation
F7.1.48 EOR (register-shifted register)
Assembler syntax
Operation
F7.1.49 ERET
F7.1.50 HLT
Assembler syntax
Operation
F7.1.51 HVC
F7.1.52 ISB
Assembler syntax
Operation
F7.1.53 IT
Assembler syntax
Operation
F7.1.54 LDA
Assembler syntax
Operation
F7.1.55 LDAB
Assembler syntax
Operation
F7.1.56 LDAEX
Assembler syntax
Operation
F7.1.57 LDAEXB
Assembler syntax
Operation
F7.1.58 LDAEXD
Assembler syntax
Operation
F7.1.59 LDAEXH
Assembler syntax
Operation
F7.1.60 LDAH
Assembler syntax
Operation
F7.1.61 LDC, LDC2 (immediate)
Assembler syntax
Operation
F7.1.62 LDC, LDC2 (literal)
Assembler syntax
Operation
F7.1.63 LDM/LDMIA/LDMFD (T32)
Assembler syntax
Operation
F7.1.64 LDM/LDMIA/LDMFD (A32)
Assembler syntax
Operation
F7.1.65 LDMDA/LDMFA
Assembler syntax
Operation
F7.1.66 LDMDB/LDMEA
Assembler syntax
Operation
F7.1.67 LDMIB/LDMED
Assembler syntax
Operation
F7.1.68 LDR (immediate, T32)
Assembler syntax
Operation
F7.1.69 LDR (immediate, A32)
Assembler syntax
Operation
F7.1.70 LDR (literal)
Assembler syntax
Operation
F7.1.71 LDR (register, T32)
Assembler syntax
Operation
F7.1.72 LDR (register, A32)
Assembler syntax
Operation
F7.1.73 LDRB (immediate, T32)
Assembler syntax
Operation
F7.1.74 LDRB (immediate, A32)
Assembler syntax
Operation
F7.1.75 LDRB (literal)
Assembler syntax
Operation
F7.1.76 LDRB (register)
Assembler syntax
Operation
F7.1.77 LDRBT
Assembler syntax
Operation
F7.1.78 LDRD (immediate)
Assembler syntax
Operation
F7.1.79 LDRD (literal)
Assembler syntax
Operation
F7.1.80 LDRD (register)
Assembler syntax
Operation
F7.1.81 LDREX
Assembler syntax
Operation
F7.1.82 LDREXB
Assembler syntax
Operation
F7.1.83 LDREXD
Assembler syntax
Operation
F7.1.84 LDREXH
Assembler syntax
Operation
F7.1.85 LDRH (immediate, T32)
Assembler syntax
Operation
F7.1.86 LDRH (immediate, A32)
Assembler syntax
Operation
F7.1.87 LDRH (literal)
Assembler syntax
Operation
F7.1.88 LDRH (register)
Assembler syntax
Operation
F7.1.89 LDRHT
Assembler syntax
Operation
F7.1.90 LDRSB (immediate)
Assembler syntax
Operation
F7.1.91 LDRSB (literal)
Assembler syntax
Operation
F7.1.92 LDRSB (register)
Assembler syntax
Operation
F7.1.93 LDRSBT
Assembler syntax
Operation
F7.1.94 LDRSH (immediate)
Assembler syntax
Operation
F7.1.95 LDRSH (literal)
Assembler syntax
Operation
F7.1.96 LDRSH (register)
Assembler syntax
Operation
F7.1.97 LDRSHT
Assembler syntax
Operation
F7.1.98 LDRT
Assembler syntax
Operation
F7.1.99 LSL (immediate)
Assembler syntax
Operation
F7.1.100 LSL (register)
Assembler syntax
Operation
F7.1.101 LSR (immediate)
Assembler syntax
Operation
F7.1.102 LSR (register)
Assembler syntax
Operation
F7.1.103 MCR, MCR2
Assembler syntax
Operation
F7.1.104 MCRR, MCRR2
Assembler syntax
Operation
F7.1.105 MLA
Assembler syntax
Operation
F7.1.106 MLS
Assembler syntax
Operation
F7.1.107 MOV (immediate)
Assembler syntax
Operation
F7.1.108 MOV (register, T32)
Assembler syntax
Operation
F7.1.109 MOV (register, A32)
Assembler syntax
Operation
F7.1.110 MOV (shifted register)
Assembler syntax
F7.1.111 MOVT
Assembler syntax
Operation
F7.1.112 MRC, MRC2
Assembler syntax
Operation
F7.1.113 MRRC, MRRC2
Assembler syntax
Operation
F7.1.114 MRS
Assembler syntax
Operation
F7.1.115 MRS (Banked register)
F7.1.116 MSR (immediate)
Assembler syntax
Operation
Usage
F7.1.117 MSR (register)
Assembler syntax
Operation
Usage
F7.1.118 MSR (Banked register)
F7.1.119 MUL
Assembler syntax
Operation
F7.1.120 MVN (immediate)
Assembler syntax
Operation
F7.1.121 MVN (register)
Assembler syntax
Operation
F7.1.122 MVN (register-shifted register)
Assembler syntax
Operation
F7.1.123 NEG
Assembler syntax
F7.1.124 NOP
Assembler syntax
Operation
F7.1.125 ORN (immediate)
Assembler syntax
Operation
F7.1.126 ORN (register)
Assembler syntax
Operation
F7.1.127 ORR (immediate)
Assembler syntax
Operation
F7.1.128 ORR (register)
Assembler syntax
Operation
F7.1.129 ORR (register-shifted register)
Assembler syntax
Operation
F7.1.130 PKH
Assembler syntax
Operation
F7.1.131 PLD, PLDW (immediate)
Assembler syntax
Operation
F7.1.132 PLD (literal)
Assembler syntax
Operation
F7.1.133 PLD, PLDW (register)
Assembler syntax
Operation
F7.1.134 PLI (immediate, literal)
Assembler syntax
Operation
F7.1.135 PLI (register)
Assembler syntax
Operation
F7.1.136 POP (T32)
Assembler syntax
Operation
F7.1.137 POP (A32)
Assembler syntax
Operation
F7.1.138 PUSH
Assembler syntax
Operation
F7.1.139 QADD
Assembler syntax
Operation
F7.1.140 QADD8
Assembler syntax
Operation
F7.1.141 QADD16
Assembler syntax
Operation
F7.1.142 QASX
Assembler syntax
Operation
F7.1.143 QDADD
Assembler syntax
Operation
F7.1.144 QDSUB
Assembler syntax
Operation
F7.1.145 QSAX
Assembler syntax
Operation
F7.1.146 QSUB
Assembler syntax
Operation
F7.1.147 QSUB8
Assembler syntax
Operation
F7.1.148 QSUB16
Assembler syntax
Operation
F7.1.149 RBIT
Assembler syntax
Operation
F7.1.150 REV
Assembler syntax
Operation
F7.1.151 REV16
Assembler syntax
Operation
F7.1.152 REVSH
Assembler syntax
Operation
F7.1.153 RFE
F7.1.154 ROR (immediate)
Assembler syntax
Operation
F7.1.155 ROR (register)
Assembler syntax
Operation
F7.1.156 RRX
Assembler syntax
Operation
F7.1.157 RSB (immediate)
Assembler syntax
Operation
F7.1.158 RSB (register)
Assembler syntax
Operation
F7.1.159 RSB (register-shifted register)
Assembler syntax
Operation
F7.1.160 RSC (immediate)
Assembler syntax
Operation
F7.1.161 RSC (register)
Assembler syntax
Operation
F7.1.162 RSC (register-shifted register)
Assembler syntax
Operation
F7.1.163 SADD8
Assembler syntax
Operation
F7.1.164 SADD16
Assembler syntax
Operation
F7.1.165 SASX
Assembler syntax
Operation
F7.1.166 SBC (immediate)
Assembler syntax
Operation
F7.1.167 SBC (register)
Assembler syntax
Operation
F7.1.168 SBC (register-shifted register)
Assembler syntax
Operation
F7.1.169 SBFX
Assembler syntax
Operation
F7.1.170 SDIV
Assembler syntax
Operation
Overflow
F7.1.171 SEL
Assembler syntax
Operation
F7.1.172 SETEND
Assembler syntax
Operation
F7.1.173 SEV
Assembler syntax
Operation
F7.1.174 SEVL
Assembler syntax
Operation
F7.1.175 SHADD8
Assembler syntax
Operation
F7.1.176 SHADD16
Assembler syntax
Operation
F7.1.177 SHASX
Assembler syntax
Operation
F7.1.178 SHSAX
Assembler syntax
Operation
F7.1.179 SHSUB8
Assembler syntax
Operation
F7.1.180 SHSUB16
Assembler syntax
Operation
F7.1.181 SMC (previously SMI)
F7.1.182 SMLABB, SMLABT, SMLATB, SMLATT
Assembler syntax
Operation
F7.1.183 SMLAD
Assembler syntax
Operation
F7.1.184 SMLAL
Assembler syntax
Operation
F7.1.185 SMLALBB, SMLALBT, SMLALTB, SMLALTT
Assembler syntax
Operation
F7.1.186 SMLALD
Assembler syntax
Operation
F7.1.187 SMLAWB, SMLAWT
Assembler syntax
Operation
F7.1.188 SMLSD
Assembler syntax
Operation
F7.1.189 SMLSLD
Assembler syntax
Operation
F7.1.190 SMMLA
Assembler syntax
Operation
F7.1.191 SMMLS
Assembler syntax
Operation
F7.1.192 SMMUL
Assembler syntax
Operation
F7.1.193 SMUAD
Assembler syntax
Operation
F7.1.194 SMULBB, SMULBT, SMULTB, SMULTT
Assembler syntax
Operation
F7.1.195 SMULL
Assembler syntax
Operation
F7.1.196 SMULWB, SMULWT
Assembler syntax
Operation
F7.1.197 SMUSD
Assembler syntax
Operation
F7.1.198 SRS
F7.1.199 SSAT
Assembler syntax
Operation
F7.1.200 SSAT16
Assembler syntax
Operation
F7.1.201 SSAX
Assembler syntax
Operation
F7.1.202 SSUB8
Assembler syntax
Operation
F7.1.203 SSUB16
Assembler syntax
Operation
F7.1.204 STC, STC2
Assembler syntax
Operation
F7.1.205 STL
Assembler syntax
Operation
F7.1.206 STLB
Assembler syntax
Operation
F7.1.207 STLEX
Assembler syntax
Operation
Aborts and alignment
F7.1.208 STLEXB
Assembler syntax
Operation
Aborts
F7.1.209 STLEXD
Assembler syntax
Operation
Aborts and alignment
F7.1.210 STLEXH
Assembler syntax
Operation
Aborts and alignment
F7.1.211 STLH
Assembler syntax
Operation
F7.1.212 STM (STMIA, STMEA)
Assembler syntax
Operation
F7.1.213 STMDA (STMED)
Assembler syntax
Operation
F7.1.214 STMDB (STMFD)
Assembler syntax
Operation
F7.1.215 STMIB (STMFA)
Assembler syntax
Operation
F7.1.216 STR (immediate, T32)
Assembler syntax
Operation
F7.1.217 STR (immediate, A32)
Assembler syntax
Operation
F7.1.218 STR (register)
Assembler syntax
Operation
F7.1.219 STRB (immediate, T32)
Assembler syntax
Operation
F7.1.220 STRB (immediate, A32)
Assembler syntax
Operation
F7.1.221 STRB (register)
Assembler syntax
Operation
F7.1.222 STRBT
Assembler syntax
Operation
F7.1.223 STRD (immediate)
Assembler syntax
Operation
F7.1.224 STRD (register)
Assembler syntax
Operation
F7.1.225 STREX
Assembler syntax
Operation
Aborts and alignment
F7.1.226 STREXB
Assembler syntax
Operation
Aborts
F7.1.227 STREXD
Assembler syntax
Operation
Aborts and alignment
F7.1.228 STREXH
Assembler syntax
Operation
Aborts and alignment
F7.1.229 STRH (immediate, T32)
Assembler syntax
Operation
F7.1.230 STRH (immediate, A32)
Assembler syntax
Operation
F7.1.231 STRH (register)
Assembler syntax
Operation
F7.1.232 STRHT
Assembler syntax
Operation
F7.1.233 STRT
Assembler syntax
Operation
F7.1.234 SUB (immediate, T32)
Assembler syntax
Operation
F7.1.235 SUB (immediate, A32)
Assembler syntax
Operation
F7.1.236 SUB (register)
Assembler syntax
Operation
F7.1.237 SUB (register-shifted register)
Assembler syntax
Operation
F7.1.238 SUB (SP minus immediate)
Assembler syntax
Operation
F7.1.239 SUB (SP minus register)
Assembler syntax
Operation
F7.1.240 SUBS PC, LR and related instructions
F7.1.241 SVC (previously SWI)
Assembler syntax
Operation
F7.1.242 SXTAB
Assembler syntax
Operation
F7.1.243 SXTAB16
Assembler syntax
Operation
F7.1.244 SXTAH
Assembler syntax
Operation
F7.1.245 SXTB
Assembler syntax
Operation
F7.1.246 SXTB16
Assembler syntax
Operation
F7.1.247 SXTH
Assembler syntax
Operation
F7.1.248 TBB, TBH
Assembler syntax
Operation
F7.1.249 TEQ (immediate)
Assembler syntax
Operation
F7.1.250 TEQ (register)
Assembler syntax
Operation
F7.1.251 TEQ (register-shifted register)
Assembler syntax
Operation
F7.1.252 TST (immediate)
Assembler syntax
Operation
F7.1.253 TST (register)
Assembler syntax
Operation
F7.1.254 TST (register-shifted register)
Assembler syntax
Operation
F7.1.255 UADD8
Assembler syntax
Operation
F7.1.256 UADD16
Assembler syntax
Operation
F7.1.257 UASX
Assembler syntax
Operation
F7.1.258 UBFX
Assembler syntax
Operation
F7.1.259 UDF
Assembler syntax
Operation
F7.1.260 UDIV
Assembler syntax
Operation
F7.1.261 UHADD8
Assembler syntax
Operation
F7.1.262 UHADD16
Assembler syntax
Operation
F7.1.263 UHASX
Assembler syntax
Operation
F7.1.264 UHSAX
Assembler syntax
Operation
F7.1.265 UHSUB8
Assembler syntax
Operation
F7.1.266 UHSUB16
Assembler syntax
Operation
F7.1.267 UMAAL
Assembler syntax
Operation
F7.1.268 UMLAL
Assembler syntax
Operation
F7.1.269 UMULL
Assembler syntax
Operation
F7.1.270 UQADD8
Assembler syntax
Operation
F7.1.271 UQADD16
Assembler syntax
Operation
F7.1.272 UQASX
Assembler syntax
Operation
F7.1.273 UQSAX
Assembler syntax
Operation
F7.1.274 UQSUB8
Assembler syntax
Operation
F7.1.275 UQSUB16
Assembler syntax
Operation
F7.1.276 USAD8
Assembler syntax
Operation
F7.1.277 USADA8
Assembler syntax
Operation
F7.1.278 USAT
Assembler syntax
Operation
F7.1.279 USAT16
Assembler syntax
Operation
F7.1.280 USAX
Assembler syntax
Operation
F7.1.281 USUB8
Assembler syntax
Operation
F7.1.282 USUB16
Assembler syntax
Operation
F7.1.283 UXTAB
Assembler syntax
Operation
F7.1.284 UXTAB16
Assembler syntax
Operation
F7.1.285 UXTAH
Assembler syntax
Operation
F7.1.286 UXTB
Assembler syntax
Operation
F7.1.287 UXTB16
Assembler syntax
Operation
F7.1.288 UXTH
Assembler syntax
Operation
F7.1.289 WFE
Assembler syntax
Operation
F7.1.290 WFI
Assembler syntax
Operation
F7.1.291 YIELD
Assembler syntax
Operation
F7.2 General restrictions on system instructions
F7.2.1 Restrictions on exception return instructions
F7.2.2 Restrictions on updates to the CPSR.M field
F7.3 Encoding and use of Banked register transfer instructions
F7.3.1 Register arguments in the Banked register transfer instructions
F7.3.2 Usage restrictions on the Banked register transfer instructions
F7.3.3 Encoding the register argument in the Banked register transfer instructions
F7.3.4 Pseudocode support for the Banked register transfer instructions
F7.4 Alphabetical list of system instructions
F7.4.1 CPS (T32)
Hint instructions
Assembler syntax
Operation
F7.4.2 CPS (A32)
Assembler syntax
Operation
F7.4.3 ERET
Assembler syntax
Operation
F7.4.4 HVC
Assembler syntax
Operation
F7.4.5 LDM (exception return)
Assembler syntax
Operation
F7.4.6 LDM (User registers)
Assembler syntax
Operation
F7.4.7 LDRBT, LDRHT, LDRSBT, LDRSHT, and LDRT
F7.4.8 MRS
Assembler syntax
Operation
F7.4.9 MRS (Banked register)
Assembler syntax
Operation
F7.4.10 MSR (Banked register)
Assembler syntax
Operation
F7.4.11 MSR (immediate)
Assembler syntax
Operation
E bit
F7.4.12 MSR (register)
Assembler syntax
Operation
E bit
F7.4.13 RFE
Assembler syntax
Operation
F7.4.14 SMC (previously SMI)
Assembler syntax
Operation
F7.4.15 SRS (T32)
Assembler syntax
Operation
F7.4.16 SRS (A32)
Assembler syntax
Operation
F7.4.17 STM (User registers)
Assembler syntax
Operation
F7.4.18 STRBT, STRHT, and STRT
F7.4.19 SUBS PC, LR and related instructions (T32)
Assembler syntax
Operation
F7.4.20 SUBS PC, LR and related instructions (A32)
Assembler syntax
Operation
F7.4.21 VMRS
Assembler syntax
Operation
F7.4.22 VMSR
Assembler syntax
Operation
F8: T32 and A32 Advanced SIMD and floating-point Instruction Descriptions
F8.1 Alphabetical list of floating-point and Advanced SIMD instructions
F8.1.1 AESD
Assembler syntax
Operation
F8.1.2 AESE
Assembler syntax
Operation
F8.1.3 AESIMC
Assembler syntax
Operation
F8.1.4 AESMC
Assembler syntax
Operation
F8.1.5 F*, former floating-point instruction mnemonics
FLDMX, FSTMX
F8.1.6 SHA1C
Assembler syntax
Operation
F8.1.7 SHA1H
Assembler syntax
Operation
F8.1.8 SHA1M
Assembler syntax
Operation
F8.1.9 SHA1P
Assembler syntax
Operation
F8.1.10 SHA1SU0
Assembler syntax
Operation
F8.1.11 SHA1SU1
Assembler syntax
Operation
F8.1.12 SHA256H
Assembler syntax
Operation
F8.1.13 SHA256H2
Assembler syntax
Operation
F8.1.14 SHA256SU0
Assembler syntax
Operation
F8.1.15 SHA256SU1
Assembler syntax
Operation
F8.1.16 VABA, VABAL
Assembler syntax
Operation
F8.1.17 VABD, VABDL (integer)
Assembler syntax
Operation
F8.1.18 VABD (floating-point)
Assembler syntax
Operation
F8.1.19 VABS
Assembler syntax
Operation
F8.1.20 VACGE, VACGT, VACLE, VACLT
Assembler syntax
Operation
F8.1.21 VADD (integer)
Assembler syntax
Operation
F8.1.22 VADD (floating-point)
Assembler syntax
Operation
F8.1.23 VADDHN
Assembler syntax
Operation
F8.1.24 VADDL, VADDW
Assembler syntax
Operation
F8.1.25 VAND (immediate)
F8.1.26 VAND (register)
Assembler syntax
Operation
F8.1.27 VBIC (immediate)
Assembler syntax
Operation
Pseudo-instructions
F8.1.28 VBIC (register)
Assembler syntax
Operation
F8.1.29 VBIF, VBIT, VBSL
Assembler syntax
Operation
F8.1.30 VCEQ (register)
Assembler syntax
Operation
F8.1.31 VCEQ (immediate #0)
Assembler syntax
Operation
F8.1.32 VCGE (register)
Assembler syntax
Operation
F8.1.33 VCGE (immediate #0)
Assembler syntax
Operation
F8.1.34 VCGT (register)
Assembler syntax
Operation
F8.1.35 VCGT (immediate #0)
Assembler syntax
Operation
F8.1.36 VCLE (register)
F8.1.37 VCLE (immediate #0)
Assembler syntax
Operation
F8.1.38 VCLS
Assembler syntax
Operation
F8.1.39 VCLT (register)
F8.1.40 VCLT (immediate #0)
Assembler syntax
Operation
F8.1.41 VCLZ
Assembler syntax
Operation
F8.1.42 VCMP, VCMPE
Assembler syntax
Operation
NaNs
F8.1.43 VCNT
Assembler syntax
Operation
F8.1.44 VCVT (between floating-point and integer, Advanced SIMD)
Assembler syntax
Operation
F8.1.45 VCVT, VCVTR (between floating-point and integer, floating-point)
Assembler syntax
Operation
F8.1.46 VCVT (between floating-point and fixed-point, Advanced SIMD)
Assembler syntax
Operation
F8.1.47 VCVT (between floating-point and fixed-point, floating-point)
Assembler syntax
Operation
F8.1.48 VCVT (between double-precision and single-precision)
Assembler syntax
Operation
F8.1.49 VCVT (between half-precision and single-precision, Advanced SIMD)
Assembler syntax
Operation
F8.1.50 VCVTA, VCVTN, VCVTP, VCVTM (between floating-point and integer, Advanced SIMD)
Assembler syntax
Operation
F8.1.51 VCVTA, VCVTN, VCVTP, VCVTM (between floating-point and integer, floating-point)
Assembler syntax
Operation
F8.1.52 VCVTB, VCVTT
Assembler syntax
Operation
F8.1.53 VDIV
Assembler syntax
Operation
F8.1.54 VDUP (scalar)
Assembler syntax
Operation
F8.1.55 VDUP (general-purpose register)
Assembler syntax
Operation
F8.1.56 VEOR
Assembler syntax
Operation
F8.1.57 VEXT
Assembler syntax
Operation
F8.1.58 VFMA, VFMS
Assembler syntax
Operation
F8.1.59 VFNMA, VFNMS
Assembler syntax
Operation
F8.1.60 VHADD, VHSUB
Assembler syntax
Operation
F8.1.61 VLD1 (multiple single elements)
Assembler syntax
Operation
F8.1.62 VLD1 (single element to one lane)
Assembler syntax
Operation
F8.1.63 VLD1 (single element to all lanes)
Assembler syntax
Operation
F8.1.64 VLD2 (multiple 2-element structures)
Assembler syntax
Operation
F8.1.65 VLD2 (single 2-element structure to one lane)
Assembler syntax
Operation
F8.1.66 VLD2 (single 2-element structure to all lanes)
Assembler syntax
Operation
F8.1.67 VLD3 (multiple 3-element structures)
Assembler syntax
Operation
F8.1.68 VLD3 (single 3-element structure to one lane)
Assembler syntax
Alignment
Operation
F8.1.69 VLD3 (single 3-element structure to all lanes)
Assembler syntax
Alignment
Operation
F8.1.70 VLD4 (multiple 4-element structures)
Assembler syntax
Operation
F8.1.71 VLD4 (single 4-element structure to one lane)
Assembler syntax
Operation
F8.1.72 VLD4 (single 4-element structure to all lanes)
Assembler syntax
Operation
F8.1.73 VLDM
Assembler syntax
Operation
F8.1.74 VLDR
Assembler syntax
Operation
F8.1.75 VMAX, VMIN (integer)
Assembler syntax
Operation
F8.1.76 VMAX, VMIN (floating-point)
Assembler syntax
Operation
Floating-point maximum and minimum
F8.1.77 VMAXNM, VMINNM
Assembler syntax
Operation
F8.1.78 VMLA, VMLAL, VMLS, VMLSL (integer)
Assembler syntax
Operation
F8.1.79 VMLA, VMLS (floating-point)
Assembler syntax
Operation
F8.1.80 VMLA, VMLAL, VMLS, VMLSL (by scalar)
Assembler syntax
Operation
F8.1.81 VMOV (immediate)
Assembler syntax
Operation
Pseudo-instructions
F8.1.82 VMOV (register)
Assembler syntax
Operation
F8.1.83 VMOV (general-purpose register to scalar)
Assembler syntax
Operation
F8.1.84 VMOV (scalar to general-purpose register)
Assembler syntax
Operation
F8.1.85 VMOV (between general-purpose register and single-precision register)
Assembler syntax
Operation
F8.1.86 VMOV (between two general-purpose registers and two single-precision registers)
Assembler syntax
Operation
F8.1.87 VMOV (between two general-purpose registers and a doubleword extension register)
Assembler syntax
Operation
F8.1.88 VMOVL
Assembler syntax
Operation
F8.1.89 VMOVN
Assembler syntax
Operation
F8.1.90 VMRS
Assembler syntax
Operation
F8.1.91 VMSR
Assembler syntax
Operation
F8.1.92 VMUL, VMULL (integer and polynomial)
Assembler syntax
Operation
F8.1.93 VMUL (floating-point)
Assembler syntax
Operation
F8.1.94 VMUL, VMULL (by scalar)
Assembler syntax
Operation
F8.1.95 VMVN (immediate)
Assembler syntax
Operation
Pseudo-instructions
F8.1.96 VMVN (register)
Assembler syntax
Operation
F8.1.97 VNEG
Assembler syntax
Operation
F8.1.98 VNMLA, VNMLS, VNMUL
Assembler syntax
Operation
F8.1.99 VORN (immediate)
F8.1.100 VORN (register)
Assembler syntax
Operation
F8.1.101 VORR (immediate)
Assembler syntax
Operation
Pseudo-instructions
F8.1.102 VORR (register)
Assembler syntax
Operation
F8.1.103 VPADAL
Assembler syntax
Operation
F8.1.104 VPADD (integer)
Assembler syntax
Operation
F8.1.105 VPADD (floating-point)
Assembler syntax
Operation
F8.1.106 VPADDL
Assembler syntax
Operation
F8.1.107 VPMAX, VPMIN (integer)
Assembler syntax
Operation
F8.1.108 VPMAX, VPMIN (floating-point)
Assembler syntax
Operation
F8.1.109 VPOP
Assembler syntax
Operation
F8.1.110 VPUSH
Assembler syntax
Operation
F8.1.111 VQABS
Assembler syntax
Operation
F8.1.112 VQADD
Assembler syntax
Operation
F8.1.113 VQDMLAL, VQDMLSL
Assembler syntax
Operation
F8.1.114 VQDMULH
Assembler syntax
Operation
F8.1.115 VQDMULL
Assembler syntax
Operation
F8.1.116 VQMOVN, VQMOVUN
Assembler syntax
Operation
F8.1.117 VQNEG
Assembler syntax
Operation
F8.1.118 VQRDMULH
Assembler syntax
Operation
F8.1.119 VQRSHL
Assembler syntax
Operation
F8.1.120 VQRSHRN, VQRSHRUN
Assembler syntax
Operation
Pseudo-instructions
F8.1.121 VQSHL (register)
Assembler syntax
Operation
F8.1.122 VQSHL, VQSHLU (immediate)
Assembler syntax
Operation
F8.1.123 VQSHRN, VQSHRUN
Assembler syntax
Operation
Pseudo-instructions
F8.1.124 VQSUB
Assembler syntax
Operation
F8.1.125 VRADDHN
Assembler syntax
Operation
F8.1.126 VRECPE
Assembler syntax
Operation
Newton-Raphson iteration
F8.1.127 VRECPS
Assembler syntax
Operation
Newton-Raphson iteration
F8.1.128 VREV16, VREV32, VREV64
Assembler syntax
Operation
F8.1.129 VRHADD
Assembler syntax
Operation
F8.1.130 VRINTA, VRINTN, VRINTP, VRINTM (Advanced SIMD)
Assembler syntax
Operation
F8.1.131 VRINTA, VRINTN, VRINTP, VRINTM (floating-point)
Assembler syntax
Operation
F8.1.132 VRINTX (Advanced SIMD)
Assembler syntax
Operation
F8.1.133 VRINTX (floating-point)
Assembler syntax
Operation
F8.1.134 VRINTZ (Advanced SIMD)
Assembler syntax
Operation
F8.1.135 VRINTZ, VRINTR (floating-point)
Assembler syntax
Operation
F8.1.136 VRSHL
Assembler syntax
Operation
F8.1.137 VRSHR
Assembler syntax
Operation
Pseudo-instructions
F8.1.138 VRSHRN
Assembler syntax
Operation
Pseudo-instructions
F8.1.139 VRSQRTE
Assembler syntax
Operation
Newton-Raphson iteration
F8.1.140 VRSQRTS
Assembler syntax
Operation
Newton-Raphson iteration
F8.1.141 VRSRA
Assembler syntax
Operation
F8.1.142 VRSUBHN
Assembler syntax
Operation
F8.1.143 VSEL
Assembler syntax
Operation
F8.1.144 VSHL (immediate)
Assembler syntax
Operation
F8.1.145 VSHL (register)
Assembler syntax
Operation
F8.1.146 VSHLL
Assembler syntax
Operation
F8.1.147 VSHR
Assembler syntax
Operation
Pseudo-instructions
F8.1.148 VSHRN
Assembler syntax
Operation
Pseudo-instructions
F8.1.149 VSLI
Assembler syntax
Operation
F8.1.150 VSQRT
Assembler syntax
Operation
F8.1.151 VSRA
Assembler syntax
Operation
F8.1.152 VSRI
Assembler syntax
Operation
F8.1.153 VST1 (multiple single elements)
Assembler syntax
Operation
F8.1.154 VST1 (single element from one lane)
Assembler syntax
Operation
F8.1.155 VST2 (multiple 2-element structures)
Assembler syntax
Operation
F8.1.156 VST2 (single 2-element structure from one lane)
Assembler syntax
Operation
F8.1.157 VST3 (multiple 3-element structures)
Assembler syntax
Operation
F8.1.158 VST3 (single 3-element structure from one lane)
Assembler syntax
Alignment
Operation
F8.1.159 VST4 (multiple 4-element structures)
Assembler syntax
Operation
F8.1.160 VST4 (single 4-element structure from one lane)
Assembler syntax
Operation
F8.1.161 VSTM
Assembler syntax
Operation
F8.1.162 VSTR
Assembler syntax
Operation
F8.1.163 VSUB (integer)
Assembler syntax
Operation
F8.1.164 VSUB (floating-point)
Assembler syntax
Operation
F8.1.165 VSUBHN
Assembler syntax
Operation
F8.1.166 VSUBL, VSUBW
Assembler syntax
Operation
F8.1.167 VSWP
Assembler syntax
Operation
F8.1.168 VTBL, VTBX
Assembler syntax
Operation
F8.1.169 VTRN
Assembler syntax
Operation
F8.1.170 VTST
Assembler syntax
Operation
F8.1.171 VUZP
Assembler syntax
Operation
Pseudo-instruction
F8.1.172 VZIP
Assembler syntax
Operation
Pseudo-instructions
Part G: The AArch32 System Level Architecture
G1: The AArch32 System Level Programmers’ Model
G1.1 About the AArch32 System level programmers’ model
G1.2 Exception levels
G1.2.1 Typical Exception level usage model
G1.3 Exception terminology
G1.3.1 Terminology for taking an exception
G1.3.2 Terminology for returning from an exception
G1.3.3 Exception levels
G1.3.4 Definition of a precise exception
G1.3.5 Definitions of synchronous and asynchronous exceptions
G1.4 Execution state
G1.4.1 About the AArch32 PE modes
G1.5 Instruction Set state
G1.6 Debug state
G1.7 Security state
G1.7.1 The ARMv8-A security model
The AArch32 security model, and execution privilege
Changing from Secure state to Non-secure state
G1.8 Virtualization
G1.8.1 The effect of implementing EL2 on the Exception model
Virtual interrupts
G1.9 AArch32 PE modes, general-purpose registers, and the PC
G1.9.1 AArch32 PE mode descriptions
Notes on the AArch32 PE modes
Hyp mode
Pseudocode details of mode operations
G1.9.2 AArch32 general-purpose registers, and the PC
Pseudocode details of general-purpose register and PC operations
G1.9.3 Program Status Registers (PSRs)
The Current Program Status Register (CPSR)
The Saved Program Status Registers (SPSRs)
Format of the CPSR and SPSRs
Accessing the execution state bits
Effects of EL3 and EL2 on the CPSR.{A, F} bits
Pseudocode details of PSR operations
G1.9.4 ELR_hyp
G1.10 Instruction set states
G1.10.1 Exceptions and instruction set state
G1.10.2 Unimplemented instruction sets
Trivial implementation of the Jazelle extension
G1.11 Handling exceptions that are taken to an Exception level using AArch32
G1.11.1 Exception vectors and the exception base address
The vector tables and exception offsets
G1.11.2 Exception priority order
Architectural requirements for taking asynchronous exceptions
G1.11.3 Overview of exception entry
Link values saved on exception entry
G1.11.4 PE mode for taking exceptions
Exceptions taken to Hyp mode
Security behavior in Exception levels using AArch32 when EL3 is using AArch64
Summary of the possible modes for taking each exception
G1.11.5 PE state on exception entry
Instruction set state on exception entry
CPSR.E bit value on exception entry
CPSR.{A, I, F, M} values on exception entry
G1.11.6 Routing general exceptions to EL2
Undefined Instruction exception, when HCR.TGE is set to 1
Supervisor Call exception, when HCR.TGE is set to 1
External abort, when HCR.TGE is set to 1
MMU fault, when HCR.TGE is set to 1
G1.11.7 Routing Debug exceptions to Hyp mode
G1.11.8 Exception return to an Exception level using AArch32
Exception return instructions
Alignment of exception returns
Illegal exception returns to AArch32 state
Illegal changes to the CPSR.M field
Legal exception returns that set CPSR.IL to 1
The Illegal Execution state exception
G1.11.9 Wait For Event and Send Event
WFE wake-up events
The Event Register
The Send Event instruction
The Wait For Event instruction
Pseudocode details of the Wait For Event lock mechanism
G1.11.10 Wait For Interrupt
Using WFI to indicate an idle state on bus interfaces
Pseudocode details of Wait For Interrupt
G1.12 Asynchronous exception behavior for exceptions taken from AArch32 state
G1.12.1 Virtual exceptions when an implementation includes EL2
Effects of the HCR.{AMO, IMO, FMO} bits
G1.12.2 Asynchronous exception routing controls
G1.12.3 Asynchronous exception masking controls
Asynchronous exception masking in an implementation that includes EL2 but not EL3
Asynchronous exception masking in an implementation that includes EL3 but not EL2
Asynchronous exception masking in an implementation that includes both EL2 and EL3
Summary of the asynchronous exception masking controls
G1.12.4 Asynchronous exception routing and masking with higher Exception levels using AArch64
Summary of physical interrupt routing
Summary of physical interrupt masking
G1.13 AArch32 state exception descriptions
G1.13.1 Reset
Pseudocode description of taking the Reset exception
G1.13.2 Undefined Instruction exception
Pseudocode description of taking the Undefined Instruction exception
Conditional execution of undefined instructions
Interaction of UNPREDICTABLE and UNDEFINED instruction behavior
G1.13.3 Hyp Trap exception
Pseudocode description of taking the Hyp Trap exception
G1.13.4 Supervisor Call (SVC) exception
Pseudocode description of taking the Supervisor Call exception
G1.13.5 Secure Monitor Call (SMC) exception
Pseudocode description of taking the Secure Monitor Call exception
G1.13.6 Hypervisor Call (HVC) exception
Pseudocode description of taking the Hypervisor Call exception
G1.13.7 Prefetch Abort exception
Pseudocode description of taking the Prefetch Abort exception
G1.13.8 Data Abort exception
Pseudocode description of taking the Data Abort exception
Effects of data-aborted instructions
The ARM abort model
G1.13.9 Virtual Abort exception
Pseudocode description of taking the Virtual Asynchronous Abort exception
G1.13.10 IRQ exception
Pseudocode description of taking the IRQ exception
G1.13.11 Virtual IRQ exception
Pseudocode description of taking the Virtual IRQ exception
G1.13.12 FIQ exception
Pseudocode description of taking the FIQ exception
G1.13.13 Virtual FIQ exception
Pseudocode description of taking the Virtual FIQ exception
G1.13.14 Additional pseudocode functions for exception handling
G1.14 The conceptual coprocessor interface and system control
G1.14.1 CP14 and CP15 system control registers
Access to CP14 and CP15 registers
G1.14.2 Access controls on CP10 and CP11
G1.15 Advanced SIMD and floating-point support
G1.15.1 Enabling Advanced SIMD and floating-point support
Summary of general controls of CP10 and CP11 functionality
Additional controls on Advanced SIMD functionality
Pseudocode details of enabling the Advanced SIMD and Floating-point Extensions
G1.15.2 Advanced SIMD and floating-point system registers
Register map of the Advanced SIMD and floating-point System registers
Accessing the Advanced SIMD and floating-point System registers
G1.15.3 Context switching when using Advanced SIMD and floating-point functionality
G1.15.4 Floating-point exception traps, serialization, and floating-point exception barriers
G1.16 AArch32 control of traps to the hypervisor
G1.16.1 General information about traps to the hypervisor
Hyp traps on instructions that fail their condition code check
Hyp traps on instructions that are UNPREDICTABLE
Hyp traps on instructions that are UNDEFINED
Traps of register access instructions
G1.16.2 Trapping ID mechanisms
ID group 0, Primary device identification registers
ID group 1, Implementation identification registers
ID group 2, Cache identification registers
ID group 3, Detailed feature identification registers
G1.16.3 Trapping accesses to lockdown, DMA, and TCM operations
G1.16.4 Trapping accesses to cache maintenance operations
G1.16.5 Trapping accesses to TLB maintenance operations
G1.16.6 Trapping accesses to the Auxiliary Control Register
G1.16.7 Trapping accesses to the Performance Monitors Extension
G1.16.8 Trapping use of the SMC instruction
G1.16.9 Trapping use of the WFI and WFE instructions
G1.16.10 Trapping accesses to the T32EE configuration registers
G1.16.11 Trapping accesses to coprocessors
Trapping of Advanced SIMD functionality
General trapping of coprocessor accesses
Trapping CPACR accesses
G1.16.12 Trapping writes to virtual memory control registers
G1.16.13 Generic trapping of accesses to CP15 system control registers
G1.16.14 Trapping CP14 accesses to debug registers
Trapping CP14 accesses to Debug ROM registers
Trapping CP14 accesses to OS-related debug registers
Trapping general CP14 accesses to debug registers
Permitted combinations of HDCR.{TDRA, TDOSA, TDA, TDE} bits
G1.16.15 Trapping CP14 accesses to trace registers
G1.16.16 Summary of trap controls
G2: The AArch32 System Level Memory Model
G2.1 About the memory system architecture
G2.1.1 Form of the memory system architecture
G2.1.2 Memory attributes
G2.2 Address space
G2.2.1 Address space overflow or underflow
Instruction address space overflow
Data address space overflow and underflow
G2.3 Mixed-endian support
G2.4 Cache support
G2.4.1 General behavior of the caches
G2.4.2 Cache identification
G2.4.3 Cacheability, cache allocation hints, and cache transient hints
G2.4.4 Behavior of caches at reset
G2.4.5 Cache enabling and disabling
G2.4.6 The ARMv8 cache maintenance functionality
Terms used in describing the maintenance instructions
The ARMv8 abstraction of the cache hierarchy
G2.4.7 Branch predictors
Requirements for branch predictor maintenance operations
Behavior of the branch predictors at reset
G2.4.8 Cache maintenance instructions
Instruction cache maintenance instructions (IC*)
Data cache maintenance instructions (DC*)
General requirements for the scope of cache and branch predictor maintenance instructions
Effects of instructions that operate to the point of coherency
Effects of instructions that do not operate to the point of coherency
Effects of virtualization and security on the cache maintenance instructions
Boundary conditions for cache maintenance instructions
Ordering of cache and branch predictor maintenance instructions
Performing cache maintenance instructions
G2.4.9 Cache lockdown
The interaction of cache lockdown with cache maintenance instructions
G2.4.10 System level caches
G2.5 ARMv8 CP15 register support for IMPLEMENTATION DEFINED features
G2.6 External aborts
G2.6.1 External abort on instruction fetch
G2.6.2 External abort on data read or write
G2.6.3 Provision for classification of external aborts
G2.6.4 Parity error reporting
G2.7 Memory barrier instructions
G2.7.1 EL2 control of the shareability of data barrier instructions executed at EL0 or EL1
G2.8 Pseudocode details of general memory system instructions
G2.8.1 Memory data type definitions
G2.8.2 Basic memory access
G2.8.3 Aligned memory access
G2.8.4 Unaligned memory access
G2.8.5 Exclusive monitors operations
G2.8.6 Access permission checking
G2.8.7 Abort exceptions
G2.8.8 Memory barriers
G3: The AArch32 Virtual Memory System Architecture
G3.1 Execution privilege, Exception levels, and AArch32 Privilege levels
G3.2 About VMSAv8-32
G3.2.1 Address types used in a VMSAv8-32 description
G3.2.2 Address spaces in VMSAv8-32
G3.2.3 About address translation for VMSAv8-32
G3.2.4 Organization of this chapter
G3.3 The effects of disabling address translation stages on VMSAv8-32 behavior
G3.3.1 VMSAv8-32 behavior when stage 1 address translation is disabled
Effect of the HCR.DC bit
Effect of disabling translation on maintenance and address translation operations
G3.3.2 VMSAv8-32 behavior when stage 2 address translation is disabled
G3.3.3 Behavior of instruction fetches when all associated address translations are disabled
G3.3.4 Enabling stages of address translation
G3.4 Translation tables
G3.4.1 Translation table walks for memory accesses using VMSAv8-32 translation regimes
G3.4.2 Information returned by a translation table lookup
G3.4.3 Determining the translation table base address in the VMSAv8-32 translation regimes
G3.4.4 Control of translation table walks on a TLB miss
G3.4.5 Access to the Secure or Non-secure physical address map
Secure and Non-secure address spaces
G3.5 The VMSAv8-32 Short-descriptor translation table format
G3.5.1 VMSAv8-32 Short-descriptor translation table format descriptors
Short-descriptor translation table first-level descriptor formats
Short-descriptor translation table second-level descriptor formats
Additional requirements for Short-descriptor format translation tables
G3.5.2 Memory attributes in the VMSAv8-32 Short-descriptor translation table format descriptors
G3.5.3 Control of Secure or Non-secure memory access, VMSAv8-32 Short-descriptor format
G3.5.4 Selecting between TTBR0 and TTBR1, VMSAv8-32 Short-descriptor translation table format
G3.5.5 Translation table walks, when using the VMSAv8-32 Short-descriptor translation table format
Reading a first-level translation table
The full translation flow for Sections, Supersections, Small pages and Large pages
G3.6 The VMSAv8-32 Long-descriptor translation table format
G3.6.1 Overview of VMSAv8-32 address translation using Long-descriptor translation tables
G3.6.2 VMSAv8-32 Long-descriptor translation table format descriptors
VMSAv8-32 Long-descriptor first-level and second-level descriptor formats
VMSAv8-32 Long-descriptor translation table third-level descriptor formats
G3.6.3 Memory attributes in the VMSAv8-32 Long-descriptor translation table format descriptors
Next-level attributes in VMSAv8-32 Long-descriptor stage 1 Table descriptors
Attribute fields in VMSAv8-32 Long-descriptor stage 1 Block and Page descriptors
Attribute fields in VMSAv8-32 Long-descriptor stage 2 Block and Page descriptors
G3.6.4 Control of Secure or Non-secure memory access, VMSAv8-32 Long-descriptor format
Hierarchical control of Secure or Non-secure memory accesses, Long-descriptor format
G3.6.5 Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format
Possible translation table registers programming errors
G3.6.6 VMSAv8-32 Long-descriptor translation table format address lookup levels
Use of concatenated translation tables for stage 2 translations
G3.6.7 Translation table walks, when using the VMSAv8-32 Long-descriptor translation table format
Determining the required first lookup level for stage 1 translations
Determining the required first lookup level for stage 2 translations
Full translation flows for VMSAv8-32 Long-descriptor format translation tables
G3.7 Memory access control
G3.7.1 Access permissions
AP[2:1] access permissions model
AP[2:0] access permissions control, Short-descriptor format only
G3.7.2 Execute-never restrictions on instruction fetching
Hierarchical control of instruction fetching, Long-descriptor format
Restriction on Secure instruction fetch
Preventing execution from writable locations
G3.7.3 Domains, Short-descriptor format only
G3.7.4 The Access flag
Software management of the Access flag
G3.7.5 Hyp mode control of Non-secure access permissions
G3.8 Memory region attributes
G3.8.1 Overview of memory region attributes for stage 1 translations
G3.8.2 Short-descriptor format memory region attributes, without TEX remap
Cacheable memory attributes, without TEX remap
Shareability and the S bit, without TEX remap
G3.8.3 Short-descriptor format memory region attributes, with TEX remap
Shareability and the S bit, with TEX remap
Interpretation of the NOSn fields in the PRRR, with TEX remap
SCTLR.TRE, SCTLR.M, and the effect of the TEX remap registers
The OS managed translation table bits
The effect of EL3 on TEX remap
G3.8.4 VMSAv8-32 Long-descriptor format memory region attributes
Shareability, Long-descriptor format
Other fields in the Long-descriptor translation table format descriptors
G3.8.5 EL2 control of Non-secure memory region attributes
Combining the memory type attribute
Combining the cacheability attribute
Combining the shareability attribute
G3.9 Translation Lookaside Buffers (TLBs)
G3.9.1 Global and process-specific translation table entries
G3.9.2 TLB matching
G3.9.3 TLB behavior at reset
G3.9.4 TLB lockdown
G3.9.5 TLB conflict aborts
G3.10 TLB maintenance requirements
G3.10.1 General TLB maintenance requirements
The interaction of TLB lockdown with TLB maintenance operations
TLB maintenance operations and the memory order model
G3.10.2 Maintenance requirements on changing System register values
Changing the Access flag enable
Changing HCR.PTW
Changing the current Translation table format
G3.10.3 Atomicity of register changes on changing virtual machine
G3.10.4 Synchronization of changes of ASID and TTBR
G3.10.5 The scope of TLB maintenance operations
EL2 upgrading of TLB maintenance operations
G3.11 Caches in VMSAv8-32
G3.11.1 Data and unified caches
G3.11.2 Instruction caches
PIPT instruction caches
VIPT instruction caches
ASID and VMID tagged VIVT instruction caches
IVIPT architecture Extension
G3.11.3 Cache maintenance requirement created by changing translation table attributes
G3.12 VMSAv8-32 memory aborts
G3.12.1 Routing of aborts taken to AArch32 state
G3.12.2 VMSAv8-32 MMU fault terminology
G3.12.3 The MMU fault-checking sequence
Stage 2 fault on a stage 1 translation table walk
G3.12.4 Alignment faults
G3.12.5 MMU faults in AArch32 state
Translation fault
Address size fault
Access flag fault
Domain fault, Short-descriptor format translation tables only
Permission fault
G3.12.6 External abort on a translation table walk
Behavior of external aborts on a translation table walk caused by address translation operations
G3.12.7 Prioritization of aborts
Alignment faults caused by accessing Device memory types
G3.13 Exception reporting in a VMSAv8-32 implementation
G3.13.1 About exception reporting
G3.13.2 Reporting exceptions taken to PL1 modes
Registers used for reporting exceptions taken to PL1 modes
Data Abort exceptions, taken to a PL1 mode
Prefetch Abort exceptions, taken to a PL1 mode
G3.13.3 Fault reporting in PL1 modes
Reporting of External aborts taken from Non-secure state to Monitor mode
PL1 fault reporting with the Short-descriptor translation table format
PL1 fault reporting with the Long-descriptor translation table format
Reserved encodings in the IFSR and DFSR encodings tables
G3.13.4 Summary of register updates on faults taken to PL1 modes
G3.13.5 Reporting exceptions taken to Hyp mode
Registers used for reporting exceptions taken to Hyp mode
Memory fault reporting in Hyp mode
G3.13.6 Use of the HSR
HSR exception classes and associated ISS encodings
G3.13.7 Summary of register updates on exceptions taken to Hyp mode
Classification of MMU faults taken to Hyp mode
G3.14 Virtual Address to Physical Address translation operations
G3.14.1 Naming of the address translation operations, and operation summary
Address translation stage 1, current security state
Address translation stages 1 and 2, Non-secure state only
Address translation stage 1, Hyp mode
G3.14.2 Encoding and availability of the address translation operations
G3.14.3 Determining the PAR format
G3.14.4 Handling of faults and aborts during an address translation operation
MMU fault on an address translation operation
External abort during an address translation operation
Stage 2 fault on a current state address translation operation
G3.15 About the System registers for VMSAv8-32
G3.15.1 About System register accesses
Ordering of reads of System registers
Accessing 32-bit control registers
Accessing 64-bit control registers
G3.15.2 General behavior of System registers
Read-only bits in read/write registers
UNPREDICTABLE and UNDEFINED behavior for CP14 and CP15 accesses
Read-only and write-only register encodings
Reset behavior of CP14 and CP15 registers
G3.15.3 Classification of System registers
Banked System registers
Restricted access System registers
Configurable access System registers
EL2-mode System registers
Common System registers
Secure CP15 registers
The CP15SDISABLE input
Access to registers from Monitor mode
G3.15.4 Synchronization of changes to System registers
Registers with some architectural guarantee of ordering or observability
Definitions of direct and indirect reads and writes and their side-effects
G3.15.5 Meaning of fixed bit values in register diagrams
G3.16 Organization of the CP14 registers in VMSAv8-32
G3.16.1 CP14 interface instruction arguments
G3.17 Organization of the CP15 registers in VMSAv8-32
G3.17.1 CP15 32-bit register summary by coprocessor register number, CRn
VMSAv8-32 CP15 c0 register summary
VMSAv8-32 CP15 c1 register summary
VMSAv8-32 CP15 c2 and c3 register summary
VMSAv8-32 CP15 c4 register summary
VMSAv8-32 CP15 c5 and c6 register summary
VMSAv8-32 CP15 c7 register summary
VMSAv8-32 CP15 c8 register summary
VMSAv8-32 CP15 c9 register summary
VMSAv8-32 CP15 c10 register summary
VMSAv8-32 CP15 c11 register summary
VMSAv8-32 CP15 c12 register summary
VMSAv8-32 CP15 c13 register summary
VMSAv8-32 CP15 c14 register summary
VMSAv8-32 CP15 c15 register summary
G3.17.2 Full list of VMSAv8-32 CP15 registers, by coprocessor register number
G3.17.3 Views of the CP15 registers
EL0 views of the CP15 registers
EL1 views of the CP15 registers
Non-secure EL2 view of the CP15 registers
G3.18 Functional grouping of VMSAv8-32 System registers
G3.18.1 Identification registers, functional group
The CPUID identification scheme
G3.18.2 Other system control registers, functional group
G3.18.3 Virtual memory control registers, functional group
G3.18.4 Virtualization registers, functional group
G3.18.5 Security registers, functional group
G3.18.6 Exception and fault handling registers, functional group
G3.18.7 Reset management registers, functional group
G3.18.8 Thread and process ID registers, functional group
G3.18.9 Cache maintenance operations, functional group
G3.18.10 TLB maintenance operations, functional group
G3.18.11 Address translation operations, functional group
G3.18.12 Lockdown, DMA, and TCM features, functional group
G3.18.13 Performance Monitors Extension registers, functional group
IMPLEMENTATION DEFINED performance monitors
G3.18.14 Generic Timer Extension registers, functional group
G3.18.15 Generic Interrupt Controller CPU interface registers, functional group
G3.18.16 Legacy feature registers, functional group
G3.18.17 IMPLEMENTATION DEFINED registers, functional group
G3.18.18 Floating-point registers, functional group
G3.18.19 Debug registers, functional group
Debug CP14 System register numbers
G3.19 Pseudocode details of VMSAv8-32 memory system operations
G3.19.1 Alignment fault
G3.19.2 Address translation
Address translation when the stage 1 address translation is disabled
G3.19.3 Domain checking
G3.19.4 TLB operations
G3.19.5 Translation table walk
Translation table walk using the Short-descriptor translation table format for stage 1
Translation table walk using the Long-descriptor translation table format for stage 1
Stage 2 translation table walk
G3.19.6 Reporting syndrome information
G3.19.7 Calling the hypervisor
G3.19.8 Memory access decode when TEX remap is enabled
G4: AArch32 System Register Descriptions
G4.1 About the AArch32 System registers
G4.2 General system control registers
G4.2.1 ACTLR, Auxiliary Control Register
Accessing the ACTLR:
G4.2.2 ADFSR, Auxiliary Data Fault Status Register
Accessing the ADFSR:
G4.2.3 AIDR, Auxiliary ID Register
Accessing the AIDR:
G4.2.4 AIFSR, Auxiliary Instruction Fault Status Register
Accessing the AIFSR:
G4.2.5 AMAIR0, Auxiliary Memory Attribute Indirection Register 0
Accessing the AMAIR0:
G4.2.6 AMAIR1, Auxiliary Memory Attribute Indirection Register 1
Accessing the AMAIR1:
G4.2.7 APSR, Application Program Status Register
G4.2.8 ATS12NSOPR, Address Translate Stages 1 and 2 Non-secure Only PL1 Read
Performing the ATS12NSOPR operation:
G4.2.9 ATS12NSOPW, Address Translate Stages 1 and 2 Non-secure Only PL1 Write
Performing the ATS12NSOPW operation:
G4.2.10 ATS12NSOUR, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
Performing the ATS12NSOUR operation:
G4.2.11 ATS12NSOUW, Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
Performing the ATS12NSOUW operation:
G4.2.12 ATS1CPR, Address Translate Stage 1 Current state PL1 Read
Performing the ATS1CPR operation:
G4.2.13 ATS1CPW, Address Translate Stage 1 Current state PL1 Write
Performing the ATS1CPW operation:
G4.2.14 ATS1CUR, Address Translate Stage 1 Current state Unprivileged Read
Performing the ATS1CUR operation:
G4.2.15 ATS1CUW, Address Translate Stage 1 Current state Unprivileged Write
Performing the ATS1CUW operation:
G4.2.16 ATS1HR, Address Translate Stage 1 Hyp mode Read
Performing the ATS1HR operation:
G4.2.17 ATS1HW, Address Translate Stage 1 Hyp mode Write
Performing the ATS1HW operation:
G4.2.18 BPIALL, Branch Predictor Invalidate All
Performing the BPIALL operation:
G4.2.19 BPIALLIS, Branch Predictor Invalidate All, Inner Shareable
Performing the BPIALLIS operation:
G4.2.20 BPIMVA, Branch Predictor Invalidate VA
Performing the BPIMVA operation:
G4.2.21 CCSIDR, Current Cache Size ID Register
Accessing the CCSIDR:
G4.2.22 CLIDR, Cache Level ID Register
Accessing the CLIDR:
G4.2.23 CONTEXTIDR, Context ID Register
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the CONTEXTIDR:
G4.2.24 CP15DMB, CP15 Data Memory Barrier operation
Performing the CP15DMB operation:
G4.2.25 CP15DSB, CP15 Data Synchronization Barrier operation
Performing the CP15DSB operation:
G4.2.26 CP15ISB, CP15 Instruction Synchronization Barrier operation
Performing the CP15ISB operation:
G4.2.27 CPACR, Architectural Feature Access Control Register
Accessing the CPACR:
G4.2.28 CPSR, Current Program Status Register
G4.2.29 CSSELR, Cache Size Selection Register
Accessing the CSSELR:
G4.2.30 CTR, Cache Type Register
Accessing the CTR:
G4.2.31 DACR, Domain Access Control Register
Accessing the DACR:
G4.2.32 DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC
Performing the DCCIMVAC operation:
G4.2.33 DCCISW, Data Cache line Clean and Invalidate by Set/Way
Performing the DCCISW operation:
G4.2.34 DCCMVAC, Data Cache line Clean by VA to PoC
Performing the DCCMVAC operation:
G4.2.35 DCCMVAU, Data Cache line Clean by VA to PoU
Performing the DCCMVAU operation:
G4.2.36 DCCSW, Data Cache line Clean by Set/Way
Performing the DCCSW operation:
G4.2.37 DCIMVAC, Data Cache line Invalidate by VA to PoC
Performing the DCIMVAC operation:
G4.2.38 DCISW, Data Cache line Invalidate by Set/Way
Performing the DCISW operation:
G4.2.39 DFAR, Data Fault Address Register
Accessing the DFAR:
G4.2.40 DFSR, Data Fault Status Register
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the DFSR:
G4.2.41 DTLBIALL, Data TLB Invalidate All entries
Performing the DTLBIALL operation:
G4.2.42 DTLBIASID, Data TLB Invalidate by ASID match
Performing the DTLBIASID operation:
G4.2.43 DTLBIMVA, Data TLB Invalidate entry by VA
Performing the DTLBIMVA operation:
G4.2.44 ELR_hyp, Exception Link Register (Hyp mode)
Accessing the ELR_hyp:
G4.2.45 FCSEIDR, FCSE Process ID register
Accessing the FCSEIDR:
G4.2.46 FPEXC, Floating-Point Exception Control register
Accessing the FPEXC:
G4.2.47 FPSCR, Floating-Point Status and Control Register
Accessing the FPSCR:
G4.2.48 FPSID, Floating-Point System ID register
Accessing the FPSID:
G4.2.49 HACR, Hyp Auxiliary Configuration Register
Accessing the HACR:
G4.2.50 HACTLR, Hyp Auxiliary Control Register
Accessing the HACTLR:
G4.2.51 HADFSR, Hyp Auxiliary Data Fault Status Register
Accessing the HADFSR:
G4.2.52 HAIFSR, Hyp Auxiliary Instruction Fault Status Register
Accessing the HAIFSR:
G4.2.53 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0
Accessing the HAMAIR0:
G4.2.54 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1
Accessing the HAMAIR1:
G4.2.55 HCPTR, Hyp Architectural Feature Trap Register
Accessing the HCPTR:
G4.2.56 HCR, Hyp Configuration Register
Accessing the HCR:
G4.2.57 HCR2, Hyp Configuration Register 2
Accessing the HCR2:
G4.2.58 HDFAR, Hyp Data Fault Address Register
Accessing the HDFAR:
G4.2.59 HIFAR, Hyp Instruction Fault Address Register
Accessing the HIFAR:
G4.2.60 HMAIR0, Hyp Memory Attribute Indirection Register 0
When TTBCR.EAE==1:
Accessing the HMAIR0:
G4.2.61 HMAIR1, Hyp Memory Attribute Indirection Register 1
When TTBCR.EAE==1:
Accessing the HMAIR1:
G4.2.62 HPFAR, Hyp IPA Fault Address Register
Accessing the HPFAR:
G4.2.63 HRMR, Hyp Reset Management Register
When EL2 implemented, EL3 not implemented:
Accessing the HRMR:
G4.2.64 HSCTLR, Hyp System Control Register
Accessing the HSCTLR:
G4.2.65 HSR, Hyp Syndrome Register
Accessing the HSR:
G4.2.66 HSTR, Hyp System Trap Register
Accessing the HSTR:
G4.2.67 HTCR, Hyp Translation Control Register
Accessing the HTCR:
G4.2.68 HTPIDR, Hyp Thread Pointer / ID Register
Accessing the HTPIDR:
G4.2.69 HTTBR, Hyp Translation Table Base Register
Accessing the HTTBR:
G4.2.70 HVBAR, Hyp Vector Base Address Register
Accessing the HVBAR:
G4.2.71 ICIALLU, Instruction Cache Invalidate All to PoU
Performing the ICIALLU operation:
G4.2.72 ICIALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable
Performing the ICIALLUIS operation:
G4.2.73 ICIMVAU, Instruction Cache line Invalidate by VA to PoU
Performing the ICIMVAU operation:
G4.2.74 ID_AFR0, Auxiliary Feature Register 0
Accessing the ID_AFR0:
G4.2.75 ID_DFR0, Debug Feature Register 0
Accessing the ID_DFR0:
G4.2.76 ID_ISAR0, Instruction Set Attribute Register 0
Accessing the ID_ISAR0:
G4.2.77 ID_ISAR1, Instruction Set Attribute Register 1
Accessing the ID_ISAR1:
G4.2.78 ID_ISAR2, Instruction Set Attribute Register 2
Accessing the ID_ISAR2:
G4.2.79 ID_ISAR3, Instruction Set Attribute Register 3
Accessing the ID_ISAR3:
G4.2.80 ID_ISAR4, Instruction Set Attribute Register 4
Accessing the ID_ISAR4:
G4.2.81 ID_ISAR5, Instruction Set Attribute Register 5
Accessing the ID_ISAR5:
G4.2.82 ID_MMFR0, Memory Model Feature Register 0
Accessing the ID_MMFR0:
G4.2.83 ID_MMFR1, Memory Model Feature Register 1
Accessing the ID_MMFR1:
G4.2.84 ID_MMFR2, Memory Model Feature Register 2
Accessing the ID_MMFR2:
G4.2.85 ID_MMFR3, Memory Model Feature Register 3
Accessing the ID_MMFR3:
G4.2.86 ID_PFR0, Processor Feature Register 0
Accessing the ID_PFR0:
G4.2.87 ID_PFR1, Processor Feature Register 1
Accessing the ID_PFR1:
G4.2.88 IFAR, Instruction Fault Address Register
Accessing the IFAR:
G4.2.89 IFSR, Instruction Fault Status Register
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the IFSR:
G4.2.90 ISR, Interrupt Status Register
Accessing the ISR:
G4.2.91 ITLBIALL, Instruction TLB Invalidate All entries
Performing the ITLBIALL operation:
G4.2.92 ITLBIASID, Instruction TLB Invalidate by ASID match
Performing the ITLBIASID operation:
G4.2.93 ITLBIMVA, Instruction TLB Invalidate entry by VA
Performing the ITLBIMVA operation:
G4.2.94 JIDR, Jazelle ID Register
Accessing the JIDR:
G4.2.95 JMCR, Jazelle Main Configuration Register
Accessing the JMCR:
G4.2.96 JOSCR, Jazelle OS Control Register
Accessing the JOSCR:
G4.2.97 MAIR0, Memory Attribute Indirection Register 0
When TTBCR.EAE==1:
Accessing the MAIR0:
G4.2.98 MAIR1, Memory Attribute Indirection Register 1
When TTBCR.EAE==1:
Accessing the MAIR1:
G4.2.99 MIDR, Main ID Register
Accessing the MIDR:
G4.2.100 MPIDR, Multiprocessor Affinity Register
Accessing the MPIDR:
G4.2.101 MVBAR, Monitor Vector Base Address Register
Accessing the MVBAR:
G4.2.102 MVFR0, Media and VFP Feature Register 0
Accessing the MVFR0:
G4.2.103 MVFR1, Media and VFP Feature Register 1
Accessing the MVFR1:
G4.2.104 MVFR2, Media and VFP Feature Register 2
Accessing the MVFR2:
G4.2.105 NMRR, Normal Memory Remap Register
When TTBCR.EAE==0:
Accessing the NMRR:
G4.2.106 NSACR, Non-Secure Access Control Register
Accessing the NSACR:
G4.2.107 PAR, Physical Address Register
When TTBCR.EAE==0, PAR.F==0:
When TTBCR.EAE==0, PAR.F==1:
When TTBCR.EAE==1, PAR.F==0:
When TTBCR.EAE==1, PAR.F==1:
Accessing the PAR:
G4.2.108 PRRR, Primary Region Remap Register
When TTBCR.EAE==0:
Accessing the PRRR:
G4.2.109 REVIDR, Revision ID Register
Accessing the REVIDR:
G4.2.110 RMR (at EL1), Reset Management Register
When EL2 and EL3 not implemented:
Accessing the RMR (at EL1):
G4.2.111 RMR (at EL3), Reset Management Register
When EL3 implemented:
Accessing the RMR (at EL3):
G4.2.112 RVBAR, Reset Vector Base Address Register
Accessing the RVBAR:
G4.2.113 SCR, Secure Configuration Register
Accessing the SCR:
G4.2.114 SCTLR, System Control Register
Accessing the SCTLR:
G4.2.115 SPSR, Saved Program Status Register
G4.2.116 SPSR_abt, Saved Program Status Register (Abort mode)
Accessing the SPSR_abt:
G4.2.117 SPSR_fiq, Saved Program Status Register (FIQ mode)
Accessing the SPSR_fiq:
G4.2.118 SPSR_hyp, Saved Program Status Register (Hyp mode)
Accessing the SPSR_hyp:
G4.2.119 SPSR_irq, Saved Program Status Register (IRQ mode)
Accessing the SPSR_irq:
G4.2.120 SPSR_mon, Saved Program Status Register (Monitor mode)
Accessing the SPSR_mon:
G4.2.121 SPSR_svc, Saved Program Status Register (Sup. Call mode)
Accessing the SPSR_svc:
G4.2.122 SPSR_und, Saved Program Status Register (Undefined mode)
Accessing the SPSR_und:
G4.2.123 TCMTR, TCM Type Register
When TCMTR.Format==0b000:
When TCMTR.Format==0b100:
Accessing the TCMTR:
G4.2.124 TEECR, T32EE Configuration Register
Accessing the TEECR:
G4.2.125 TEEHBR, T32EE Handler Base Register
Accessing the TEEHBR:
G4.2.126 TLBIALL, TLB Invalidate All entries
Performing the TLBIALL operation:
G4.2.127 TLBIALLH, TLB Invalidate All entries, Hyp mode
Performing the TLBIALLH operation:
G4.2.128 TLBIALLHIS, TLB Invalidate All entries, Hyp mode, Inner Shareable
Performing the TLBIALLHIS operation:
G4.2.129 TLBIALLIS, TLB Invalidate All entries, Inner Shareable
Performing the TLBIALLIS operation:
G4.2.130 TLBIALLNSNH, TLB Invalidate All entries, Non-Secure Non-Hyp
Performing the TLBIALLNSNH operation:
G4.2.131 TLBIALLNSNHIS, TLB Invalidate All entries, Non-Secure Non-Hyp, Inner Shareable
Performing the TLBIALLNSNHIS operation:
G4.2.132 TLBIASID, TLB Invalidate entry by ASID match
Performing the TLBIASID operation:
G4.2.133 TLBIASIDIS, TLB Invalidate entry by ASID match, Inner Shareable
Performing the TLBIASIDIS operation:
G4.2.134 TLBIIPAS2, TLB Invalidate entry by Intermediate Physical Address, Stage 2
Performing the TLBIIPAS2 operation:
G4.2.135 TLBIIPAS2IS, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Inner Shareable
Performing the TLBIIPAS2IS operation:
G4.2.136 TLBIIPAS2L, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level
Performing the TLBIIPAS2L operation:
G4.2.137 TLBIIPAS2LIS, TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
Performing the TLBIIPAS2LIS operation:
G4.2.138 TLBIMVA, TLB Invalidate entry by VA
Performing the TLBIMVA operation:
G4.2.139 TLBIMVAA, TLB Invalidate entry by VA, All ASID
Performing the TLBIMVAA operation:
G4.2.140 TLBIMVAAIS, TLB Invalidate entry by VA, All ASID, Inner Shareable
Performing the TLBIMVAAIS operation:
G4.2.141 TLBIMVAAL, TLB Invalidate entry by VA, All ASID, Last level
Performing the TLBIMVAAL operation:
G4.2.142 TLBIMVAALIS, TLB Invalidate entry by VA, All ASID, Last level, Inner Shareable
Performing the TLBIMVAALIS operation:
G4.2.143 TLBIMVAH, TLB Invalidate entry by VA, Hyp mode
Performing the TLBIMVAH operation:
G4.2.144 TLBIMVAHIS, TLB Invalidate entry by VA, Hyp mode, Inner Shareable
Performing the TLBIMVAHIS operation:
G4.2.145 TLBIMVAIS, TLB Invalidate entry by VA, Inner Shareable
Performing the TLBIMVAIS operation:
G4.2.146 TLBIMVAL, TLB Invalidate entry by VA, Last level
Performing the TLBIMVAL operation:
G4.2.147 TLBIMVALH, TLB Invalidate entry by VA, Last level, Hyp mode
Performing the TLBIMVALH operation:
G4.2.148 TLBIMVALHIS, TLB Invalidate entry by VA, Last level, Hyp mode, Inner Shareable
Performing the TLBIMVALHIS operation:
G4.2.149 TLBIMVALIS, TLB Invalidate entry by VA, Last level, Inner Shareable
Performing the TLBIMVALIS operation:
G4.2.150 TLBTR, TLB Type Register
Accessing the TLBTR:
G4.2.151 TPIDRPRW, Thread Pointer / ID Register, Privileged Read-Write
Accessing the TPIDRPRW:
G4.2.152 TPIDRURO, Thread Pointer / ID Register, Unprivileged Read-Only
Accessing the TPIDRURO:
G4.2.153 TPIDRURW, Thread Pointer / ID Register, Unprivileged Read-Write
Accessing the TPIDRURW:
G4.2.154 TTBCR, Translation Table Base Control Register
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the TTBCR:
G4.2.155 TTBR0, Translation Table Base Register 0
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the TTBR0:
G4.2.156 TTBR1, Translation Table Base Register 1
When TTBCR.EAE==0:
When TTBCR.EAE==1:
Accessing the TTBR1:
G4.2.157 VBAR, Vector Base Address Register
Accessing the VBAR:
G4.2.158 VMPIDR, Virtualization Multiprocessor ID Register
Accessing the VMPIDR:
G4.2.159 VPIDR, Virtualization Processor ID Register
Accessing the VPIDR:
G4.2.160 VTCR, Virtualization Translation Control Register
Accessing the VTCR:
G4.2.161 VTTBR, Virtualization Translation Table Base Register
Accessing the VTTBR:
G4.3 Debug registers
G4.3.1 DBGAUTHSTATUS, Debug Authentication Status register
Accessing the DBGAUTHSTATUS:
G4.3.2 DBGBCR, Debug Breakpoint Control Registers, n = 0 - 15
Accessing the DBGBCR:
G4.3.3 DBGBVR, Debug Breakpoint Value Registers, n = 0 - 15
When DBGBCR.BT==0b0x0x:
When DBGBCR.BT==0b1x0x:
When DBGBCR.BT==0xxx1x:
Accessing the DBGBVR:
G4.3.4 DBGBXVR, Debug Breakpoint Extended Value Registers, n = 0 - 15
When DBGBCR.BT==0b0xxx:
When DBGBCR.BT==0b1xxx and EL2 implemented:
Accessing the DBGBXVR:
G4.3.5 DBGCLAIMCLR, Debug Claim Tag Clear register
Accessing the DBGCLAIMCLR:
G4.3.6 DBGCLAIMSET, Debug Claim Tag Set register
Accessing the DBGCLAIMSET:
G4.3.7 DBGDCCINT, DCC Interrupt Enable Register
Accessing the DBGDCCINT:
G4.3.8 DBGDEVID, Debug Device ID register 0
Accessing the DBGDEVID:
G4.3.9 DBGDEVID1, Debug Device ID register 1
Accessing the DBGDEVID1:
G4.3.10 DBGDEVID2, Debug Device ID register 2
Accessing the DBGDEVID2:
G4.3.11 DBGDIDR, Debug ID Register
Accessing the DBGDIDR:
G4.3.12 DBGDRAR, Debug ROM Address Register
When accessing the 32-bit version:
When accessing the 64-bit version:
Accessing the DBGDRAR:
G4.3.13 DBGDSAR, Debug Self Address Register
When accessing the 32-bit version:
When accessing the 64-bit version:
Accessing the DBGDSAR:
G4.3.14 DBGDSCRext, Debug Status and Control Register, External View
Accessing the DBGDSCRext:
G4.3.15 DBGDSCRint, Debug Status and Control Register, Internal View
Accessing the DBGDSCRint:
G4.3.16 DBGDTRRXext, Debug Data Transfer Register, Receive, External View
Accessing the DBGDTRRXext:
G4.3.17 DBGDTRRXint, Debug Data Transfer Register, Receive, Internal View
Accessing the DBGDTRRXint:
G4.3.18 DBGDTRTXext, Debug Data Transfer Register, Transmit, External View
Accessing the DBGDTRTXext:
G4.3.19 DBGDTRTXint, Debug Data Transfer Register, Transmit, Internal View
Accessing the DBGDTRTXint:
G4.3.20 DBGOSDLR, Debug OS Double Lock Register
Accessing the DBGOSDLR:
G4.3.21 DBGOSECCR, Debug OS Lock Exception Catch Control Register
When OSLSR.OSLK==1:
Accessing the DBGOSECCR:
G4.3.22 DBGOSLAR, Debug OS Lock Access Register
Accessing the DBGOSLAR:
G4.3.23 DBGOSLSR, Debug OS Lock Status Register
Accessing the DBGOSLSR:
G4.3.24 DBGPRCR, Debug Power Control Register
Accessing the DBGPRCR:
G4.3.25 DBGVCR, Debug Vector Catch Register
When EL3 implemented and using AArch32:
When EL3 implemented and using AArch64:
When EL3 not implemented:
Accessing the DBGVCR:
G4.3.26 DBGWCR, Debug Watchpoint Control Registers, n = 0 - 15
Accessing the DBGWCR:
G4.3.27 DBGWFAR, Debug Watchpoint Fault Address Register
Accessing the DBGWFAR:
G4.3.28 DBGWVR, Debug Watchpoint Value Registers, n = 0 - 15
Accessing the DBGWVR:
G4.3.29 DLR, Debug Link Register
Accessing the DLR:
G4.3.30 DSPSR, Debug Saved Program Status Register
Accessing the DSPSR:
G4.3.31 HDCR, Hyp Debug Control Register
Accessing the HDCR:
G4.3.32 SDCR, Secure Debug Configuration Register
Accessing the SDCR:
G4.3.33 SDER, Secure Debug Enable Register
Accessing the SDER:
G4.4 Performance Monitors registers
G4.4.1 PMCCFILTR, Performance Monitors Cycle Count Filter Register
Accessing the PMCCFILTR:
G4.4.2 PMCCNTR, Performance Monitors Cycle Count Register
When accessing as a 32-bit register:
When accessing as a 64-bit register:
Accessing the PMCCNTR:
G4.4.3 PMCEID0, Performance Monitors Common Event Identification register 0
Accessing the PMCEID0:
G4.4.4 PMCEID1, Performance Monitors Common Event Identification register 1
Accessing the PMCEID1:
G4.4.5 PMCNTENCLR, Performance Monitors Count Enable Clear register
Accessing the PMCNTENCLR:
G4.4.6 PMCNTENSET, Performance Monitors Count Enable Set register
Accessing the PMCNTENSET:
G4.4.7 PMCR, Performance Monitors Control Register
Accessing the PMCR:
G4.4.8 PMEVCNTR, Performance Monitors Event Count Registers, n = 0 - 30
Accessing the PMEVCNTR:
G4.4.9 PMEVTYPER, Performance Monitors Event Type Registers, n = 0 - 30
Accessing the PMEVTYPER:
G4.4.10 PMINTENCLR, Performance Monitors Interrupt Enable Clear register
Accessing the PMINTENCLR:
G4.4.11 PMINTENSET, Performance Monitors Interrupt Enable Set register
Accessing the PMINTENSET:
G4.4.12 PMOVSR, Performance Monitors Overflow Flag Status Register
Accessing the PMOVSR:
G4.4.13 PMOVSSET, Performance Monitors Overflow Flag Status Set register
Accessing the PMOVSSET:
G4.4.14 PMSELR, Performance Monitors Event Counter Selection Register
Accessing the PMSELR:
G4.4.15 PMSWINC, Performance Monitors Software Increment register
Accessing the PMSWINC:
G4.4.16 PMUSERENR, Performance Monitors User Enable Register
Accessing the PMUSERENR:
G4.4.17 PMXEVCNTR, Performance Monitors Selected Event Count Register
Accessing the PMXEVCNTR:
G4.4.18 PMXEVTYPER, Performance Monitors Selected Event Type Register
Accessing the PMXEVTYPER:
G4.5 Generic Timer registers
G4.5.1 CNTFRQ, Counter-timer Frequency register
Accessing the CNTFRQ:
G4.5.2 CNTHCTL, Counter-timer Hyp Control register
Accessing the CNTHCTL:
G4.5.3 CNTHP_CTL, Counter-timer Hyp Physical Timer Control register
Accessing the CNTHP_CTL:
G4.5.4 CNTHP_CVAL, Counter-timer Hyp Physical CompareValue register
Accessing the CNTHP_CVAL:
G4.5.5 CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue register
Accessing the CNTHP_TVAL:
G4.5.6 CNTKCTL, Counter-timer Kernel Control register
Accessing the CNTKCTL:
G4.5.7 CNTP_CTL, Counter-timer Physical Timer Control register
Accessing the CNTP_CTL:
G4.5.8 CNTP_CVAL, Counter-timer Physical Timer CompareValue register
Accessing the CNTP_CVAL:
G4.5.9 CNTP_TVAL, Counter-timer Physical Timer TimerValue register
Accessing the CNTP_TVAL:
G4.5.10 CNTPCT, Counter-timer Physical Count register
Accessing the CNTPCT:
G4.5.11 CNTV_CTL, Counter-timer Virtual Timer Control register
Accessing the CNTV_CTL:
G4.5.12 CNTV_CVAL, Counter-timer Virtual Timer CompareValue register
Accessing the CNTV_CVAL:
G4.5.13 CNTV_TVAL, Counter-timer Virtual Timer TimerValue register
Accessing the CNTV_TVAL:
G4.5.14 CNTVCT, Counter-timer Virtual Count register
Accessing the CNTVCT:
G4.5.15 CNTVOFF, Counter-timer Virtual Offset register
Accessing the CNTVOFF:
G4.6 Generic Interrupt Controller CPU interface registers
G4.6.1 ICC_AP0R0, Interrupt Controller Active Priorities Register (0,0)
Accessing the ICC_AP0R0:
G4.6.2 ICC_AP0R1, Interrupt Controller Active Priorities Register (0,1)
Accessing the ICC_AP0R1:
G4.6.3 ICC_AP0R2, Interrupt Controller Active Priorities Register (0,2)
Accessing the ICC_AP0R2:
G4.6.4 ICC_AP0R3, Interrupt Controller Active Priorities Register (0,3)
Accessing the ICC_AP0R3:
G4.6.5 ICC_AP1R0, Interrupt Controller Active Priorities Register (1,0)
Accessing the ICC_AP1R0:
G4.6.6 ICC_AP1R1, Interrupt Controller Active Priorities Register (1,1)
Accessing the ICC_AP1R1:
G4.6.7 ICC_AP1R2, Interrupt Controller Active Priorities Register (1,2)
Accessing the ICC_AP1R2:
G4.6.8 ICC_AP1R3, Interrupt Controller Active Priorities Register (1,3)
Accessing the ICC_AP1R3:
G4.6.9 ICC_ASGI1R, Interrupt Controller Alias Software Generated Interrupt group 1 Register
Accessing the ICC_ASGI1R:
G4.6.10 ICC_BPR0, Interrupt Controller Binary Point Register 0
Accessing the ICC_BPR0:
G4.6.11 ICC_BPR1, Interrupt Controller Binary Point Register 1
Accessing the ICC_BPR1:
G4.6.12 ICC_CTLR, Interrupt Controller Control Register
Accessing the ICC_CTLR:
G4.6.13 ICC_DIR, Interrupt Controller Deactivate Interrupt Register
Accessing the ICC_DIR:
G4.6.14 ICC_EOIR0, Interrupt Controller End Of Interrupt Register 0
Accessing the ICC_EOIR0:
G4.6.15 ICC_EOIR1, Interrupt Controller End Of Interrupt Register 1
Accessing the ICC_EOIR1:
G4.6.16 ICC_HPPIR0, Interrupt Controller Highest Priority Pending Interrupt Register 0
Accessing the ICC_HPPIR0:
G4.6.17 ICC_HPPIR1, Interrupt Controller Highest Priority Pending Interrupt Register 1
Accessing the ICC_HPPIR1:
G4.6.18 ICC_HSRE, Interrupt Controller Hyp System Register Enable register
Accessing the ICC_HSRE:
G4.6.19 ICC_IAR0, Interrupt Controller Interrupt Acknowledge Register 0
Accessing the ICC_IAR0:
G4.6.20 ICC_IAR1, Interrupt Controller Interrupt Acknowledge Register 1
Accessing the ICC_IAR1:
G4.6.21 ICC_IGRPEN0, Interrupt Controller Interrupt Group 0 Enable register
Accessing the ICC_IGRPEN0:
G4.6.22 ICC_IGRPEN1, Interrupt Controller Interrupt Group 1 Enable register
Accessing the ICC_IGRPEN1:
G4.6.23 ICC_MCTLR, Interrupt Controller Monitor Control Register
Accessing the ICC_MCTLR:
G4.6.24 ICC_MGRPEN1, Interrupt Controller Monitor Interrupt Group 1 Enable register
Accessing the ICC_MGRPEN1:
G4.6.25 ICC_MSRE, Interrupt Controller Monitor System Register Enable register
Accessing the ICC_MSRE:
G4.6.26 ICC_PMR, Interrupt Controller Interrupt Priority Mask Register
Accessing the ICC_PMR:
G4.6.27 ICC_RPR, Interrupt Controller Running Priority Register
Accessing the ICC_RPR:
G4.6.28 ICC_SEIEN, Interrupt Controller System Error Interrupt Enable register
Accessing the ICC_SEIEN:
G4.6.29 ICC_SGI0R, Interrupt Controller Software Generated Interrupt group 0 Register
Accessing the ICC_SGI0R:
G4.6.30 ICC_SGI1R, Interrupt Controller Software Generated Interrupt group 1 Register
Accessing the ICC_SGI1R:
G4.6.31 ICC_SRE, Interrupt Controller System Register Enable register
Accessing the ICC_SRE:
G4.6.32 ICH_AP0R0, Interrupt Controller Hyp Active Priorities Register (0,0)
Accessing the ICH_AP0R0:
G4.6.33 ICH_AP0R1, Interrupt Controller Hyp Active Priorities Register (0,1)
Accessing the ICH_AP0R1:
G4.6.34 ICH_AP0R2, Interrupt Controller Hyp Active Priorities Register (0,2)
Accessing the ICH_AP0R2:
G4.6.35 ICH_AP0R3, Interrupt Controller Hyp Active Priorities Register (0,3)
Accessing the ICH_AP0R3:
G4.6.36 ICH_AP1R0, Interrupt Controller Hyp Active Priorities Register (1,0)
Accessing the ICH_AP1R0:
G4.6.37 ICH_AP1R1, Interrupt Controller Hyp Active Priorities Register (1,1)
Accessing the ICH_AP1R1:
G4.6.38 ICH_AP1R2, Interrupt Controller Hyp Active Priorities Register (1,2)
Accessing the ICH_AP1R2:
G4.6.39 ICH_AP1R3, Interrupt Controller Hyp Active Priorities Register (1,3)
Accessing the ICH_AP1R3:
G4.6.40 ICH_EISR, Interrupt Controller End of Interrupt Status Register
Accessing the ICH_EISR:
G4.6.41 ICH_ELSR, Interrupt Controller Empty List Register Status Register
Accessing the ICH_ELSR:
G4.6.42 ICH_HCR, Interrupt Controller Hyp Control Register
Accessing the ICH_HCR:
G4.6.43 ICH_LRC, Interrupt Controller List Registers, n = 0 - 15
Accessing the ICH_LRC:
G4.6.44 ICH_LR, Interrupt Controller List Registers, n = 0 - 15
Accessing the ICH_LR:
G4.6.45 ICH_MISR, Interrupt Controller Maintenance Interrupt State Register
Accessing the ICH_MISR:
G4.6.46 ICH_VMCR, Interrupt Controller Virtual Machine Control Register
Accessing the ICH_VMCR:
G4.6.47 ICH_VSEIR, Interrupt Controller Virtual System Error Interrupt Register
Accessing the ICH_VSEIR:
G4.6.48 ICH_VTR, Interrupt Controller VGIC Type Register
Accessing the ICH_VTR:
Part H: External Debug
H1: Introduction to External Debug
H1.1 Introduction to external debug
H1.2 External debug
H2: Debug State
H2.1 About Debug state
H2.2 Halting the PE on debug events
H2.2.1 Halting allowed and halting prohibited
H2.2.2 Halting debug events
H2.2.3 Breakpoint and Watchpoint debug events
H2.2.4 Other debug exceptions
H2.2.5 Debug state entry and debug event prioritization
Debug state entry and Software Step
Breakpoint debug events and Vector Catch exception
H2.2.6 Forcing entry to Debug state
H2.2.7 Summary of actions from debug events
H2.2.8 Pseudocode details of Halting on debug events
H2.3 Entering Debug state
H2.3.1 Entering Debug state from AArch32 state
H2.3.2 Effect of entering Debug state on DLR and DSPSR
H2.3.3 Effect of entering Debug state on system registers, the Event register, and exclusive monitors
H2.3.4 Effect of entering Debug state on PSTATE
H2.3.5 Pseudocode details for entering Debug state
H2.4 Behavior in Debug state
H2.4.1 Process state (PSTATE) in Debug state
H2.4.2 Executing instructions in Debug state
Instructions that are unallocated in Debug state
Debug state instructions
Instructions with modified behavior in Debug state
Instructions that are unchanged in Debug state
unpredictable instructions in Debug state
H2.4.3 Debug state unallocated decode tables
H2.4.4 Instructions that debuggers might use in Debug state
H2.4.5 Security in Debug state
H2.4.6 Privilege in Debug state
H2.4.7 Debug state instructions, DCPS, DRPS, MRS, MSR
DCPS
DRPS
MRS and MSR instructions to access DLR_EL0 and DSPSR_EL0
H2.4.8 Exceptions in Debug state
Generating exceptions in Debug state
Taking exceptions in Debug state
Reset in Debug state
H2.4.9 Accessing registers in Debug state
General-purpose register access, other than SP access in AArch64 state
SIMD and floating-point, and system register accesses, and SP access in AArch64 state
PC and PSTATE access
H2.4.10 Accessing memory in Debug state
Simple memory transfers
Bulk memory transfers
H2.5 Exiting Debug state
H3: Halting Debug Events
H3.1 Introduction to Halting debug events
H3.2 Halting Step debug event
H3.2.1 Overview of a Halting Step debug event
H3.2.2 The Halting Step state machine
H3.2.3 Using Halting Step
H3.2.4 Detailed Halting Step state machine behavior
Entering the active-not-pending state
PE behavior in the active-not-pending state
Entering the active-pending state
PE behavior in the inactive state when in Non-debug state
PE behavior in Debug state
H3.2.5 Synchronization and the Halting Step state machine
H3.2.6 Stepping T32 IT instructions
H3.2.7 Disabling interrupts while stepping
H3.2.8 Syndrome information on Halting Step
H3.2.9 Pseudocode details for Halting Step debug events
H3.3 Halt Instruction debug event
H3.3.1 HLT instructions as the first instruction in a T32 IT block
H3.4 Exception Catch debug event
H3.4.1 Prioritization of Exception Catch debug events
H3.4.2 UNPREDICTABLE generation of Exception Catch debug events
H3.4.3 Examples of Exception Catch debug events
H3.4.4 Pseudocode details for Exception Catch debug events
H3.5 External Debug Request debug event
H3.5.1 Pseudocode details for External Debug Request debug events
H3.6 OS Unlock Catch debug event
H3.6.1 Using the OS Unlock Catch debug event
H3.6.2 Pseudocode details for OS Unlock Catch debug event
H3.7 Reset Catch debug event
H3.7.1 Pseudocode details for Reset Catch debug event
H3.8 Software Access debug event
H3.8.1 Pseudocode details for Software Access debug event
H3.9 Synchronization and Halting debug events
H3.9.1 Pending Halting debug events
H3.9.2 Taking Halting debug events asynchronously
H4: The Debug Communication Channel and Instruction Transfer Register
H4.1 Introduction
H4.2 DCC and ITR registers
H4.3 DCC and ITR access modes
H4.3.1 Normal access mode
H4.3.2 Memory access mode
Ordering, access sizes and effect on exclusive monitors
Data aborts
Illegal State exception
Alignment constraints
H4.3.3 Memory-mapped accesses to the DCC and ITR
H4.4 Flow-control of the DCC and ITR registers
H4.4.1 Ready flags
H4.4.2 Overrun and underrun flags
Accessing 64-bit data
H4.4.3 Cumulative error flag
Pseudocode details for clearing the error flag
H4.5 Synchronization of DCC and ITR accesses
H4.5.1 Summary of system register accesses to the DCC
H4.5.2 DCC accesses in Non-debug state
H4.5.3 Synchronization of DCC interrupt request signals
H4.5.4 DCC and ITR access in Debug state
H4.6 Interrupt-driven use of the DCC
H4.7 Pseudocode details for the operation of the DCC and ITR registers
H5: The Embedded Cross Trigger Interface
H5.1 About the Embedded Cross Trigger (ECT)
H5.1.1 Implementation with a CoreSight CTI
H5.2 Basic operation on the ECT
H5.2.1 Multicycle events
An ECT that supports multicycle trigger events
An ECT that does not support multicycle trigger events
H5.3 Cross-triggers on a PE in an ARMv8 implementation
H5.4 Description and allocation of CTI triggers
H5.4.1 Debug request trigger event
H5.4.2 Restart request trigger event
H5.4.3 Cross-halt trigger event
H5.4.4 Performance Monitors overflow trigger event
H5.4.5 Generic trace external input trigger events
H5.4.6 Generic trace external output trigger events
H5.4.7 Generic CTI interrupt trigger event
H5.5 CTI registers programmers’ model
H5.5.1 CTI reset
H5.5.2 CTI authentication
H5.6 Examples
H6: Debug Reset and Powerdown Support
H6.1 About Debug over powerdown
H6.2 Power domains and debug
H6.3 Core power domain power states
H6.4 Emulating low-power states
H6.5 Debug OS Save and Restore sequences
H6.5.1 Debug registers to save over powerdown
H6.5.2 OS Save sequence
H6.5.3 OS Restore sequence
H6.5.4 Debug behavior when the OS Lock is locked
H6.5.5 Debug behavior when the OS Lock is unlocked
H6.5.6 Debug behavior when the OS Double Lock is locked
H7: The Sample-based Profiling Extension
H7.1 Sample-based profiling
H7.1.1 The implemented Sample-based profiling registers
H7.1.2 Reads of the External Debug Program Counter Sampling Registers
H7.1.3 Reads of the External Debug Virtual Context Sample Register
H7.1.4 Accuracy of sampling
H7.1.5 Sample-based Profiling and security
H7.1.6 Pseudocode details of Sample-based Profiling
H8: About the External Debug Registers
H8.1 Relationship between external debug and System registers
H8.2 Supported access sizes
H8.3 Synchronization of changes to the external debug registers
H8.3.1 Synchronization and the authentication interface
H8.3.2 Examples of the synchronization of changes to the external debug registers
H8.4 Memory-mapped accesses to the external debug interface
H8.4.1 Register access permissions for memory-mapped accesses
Effect of the optional Software Lock on memory-mapped access
Behavior of a not permitted memory-mapped access
H8.4.2 Synchronization of memory-mapped accesses to external debug registers
H8.4.3 Access sizes for memory-mapped accesses
H8.5 External debug interface register access permissions
H8.5.1 External debug over powerdown and locks
H8.5.2 External access disabled
H8.5.3 Behavior of a not permitted access
H8.5.4 Trapping software access to debug registers
H8.5.5 External debug interface register access permissions summary
H8.5.6 implementation defined registers
H8.5.7 optional CoreSight management registers
H8.5.8 Reserved and unallocated registers
H8.6 External debug interface registers
H8.7 Cross-trigger interface registers
H8.8 Reset and debug
H8.8.1 External debug interface accesses to registers in reset
H8.9 External debug register resets
H9: External Debug Register Descriptions
H9.1 Introduction
H9.2 Debug registers
H9.2.1 DBGAUTHSTATUS_EL1, Debug Authentication Status register
Accessing the DBGAUTHSTATUS_EL1:
H9.2.2 DBGBCR_EL1, Debug Breakpoint Control Registers, n = 0 - 15
Accessing the DBGBCR_EL1:
H9.2.3 DBGBVR_EL1, Debug Breakpoint Value Registers, n = 0 - 15
When DBGBCR_EL1.BT==0b0x0x:
When DBGBCR_EL1.BT==0b0x1x:
When DBGBCR_EL1.BT==0b1x0x and EL2 implemented:
When DBGBCR_EL1.BT==0x1x1x and EL2 implemented:
Accessing the DBGBVR_EL1:
H9.2.4 DBGCLAIMCLR_EL1, Debug Claim Tag Clear register
Accessing the DBGCLAIMCLR_EL1:
H9.2.5 DBGCLAIMSET_EL1, Debug Claim Tag Set register
Accessing the DBGCLAIMSET_EL1:
H9.2.6 DBGDTRRX_EL0, Debug Data Transfer Register, Receive
Accessing the DBGDTRRX_EL0:
H9.2.7 DBGDTRTX_EL0, Debug Data Transfer Register, Transmit
Accessing the DBGDTRTX_EL0:
H9.2.8 DBGWCR_EL1, Debug Watchpoint Control Registers, n = 0 - 15
Accessing the DBGWCR_EL1:
H9.2.9 DBGWVR_EL1, Debug Watchpoint Value Registers, n = 0 - 15
Accessing the DBGWVR_EL1:
H9.2.10 EDACR, External Debug Auxiliary Control Register
Accessing the EDACR:
H9.2.11 EDCIDR0, External Debug Component Identification Register 0
Accessing the EDCIDR0:
H9.2.12 EDCIDR1, External Debug Component Identification Register 1
Accessing the EDCIDR1:
H9.2.13 EDCIDR2, External Debug Component Identification Register 2
Accessing the EDCIDR2:
H9.2.14 EDCIDR3, External Debug Component Identification Register 3
Accessing the EDCIDR3:
H9.2.15 EDCIDSR, External Debug Context ID Sample Register
Accessing the EDCIDSR:
H9.2.16 EDDEVAFF0, External Debug Device Affinity register 0
Accessing the EDDEVAFF0:
H9.2.17 EDDEVAFF1, External Debug Device Affinity register 1
Accessing the EDDEVAFF1:
H9.2.18 EDDEVARCH, External Debug Device Architecture register
Accessing the EDDEVARCH:
H9.2.19 EDDEVID, External Debug Device ID register 0
Accessing the EDDEVID:
H9.2.20 EDDEVID1, External Debug Device ID register 1
Accessing the EDDEVID1:
H9.2.21 EDDEVID2, External Debug Device ID register 2
Accessing the EDDEVID2:
H9.2.22 EDDEVTYPE, External Debug Device Type register
Accessing the EDDEVTYPE:
H9.2.23 EDECCR, External Debug Exception Catch Control Register
Accessing the EDECCR:
H9.2.24 EDECR, External Debug Execution Control Register
Accessing the EDECR:
H9.2.25 EDESR, External Debug Event Status Register
Accessing the EDESR:
H9.2.26 EDITCTRL, External Debug Integration mode Control register
Accessing the EDITCTRL:
H9.2.27 EDITR, External Debug Instruction Transfer Register
When in AArch32 state:
When in AArch64 state:
Accessing the EDITR:
H9.2.28 EDLAR, External Debug Lock Access Register
Accessing the EDLAR:
H9.2.29 EDLSR, External Debug Lock Status Register
Accessing the EDLSR:
H9.2.30 EDPCSR, External Debug Program Counter Sample Register
Accessing the EDPCSR:
H9.2.31 EDPIDR0, External Debug Peripheral Identification Register 0
Accessing the EDPIDR0:
H9.2.32 EDPIDR1, External Debug Peripheral Identification Register 1
Accessing the EDPIDR1:
H9.2.33 EDPIDR2, External Debug Peripheral Identification Register 2
Accessing the EDPIDR2:
H9.2.34 EDPIDR3, External Debug Peripheral Identification Register 3
Accessing the EDPIDR3:
H9.2.35 EDPIDR4, External Debug Peripheral Identification Register 4
Accessing the EDPIDR4:
H9.2.36 EDPRCR, External Debug Power/Reset Control Register
Accessing the EDPRCR:
H9.2.37 EDPRSR, External Debug Processor Status Register
Accessing the EDPRSR:
H9.2.38 EDRCR, External Debug Reserve Control Register
Accessing the EDRCR:
H9.2.39 EDSCR, External Debug Status and Control Register
Accessing the EDSCR:
H9.2.40 EDVIDSR, External Debug Virtual Context Sample Register
Accessing the EDVIDSR:
H9.2.41 EDWAR, External Debug Watchpoint Address Register
Accessing the EDWAR:
H9.2.42 ID_AA64DFR0_EL1, Debug Feature Register 0
Accessing the ID_AA64DFR0_EL1:
H9.2.43 ID_AA64DFR1_EL1, Debug Feature Register 1
Accessing the ID_AA64DFR1_EL1:
H9.2.44 ID_AA64ISAR0_EL1, Instruction Set Attribute Register 0
Accessing the ID_AA64ISAR0_EL1:
H9.2.45 ID_AA64ISAR1_EL1, Instruction Set Attribute Register 1
Accessing the ID_AA64ISAR1_EL1:
H9.2.46 ID_AA64MMFR0_EL1, Memory Model Feature Register 0
Accessing the ID_AA64MMFR0_EL1:
H9.2.47 ID_AA64MMFR1_EL1, Memory Model Feature Register 1
Accessing the ID_AA64MMFR1_EL1:
H9.2.48 ID_AA64PFR0_EL1, Processor Feature Register 0
Accessing the ID_AA64PFR0_EL1:
H9.2.49 ID_AA64PFR1_EL1, Processor Feature Register 1
Accessing the ID_AA64PFR1_EL1:
H9.2.50 MIDR_EL1, Main ID Register
Accessing the MIDR_EL1:
H9.2.51 OSLAR_EL1, OS Lock Access Register
Accessing the OSLAR_EL1:
H9.3 Cross-Trigger Interface registers
H9.3.1 ASICCTL, CTI External Multiplexer Control register
Accessing the ASICCTL:
H9.3.2 CTIAPPCLEAR, CTI Application Trigger Clear register
Accessing the CTIAPPCLEAR:
H9.3.3 CTIAPPPULSE, CTI Application Pulse register
Accessing the CTIAPPPULSE:
H9.3.4 CTIAPPSET, CTI Application Trigger Set register
Accessing the CTIAPPSET:
H9.3.5 CTIAUTHSTATUS, CTI Authentication Status register
Accessing the CTIAUTHSTATUS:
H9.3.6 CTICHINSTATUS, CTI Channel In Status register
Accessing the CTICHINSTATUS:
H9.3.7 CTICHOUTSTATUS, CTI Channel Out Status register
Accessing the CTICHOUTSTATUS:
H9.3.8 CTICIDR0, CTI Component Identification Register 0
Accessing the CTICIDR0:
H9.3.9 CTICIDR1, CTI Component Identification Register 1
Accessing the CTICIDR1:
H9.3.10 CTICIDR2, CTI Component Identification Register 2
Accessing the CTICIDR2:
H9.3.11 CTICIDR3, CTI Component Identification Register 3
Accessing the CTICIDR3:
H9.3.12 CTICLAIMCLR, CTI Claim Tag Clear register
Accessing the CTICLAIMCLR:
H9.3.13 CTICLAIMSET, CTI Claim Tag Set register
Accessing the CTICLAIMSET:
H9.3.14 CTICONTROL, CTI Control register
Accessing the CTICONTROL:
H9.3.15 CTIDEVAFF0, CTI Device Affinity register 0
Accessing the CTIDEVAFF0:
H9.3.16 CTIDEVAFF1, CTI Device Affinity register 1
Accessing the CTIDEVAFF1:
H9.3.17 CTIDEVARCH, CTI Device Architecture register
Accessing the CTIDEVARCH:
H9.3.18 CTIDEVID, CTI Device ID register 0
Accessing the CTIDEVID:
H9.3.19 CTIDEVID1, CTI Device ID register 1
Accessing the CTIDEVID1:
H9.3.20 CTIDEVID2, CTI Device ID register 2
Accessing the CTIDEVID2:
H9.3.21 CTIDEVTYPE, CTI Device Type register
Accessing the CTIDEVTYPE:
H9.3.22 CTIGATE, CTI Channel Gate Enable register
Accessing the CTIGATE:
H9.3.23 CTIINEN, CTI Input Trigger to Output Channel Enable registers, n = 0 - 31
Accessing the CTIINEN:
H9.3.24 CTIINTACK, CTI Output Trigger Acknowledge register
Accessing the CTIINTACK:
H9.3.25 CTIITCTRL, CTI Integration mode Control register
Accessing the CTIITCTRL:
H9.3.26 CTILAR, CTI Lock Access Register
Accessing the CTILAR:
H9.3.27 CTILSR, CTI Lock Status Register
Accessing the CTILSR:
H9.3.28 CTIOUTEN, CTI Input Channel to Output Trigger Enable registers, n = 0 - 31
Accessing the CTIOUTEN:
H9.3.29 CTIPIDR0, CTI Peripheral Identification Register 0
Accessing the CTIPIDR0:
H9.3.30 CTIPIDR1, CTI Peripheral Identification Register 1
Accessing the CTIPIDR1:
H9.3.31 CTIPIDR2, CTI Peripheral Identification Register 2
Accessing the CTIPIDR2:
H9.3.32 CTIPIDR3, CTI Peripheral Identification Register 3
Accessing the CTIPIDR3:
H9.3.33 CTIPIDR4, CTI Peripheral Identification Register 4
Accessing the CTIPIDR4:
H9.3.34 CTITRIGINSTATUS, CTI Trigger In Status register
Accessing the CTITRIGINSTATUS:
H9.3.35 CTITRIGOUTSTATUS, CTI Trigger Out Status register
Accessing the CTITRIGOUTSTATUS:
Part I: Memory-mapped Components of the ARMv8 Architecture
I1: Memory-Mapped System Register Descriptions
I1.1 Introduction
I1.2 Performance Monitors registers
I1.2.1 PMAUTHSTATUS, Performance Monitors Authentication Status register
Accessing the PMAUTHSTATUS:
I1.2.2 PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register
Accessing the PMCCFILTR_EL0:
I1.2.3 PMCCNTR_EL0, Performance Monitors Cycle Counter
Accessing the PMCCNTR_EL0:
I1.2.4 PMCEID0_EL0, Performance Monitors Common Event Identification register 0
Accessing the PMCEID0_EL0:
I1.2.5 PMCEID1_EL0, Performance Monitors Common Event Identification register 1
Accessing the PMCEID1_EL0:
I1.2.6 PMCFGR, Performance Monitors Configuration Register
Accessing the PMCFGR:
I1.2.7 PMCIDR0, Performance Monitors Component Identification Register 0
Accessing the PMCIDR0:
I1.2.8 PMCIDR1, Performance Monitors Component Identification Register 1
Accessing the PMCIDR1:
I1.2.9 PMCIDR2, Performance Monitors Component Identification Register 2
Accessing the PMCIDR2:
I1.2.10 PMCIDR3, Performance Monitors Component Identification Register 3
Accessing the PMCIDR3:
I1.2.11 PMCNTENCLR_EL0, Performance Monitors Count Enable Clear register
Accessing the PMCNTENCLR_EL0:
I1.2.12 PMCNTENSET_EL0, Performance Monitors Count Enable Set register
Accessing the PMCNTENSET_EL0:
I1.2.13 PMCR_EL0, Performance Monitors Control Register
Accessing the PMCR_EL0:
I1.2.14 PMDEVAFF0, Performance Monitors Device Affinity register 0
Accessing the PMDEVAFF0:
I1.2.15 PMDEVAFF1, Performance Monitors Device Affinity register 1
Accessing the PMDEVAFF1:
I1.2.16 PMDEVARCH, Performance Monitors Device Architecture register
Accessing the PMDEVARCH:
I1.2.17 PMDEVTYPE, Performance Monitors Device Type register
Accessing the PMDEVTYPE:
I1.2.18 PMEVCNTR_EL0, Performance Monitors Event Count Registers, n = 0 - 30
Accessing the PMEVCNTR_EL0:
I1.2.19 PMEVTYPER_EL0, Performance Monitors Event Type Registers, n = 0 - 30
Accessing the PMEVTYPER_EL0:
I1.2.20 PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register
Accessing the PMINTENCLR_EL1:
I1.2.21 PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register
Accessing the PMINTENSET_EL1:
I1.2.22 PMITCTRL, Performance Monitors Integration mode Control register
Accessing the PMITCTRL:
I1.2.23 PMLAR, Performance Monitors Lock Access Register
Accessing the PMLAR:
I1.2.24 PMLSR, Performance Monitors Lock Status Register
Accessing the PMLSR:
I1.2.25 PMOVSCLR_EL0, Performance Monitors Overflow Flag Status Clear register
Accessing the PMOVSCLR_EL0:
I1.2.26 PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register
Accessing the PMOVSSET_EL0:
I1.2.27 PMPIDR0, Performance Monitors Peripheral Identification Register 0
Accessing the PMPIDR0:
I1.2.28 PMPIDR1, Performance Monitors Peripheral Identification Register 1
Accessing the PMPIDR1:
I1.2.29 PMPIDR2, Performance Monitors Peripheral Identification Register 2
Accessing the PMPIDR2:
I1.2.30 PMPIDR3, Performance Monitors Peripheral Identification Register 3
Accessing the PMPIDR3:
I1.2.31 PMPIDR4, Performance Monitors Peripheral Identification Register 4
Accessing the PMPIDR4:
I1.2.32 PMSWINC_EL0, Performance Monitors Software Increment register
Accessing the PMSWINC_EL0:
I1.3 Generic Timer registers
I1.3.1 CNTACR, Counter-timer Access Control Registers, n = 0 - 7
Accessing the CNTACR:
I1.3.2 CNTCR, Counter Control Register
Accessing the CNTCR:
I1.3.3 CNTCV, Counter Count Value register
Accessing the CNTCV:
I1.3.4 CNTEL0ACR, Counter-timer EL0 Access Control Register
Accessing the CNTEL0ACR:
I1.3.5 CNTFID0, Counter Frequency ID
Accessing the CNTFID0:
I1.3.6 CNTFID, Counter Frequency IDs, n = 1 - 23
Accessing the CNTFID:
I1.3.7 CNTFRQ, Counter-timer Frequency
Accessing the CNTFRQ:
I1.3.8 CNTNSAR, Counter-timer Non-secure Access Register
Accessing the CNTNSAR:
I1.3.9 CNTP_CTL, Counter-timer Physical Timer Control
Accessing the CNTP_CTL:
I1.3.10 CNTP_CVAL, Counter-timer Physical Timer CompareValue
Accessing the CNTP_CVAL:
I1.3.11 CNTP_TVAL, Counter-timer Physical Timer TimerValue
Accessing the CNTP_TVAL:
I1.3.12 CNTPCT, Counter-timer Physical Count
Accessing the CNTPCT:
I1.3.13 CNTSR, Counter Status Register
Accessing the CNTSR:
I1.3.14 CNTTIDR, Counter-timer Timer ID Register
Accessing the CNTTIDR:
I1.3.15 CNTV_CTL, Counter-timer Virtual Timer Control
Accessing the CNTV_CTL:
I1.3.16 CNTV_CVAL, Counter-timer Virtual Timer CompareValue
Accessing the CNTV_CVAL:
I1.3.17 CNTV_TVAL, Counter-timer Virtual Timer TimerValue
Accessing the CNTV_TVAL:
I1.3.18 CNTVCT, Counter-timer Virtual Count
Accessing the CNTVCT:
I1.3.19 CNTVOFF, Counter-timer Virtual Offset
Accessing the CNTVOFF:
I1.3.20 CNTVOFF, Counter-timer Virtual Offsets, n = 0 - 7
Accessing the CNTVOFF:
I1.3.21 CounterID, Counter ID registers, n = 0 - 11
Accessing the CounterID:
I2: System Level Implementation of the Generic Timer
I2.1 About the Generic Timer specification
I2.1.1 The memory-mapped view of the Generic Timer
I2.2 Memory-mapped counter module
I2.2.1 Control of counter operating frequency and increment
The frequency modes table
Changing the system counter and increment
I2.3 Counter module control and status register summary
I2.4 About the memory-mapped view of the counter and timer
I2.5 The CNTBaseN and CNTPL0BaseN frames
I2.6 The CNTCTLBase frame
I2.7 Providing a complete set of counter and timer features
I2.8 Gray-count scheme for timer distribution scheme
I3: Recommended Memory-mapped Interfaces to the Performance Monitors
I3.1 About the memory-mapped views of the Performance Monitors registers
I3.1.1 Differences in the memory-mapped views of the Performance Monitors registers
I3.1.2 Synchronization of changes to the memory-mapped views
I3.1.3 Performance Monitors memory-mapped register views
I3.1.4 Access permissions for memory-mapped views of the Performance Monitors
I3.1.5 Power domains and Performance Monitors registers reset
Part J: Appendixes
A: Architectural Constraints on UNPREDICTABLE behaviors
A.1 AArch32 CONSTRAINED UNPREDICTABLE behaviors
A.1.1 Overview of the constraints on ARMv7 UNPREDICTABLE behaviors
A.1.2 CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instructions
BFC
BFI
BKPT
CLZ
CMP (register)
CRC32, CRC32C
HLT
IT
LDC/LDC2 (literal)
LDM/LDMIA/LDMFD (T32)
LDM/LDMIA/LDMFD (A32)
LDMDA/LDMFA
LDMIB/LDMED
LDMDB/LDMEA
LDR (immediate, T32)
LDR (immediate, A32)
LDR (register, A32)
LDRB (immediate, T32)
LDRB (immediate, A32)
LDRB (register)
LDRBT
LDRH (immediate, T32)
LDRH (immediate, A32)
LDRH (register)
LDRHT
LDRSB (immediate)
LDRSB (register)
LDRSBT
LDRSH (immediate)
LDRSH (register)
LDRSHT
LDRT
LDR (literal)
LDRB (literal)
LDRH (literal)
LDRSB (literal)
LDRSH (literal)
LDRD (immediate)
LDRD (register)
LDRD (literal)
LDREX
LDREXH
LDREXB
LDAEX
LDAEXH
LDAEXB
LDREXD
LDAEXD
MOV (register, T32)
MRRC, MRRC2
MSR (register)
POP (T32)
POP (A32)
PUSH
RBIT
REV
REV16
REVSH
SBFX
UBFX
SDIV
UDIV
SMULL
SMLAL
SMLALBB, SMLALBT, SMLALTB, SMLALTT
SMLALD
SMLSLD
UMULL
UMAAL
UMLAL
STC, STC2
STM (STMIA, STMEA)
STMDA (STMED)
STMIB (STMFA)
STMDB (STMFD)
STR (immediate, T32)
STR (immediate, A32)
STR (register)
STRB (immediate, T32)
STRB (immediate, A32)
STRB (register)
STRBT
STRH (immediate, T32)
STRH (immediate, A32)
STRH (register)
STRHT
STRT
STRD (immediate)
STRD (register)
STREX
STREXB
STREXD
STREXH
STLEX
STLEXB
STLEXD
STLEXH
VCVT (between floating-point and fixed-point)
VLD1 (multiple single elements)
VLD1 (single element to all lanes)
VLD2 (multiple 2-element structures)
VLD2 (single 2-element structure to one lane)
VLD2 (single 2-element structure to all lanes)
VLD3 (multiple 3-element structures)
VLD3 (single 3-element structure to one lane)
VLD3 (single 3-element structure to all lanes)
VLD4 (multiple 4-element structures)
VLD4 (single 4-element structure to one lane)
VLD4 (single 4-element structure to all lanes)
VLDM
VPOP
VMOV (between two general-purpose registers and two single-precision registers)
VMOV (between two general-purpose registers and a doubleword extension register)
VST1 (multiple single elements)
VST2 (multiple 2-element structures)
VST2 (single 2-element structure from one lane)
VST3 (multiple 3-element structures)
VST3 (single 3-element structure from one lane)
VST4 (multiple 4-element structures)
VST4 (single 4-element structure from one lane)
VSTM
VPUSH
VTBL, VTBX
A.1.3 CONSTRAINED UNPREDICTABLE behavior, A32 and T32 system instructions
CPS (A32)
CPS (T32)
LDM (exception return)
LDM (User registers)
MRS
MSR (immediate)
MSR (register)
RFE
SRS (T32)
SRS (A32)
STM (User registers)
SUBS PC, LR and related instructions (T32)
SUBS PC. LR and related instructions (A32)
VMRS
VMSR
A.1.4 CONSTRAINED UNPREDICTABLE behavior in Debug state
A.1.5 Using R13
A.1.6 Using R15
A.1.7 SBZ or SBO fields in instructions
A.1.8 CONSTRAINED UNPREDICTABLE behavior in an IT block
A.1.9 Branching into an IT block
A.1.10 Syndrome register handling for CONSTRAINED UNPREDICTABLE instructions treated as UNDEFINED
A.1.11 Unallocated values in register fields of CP14 and CP 15 registers and translation table entries
A.1.12 Unallocated CP14 and CP15 instructions
A.1.13 Loads and Stores to unaligned locations
A.1.14 Branching to an unaligned PC
A.1.15 Unpredictable CPACR and NSACR settings
A.1.16 Instruction fetches from Device memory
A.1.17 Multi-access instructions that load the PC from Device memory
A.1.18 Out of range virtual address
A.1.19 Translation Table Base Address alignment
A.2 Constraints on AArch64 state UNPREDICTABLE behaviors
A.2.1 Overview of the constraints on AArch64 UNPREDICTABLE behaviors
A.2.2 CONSTRAINED UNPREDICTABLE behavior for A64 instructions
LDR (immediate)
LDRB (immediate)
LDRH (immediate)
LDRSB (immediate)
LDRSH (immediate)
LDRSW (immediate)
LDP
LDPSW
LDNP (SIMD&FP)
LDP (SIMD&FP)
LDAXP
LDXP
STR (immediate)
STRB (immediate)
STRH (immediate)
STP
STLXR
STLXRB
STLXRH
STXR
STXRB
STXRH
STLXP
STXP
B: Recommended External Debug Interface
B.1 About the recommended external debug interface
B.2 PMUEVENT bus
B.3 DBGCPUDONE
B.4 Recommended authentication interface
B.4.1 Pseudocode details for AArch32 Self-Hosted Secure Privileged Invasive Debug Enabled
B.4.2 Pseudocode details for External Invasive Debug Enabled
B.4.3 Pseudocode details for External Secure Invasive Debug Enabled
B.4.4 Pseudocode details for External Non-invasive Debug Enabled
B.4.5 Pseudocode details for External Secure Non-invasive Debug Enabled
B.5 Management registers and CoreSight compliance
B.5.1 CoreSight interface register map
B.5.2 Management register access permissions
B.5.3 Management register resets
C: Recommendations for Performance Monitors Event Numbers for IMPLEMENTATION DEFINED Events
C.1 ARM recommendations for IMPLEMENTATION DEFINED event numbers
C.2 Summary of events taken to an Exception Level using AArch64
D: Example OS Save and Restore sequences
D.1 Save Debug registers
D.2 Restore Debug registers
E: Additional Guidance
E.1 Implementation guidance for multiple views of Debug registers
E.2 AArch32 equivalent Advanced SIMD Mnemonics
E.3 Identifying the cache resources in ARMv8
E.4 Memory access mode in Debug state
E.4.1 Alignment constraints
E.4.2 Using memory access mode in AArch64 state
F: Barrier Litmus Tests
F.1 Introduction
F.1.1 Overview of memory consistency
F.1.2 Barrier operation definitions
F.1.3 Conventions
Notes on timing effects
F.2 Load-Acquire, Store-Release and barriers
F.2.1 Message passing
Resolving weakly-ordered message passing by using Acquire and Release
Resolving message passing by the use of Store-Release and address dependency
F.2.2 Address dependency with object construction
F.2.3 Causal consistency issues with multiple observers
Using multi-copy atomicity of the Store-Release when observed by Load-Acquire
Using ordering property of Store-Release on stores observed by the PE
F.2.4 Multiple observers of writes to multiple locations
F.2.5 WFE and WFI and barriers
F.3 Load-Acquire Exclusive, Store-Release Exclusive and barriers
F.3.1 Acquiring a lock
F.3.2 Releasing a lock
F.3.3 Ticket locks
F.3.4 Use of Wait For Event (WFE) and Send Event (SEV) with locks
Simple lock
Ticket lock
F.4 Using a mailbox to send an interrupt
F.5 Cache and TLB maintenance operations and barriers
F.5.1 Data cache maintenance operations
Message passing to non-caching observers
Multiprocessing message passing to non-caching observers
Invalidating DMA buffers, non-functional example
Invalidating DMA buffers, functional example with single PE
Invalidating DMA buffers, functional example with multiple coherent PEs
F.5.2 Instruction cache maintenance operations
Ensuring the visibility of updates to instructions for a uniprocessor
Ensuring the visibility of updates to instructions for a multiprocessor
F.5.3 TLB maintenance operations and barriers
Ensuring the visibility of updates to translation tables for a uniprocessor
Ensuring the visibility of updates to translation tables for a multiprocessor
Paging memory in and out
F.5.4 Ordering of Memory-mapped device control with payloads
F.6 ARMv7 compatible approaches for ordering, using DMB and DSB barriers
F.6.1 Simple ordering and barrier cases
Simple weakly consistent ordering example
Message passing
Address dependency with object construction
Causal consistency issues with multiple observers
Multiple observers of writes to multiple locations
Posting a store before polling for acknowledgement
WFE and WFI and barriers
F.6.2 Load-Exclusive, Store-Exclusive and barriers
Acquiring a lock
Releasing a lock
Use of Wait For Event (WFE) and Send Event (SEV) with locks
F.6.3 Using a mailbox to send an interrupt
F.6.4 Cache and TLB maintenance operations and barriers
Data cache maintenance operations
Instruction cache maintenance operations
TLB maintenance operations and barriers
G: ARMv8 Pseudocode Library
G.1 Library pseudocode for AArch64
G.1.1 aarch64/debug
aarch64/debug/breakpoint
aarch64/debug/enables
aarch64/debug/watchpoint
G.1.2 aarch64/exceptions
aarch64/exceptions/aborts
aarch64/exceptions/asynch
aarch64/exceptions/debug
aarch64/exceptions/exceptions
aarch64/exceptions/ieeefp
aarch64/exceptions/syscalls
aarch64/exceptions/traps
G.1.3 aarch64/functions
aarch64/functions/aborts
aarch64/functions/exclusive
aarch64/functions/fusedrstep
aarch64/functions/memory
aarch64/functions/registers
aarch64/functions/sysregisters
aarch64/functions/system
G.1.4 aarch64/instrs
aarch64/instrs/branch/eret
aarch64/instrs/countop
aarch64/instrs/extendreg
aarch64/instrs/float/arithmetic/max-min/fpmaxminop
aarch64/instrs/float/arithmetic/unary/fpunaryop
aarch64/instrs/float/convert/fpconvop
aarch64/instrs/integer/arithmetic/rev/revop
aarch64/instrs/integer/bitfield/bfxpreferred
aarch64/instrs/integer/bitmasks
aarch64/instrs/integer/ins-ext/insert/movewide/movewideop
aarch64/instrs/integer/logical/movwpreferred
aarch64/instrs/integer/shiftreg
aarch64/instrs/logicalop
aarch64/instrs/memory/memop
aarch64/instrs/memory/prefetch
aarch64/instrs/system/barriers/barrierop
aarch64/instrs/system/hints/syshintop
aarch64/instrs/system/register/cpsr/pstatefield
aarch64/instrs/system/sysops/sysop
aarch64/instrs/vector/arithmetic/binary/uniform/logical/bsl-eor/vbitop
aarch64/instrs/vector/arithmetic/unary/cmp/compareop
aarch64/instrs/vector/crypto/enabled
aarch64/instrs/vector/logical/immediateop
aarch64/instrs/vector/reduce/reduceop
G.1.5 aarch64/translation
aarch64/translation/attrs
aarch64/translation/checks
aarch64/translation/debug
aarch64/translation/faults
aarch64/translation/translation
aarch64/translation/walk
G.2 Library pseudocode for AArch32
G.2.1 aarch32/debug
aarch32/debug/VCRMatch
aarch32/debug/breakpoint
aarch32/debug/enables
aarch32/debug/watchpoint
G.2.2 aarch32/exceptions
aarch32/exceptions/aborts
aarch32/exceptions/asynch
aarch32/exceptions/debug
aarch32/exceptions/exceptions
aarch32/exceptions/ieeefp
aarch32/exceptions/syscalls
aarch32/exceptions/traps
G.2.3 aarch32/functions
aarch32/functions/aborts
aarch32/functions/common
aarch32/functions/coproc
aarch32/functions/exclusive
aarch32/functions/float
aarch32/functions/memory
aarch32/functions/registers
aarch32/functions/system
aarch32/functions/v6simd
G.2.4 aarch32/translation
aarch32/translation/attrs
aarch32/translation/checks
aarch32/translation/debug
aarch32/translation/faults
aarch32/translation/translation
aarch32/translation/walk
G.3 Common library pseudocode
G.3.1 shared/debug
shared/debug/CONTEXTIDR_GEN
shared/debug/ClearStickyErrors
shared/debug/DebugTarget
shared/debug/DoubleLockStatus
shared/debug/FindWatchpoint
shared/debug/authentication
shared/debug/cti
shared/debug/dccanditr
shared/debug/halting
shared/debug/haltingevents
shared/debug/interrupts
shared/debug/pmu
shared/debug/samplebasedprofiling
shared/debug/softwarestep
G.3.2 shared/exceptions
shared/exceptions/exceptions
shared/exceptions/traps
G.3.3 shared/functions
shared/functions/aborts
shared/functions/common
shared/functions/crc
shared/functions/crypto
shared/functions/exclusive
shared/functions/float
shared/functions/gray
shared/functions/integer
shared/functions/memory
shared/functions/registers
shared/functions/sysregisters
shared/functions/system
shared/functions/unpredictable
shared/functions/vector
G.3.4 shared/translation
shared/translation/attrs
shared/translation/translation
H: ARM Pseudocode Definition
H.1 About the ARM pseudocode
H.1.1 General limitations of ARM pseudocode
H.2 Pseudocode for instruction descriptions
H.2.1 Instruction encoding diagrams and instruction pseudocode
H.2.2 Limitations of the instruction pseudocode
H.3 Data types
H.3.1 General data type rules
H.3.2 Bitstrings
H.3.3 Integers
H.3.4 Reals
H.3.5 Booleans
H.3.6 Enumerations
H.3.7 Lists
H.3.8 Arrays
H.4 Expressions
H.4.1 General expression syntax
H.4.2 Operators and functions - polymorphism and prototypes
H.4.3 Precedence rules
H.5 Operators and built-in functions
H.5.1 Operations on generic types
Equality and non-equality testing
Conditional selection
H.5.2 Operations on Booleans
H.5.3 Bitstring manipulation
Bitstring length and most significant bit
Bitstring concatenation and replication
Bitstring extraction
Logical operations on bitstrings
Bitstring count
Testing a bitstring for being all zero or all ones
Lowest and highest set bits of a bitstring
Zero-extension and sign-extension of bitstrings
Converting bitstrings to integers
H.5.4 Arithmetic
Unary plus, minus and absolute value
Addition and subtraction
Comparisons
Multiplication
Division and modulo
Square root
Rounding and aligning
Scaling
Maximum and minimum
Raising to a power
H.6 Statements and program structure
H.6.1 Simple statements
Assignments
Procedure calls
Return statements
UNDEFINED
UNPREDICTABLE
SEE…
IMPLEMENTATION_DEFINED
SUBARCHITECTURE_DEFINED
H.6.2 Compound statements
if … then … else …
repeat … until …
while … do
for …
case … of …
Procedure and function definitions
H.6.3 Comments
H.7 Miscellaneous helper procedures and functions
H.7.1 ArchVersion()
H.7.2 EndOfInstruction()
H.7.3 GenerateAlignmentException()
H.7.4 GenerateCoprocessorException()
H.7.5 Hint_Debug()
H.7.6 Hint_PreloadData()
H.7.7 Hint_PreloadDataForWrite()
H.7.8 Hint_PreloadInstr()
H.7.9 Hint_Yield()
H.7.10 IntegerZeroDivideTrappingEnabled()
H.7.11 IsExternalAbort()
H.7.12 IsAsyncAbort()
H.7.13 JazelleAcceptsExecution()
H.7.14 LSInstructionSyndrome()
H.7.15 ProcessorID()
H.7.16 RemapRegsHaveResetValues()
H.7.17 ThisInstr()
H.7.18 ThisInstrLength()
I: Pseudocode Index
I.1 Pseudocode operators and keywords
I.2 Pseudocode indexes
J: Registers Index
J.1 Introduction and register disambiguation
J.1.1 Register name disambiguation by Execution state
J.1.2 Register name disambiguation by Exception level
J.2 Alphabetical index of AArch64 registers and system instructions
J.3 Functional index of AArch64 registers and system instructions
J.3.1 Special-purpose registers
J.3.2 VMSA-specific registers
J.3.3 ID registers
J.3.4 Performance monitors registers
J.3.5 Debug registers
J.3.6 Generic timer registers
J.3.7 Generic Interrupt Controller CPU interface registers
J.3.8 Cache maintenance system instructions
J.3.9 Address translation system instructions
J.3.10 TLB maintenance system instructions
J.3.11 Base system registers
J.4 Alphabetical index of AArch32 registers and system instructions
J.5 Functional index of AArch32 registers and system instructions
J.5.1 Special-purpose registers
J.5.2 VMSA-specific registers
J.5.3 ID registers
J.5.4 Performance monitors registers
J.5.5 Debug registers
J.5.6 Generic timer registers
J.5.7 Generic Interrupt Controller CPU interface registers
J.5.8 Cache maintenance system instructions
J.5.9 Address translation system instructions
J.5.10 TLB maintenance system instructions
J.5.11 Legacy feature registers and system instructions
J.5.12 Base system registers
J.6 Alphabetical index of memory-mapped registers
J.7 Functional index of memory-mapped registers
J.7.1 ID registers
J.7.2 Performance monitors registers
J.7.3 Debug registers
J.7.4 Cross-trigger interface registers
Glossary
ARM® Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile
Beta
Copyright © 2013 ARM Limited. All rights reserved.
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ARM Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile
Copyright © 2013 ARM Limited. All rights reserved.
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iii
iv
Copyright © 2013 ARM Limited. All rights reserved.
Non-Confidential - Beta
ARM DDI 0487A.a
ID090413
Contents
ARM Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile
Preface
About this manual ..................................................................................................... xvi
Using this manual ................................................................................................... xviii
Conventions ............................................................................................................ xxiii
Additional reading .................................................................................................... xxv
Feedback ................................................................................................................ xxvi
ARMv8 Architecture Introduction and Overview
Introduction to the ARMv8 Architecture
A1.1
A1.2
A1.3
A1.4
A1.5
A1.6
A1.7
About the ARM architecture ................................................................................. A1-30
Architecture profiles ............................................................................................. A1-32
ARMv8 architectural concepts ............................................................................. A1-33
Supported data types ........................................................................................... A1-36
Floating-point and Advanced SIMD support ........................................................ A1-46
Cryptographic Extension ...................................................................................... A1-52
The ARM memory model ..................................................................................... A1-53
The AArch64 Application Level Architecture
The AArch64 Application Level Programmers’ Model
B1.1
B1.2
B1.3
About the Application level programmers’ model ................................................. B1-58
Registers in AArch64 Execution state .................................................................. B1-59
Software control features and EL0 ....................................................................... B1-65
Part A
Chapter A1
Part B
Chapter B1
ARM DDI 0487A.a
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Copyright © 2013 ARM Limited. All rights reserved.
Non-Confidential - Beta
v
Chapter B2
Part C
Chapter C1
Chapter C2
Chapter C3
Chapter C4
Chapter C5
Chapter C6
The AArch64 Application Level Memory Model
Address space ..................................................................................................... B2-68
B2.1
Memory type overview ........................................................................................ B2-69
B2.2
Caches and memory hierarchy ........................................................................... B2-70
B2.3
Alignment support ............................................................................................... B2-75
B2.4
Endian support .................................................................................................... B2-76
B2.5
Atomicity in the ARM architecture ....................................................................... B2-79
B2.6
Memory ordering ................................................................................................. B2-82
B2.7
Memory types and attributes ............................................................................... B2-89
B2.8
B2.9
Mismatched memory attributes ........................................................................... B2-98
B2.10 Synchronization and semaphores ..................................................................... B2-100
The AArch64 Instruction Set
The A64 Instruction Set
C1.1
C1.2
C1.3
C1.4
Introduction ........................................................................................................ C1-112
Structure of the A64 assembler language ......................................................... C1-113
Address generation ........................................................................................... C1-118
Instruction aliases .............................................................................................. C1-121
A64 Instruction Set Overview
C2.1
C2.2
C2.3
C2.4
C2.5
Branches, Exception generating, and System instructions ............................... C2-124
Loads and stores ............................................................................................... C2-129
Data processing - immediate ............................................................................. C2-140
Data processing - register ................................................................................. C2-145
Data processing - SIMD and floating-point ........................................................ C2-152
A64 Instruction Set Encoding
C3.1
C3.2
C3.3
C3.4
C3.5
C3.6
A64 instruction index by encoding ..................................................................... C3-172
Branches, exception generating and system instructions ................................. C3-173
Loads and stores ............................................................................................... C3-176
Data processing - immediate ............................................................................. C3-193
Data processing - register ................................................................................. C3-196
Data processing - SIMD and floating point ........................................................ C3-203
The AArch64 System Instruction Class
C4.1
C4.2
C4.3
C4.4
C4.5
C4.6
About the System instruction and System register descriptions ....................... C4-230
The System instruction class encoding space .................................................. C4-232
PSTATE and special purpose registers ............................................................ C4-251
A64 system instructions for cache maintenance ............................................... C4-306
A64 system instructions for address translation ................................................ C4-322
A64 system instructions for TLB maintenance .................................................. C4-335
A64 Base Instruction Descriptions
C5.1
C5.2
C5.3
C5.4
C5.5
C5.6
Introduction ........................................................................................................ C5-386
Register size ...................................................................................................... C5-387
Use of the PC .................................................................................................... C5-388
Use of the stack pointer ..................................................................................... C5-389
Condition flags and related instructions ............................................................ C5-390
Alphabetical list of instructions .......................................................................... C5-391
A64 SIMD and Floating-point Instruction Descriptions
C6.1
C6.2
C6.3
Introduction ........................................................................................................ C6-776
About the SIMD and floating-point instructions ................................................. C6-777
Alphabetical list of floating-point and Advanced SIMD instructions ................... C6-779
vi
Copyright © 2013 ARM Limited. All rights reserved.
Non-Confidential - Beta
ARM DDI 0487A.a
ID090413
Part D
Chapter D1
Chapter D2
Chapter D3
Chapter D4
The AArch64 System Level Architecture
The AArch64 System Level Programmers’ Model
Exception levels ............................................................................................... D1-1408
D1.1
Exception terminology ...................................................................................... D1-1409
D1.2
Execution state ................................................................................................ D1-1411
D1.3
Security state ................................................................................................... D1-1412
D1.4
Virtualization .................................................................................................... D1-1414
D1.5
Registers for instruction processing and exception handling ........................... D1-1416
D1.6
Process state, PSTATE ................................................................................... D1-1421
D1.7
Program counter and stack pointer alignment ................................................. D1-1423
D1.8
Reset ................................................................................................................ D1-1426
D1.9
D1.10 Exception entry ................................................................................................ D1-1429
D1.11 Exception return ............................................................................................... D1-1439
D1.12
The Exception level hierarchy .......................................................................... D1-1443
D1.13 Synchronous exception types, routing and priorities ....................................... D1-1450
D1.14 Asynchronous exception types, routing, masking and priorities ...................... D1-1456
D1.15
Trapping functionality to higher Exception levels ............................................. D1-1462
D1.16 System calls ..................................................................................................... D1-1511
D1.17 Use of the ESR_EL1, ESR_EL2, and ESR_EL3 ............................................. D1-1512
D1.18 Mechanisms for entering a low-power state .................................................... D1-1533
D1.19 Self-hosted debug ............................................................................................ D1-1539
D1.20 Performance Monitors extension ..................................................................... D1-1541
D1.21
Interprocessing ................................................................................................ D1-1542
D1.22 Supported configurations ................................................................................. D1-1554
Debug Exceptions
Introduction to debug exceptions ..................................................................... D2-1560
D2.1
Legacy debug exceptions ................................................................................ D2-1564
D2.2
Understanding the descriptions for AArch64 state and AArch32 state ............ D2-1565
D2.3
Software Breakpoint Instruction exceptions ..................................................... D2-1566
D2.4
D2.5
Breakpoint exceptions ...................................................................................... D2-1569
D2.6 Watchpoint exceptions ..................................................................................... D2-1606
Vector Catch exceptions .................................................................................. D2-1627
D2.7
D2.8
Software Step exceptions ................................................................................ D2-1634
Synchronization and debug exceptions ........................................................... D2-1647
D2.9
The Debug Exception Model
D3.1
D3.2
D3.3
D3.4
D3.5
D3.6
D3.7
D3.8
About debug exceptions .................................................................................. D3-1650
The debug exceptions enable controls ............................................................ D3-1651
Routing debug exceptions ............................................................................... D3-1652
Enabling debug exceptions from current Exception level and Security state .. D3-1656
The effect of powerdown on debug exceptions ............................................... D3-1661
Summary of permitted routing and enabling of debug exceptions ................... D3-1662
Debug exception behavior ............................................................................... D3-1665
Pseudocode descriptions of debug exceptions ................................................ D3-1669
The AArch64 System Level Memory Model
D4.1
D4.2
D4.3
D4.4
D4.5
D4.6
D4.7
About the memory system architecture ........................................................... D4-1672
Address space ................................................................................................. D4-1673
Mixed-endian support ...................................................................................... D4-1674
Cache support .................................................................................................. D4-1675
External aborts ................................................................................................. D4-1694
Memory barrier instructions ............................................................................. D4-1696
Pseudocode details of general memory system instructions ........................... D4-1697
Chapter D5
The AArch64 Virtual Memory System Architecture
D5.1
About the Virtual Memory System Architecture (VMSA) .................................. D5-1708
ARM DDI 0487A.a
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Copyright © 2013 ARM Limited. All rights reserved.
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vii
Chapter D6
Chapter D7
Chapter D8
Part E
Chapter E1
Chapter E2
D5.2
D5.3
D5.4
D5.5
D5.6
D5.7
D5.8
The VMSAv8-64 address translation system .................................................. D5-1710
Translation table walk examples ..................................................................... D5-1760
VMSAv8-64 translation table format descriptors ............................................. D5-1772
Access controls and memory region attributes ............................................... D5-1781
MMU faults ...................................................................................................... D5-1796
Translation Lookaside Buffers (TLBs) ............................................................. D5-1804
Caches in a VMSA implementation ................................................................. D5-1818
The Performance Monitors Extension
About the Performance Monitors ..................................................................... D6-1822
D6.1
Accuracy of the Performance Monitors ........................................................... D6-1824
D6.2
Behavior on overflow ....................................................................................... D6-1826
D6.3
Attributability .................................................................................................... D6-1828
D6.4
Effect of EL3 and EL2 ..................................................................................... D6-1829
D6.5
Event filtering ................................................................................................... D6-1831
D6.6
Performance Monitors and Debug state .......................................................... D6-1832
D6.7
Counter enables .............................................................................................. D6-1833
D6.8
D6.9
Counter access ............................................................................................... D6-1834
D6.10 Event numbers and mnemonics ...................................................................... D6-1836
D6.11 Performance Monitors Extension registers ..................................................... D6-1851
D6.12 Pseudocode details ......................................................................................... D6-1854
The Generic Timer
D7.1
D7.2
About the Generic Timer ................................................................................. D7-1856
About the Generic Timer registers .................................................................. D7-1864
AArch64 System Register Descriptions
D8.1
D8.2
D8.3
D8.4
D8.5
D8.6
About the AArch64 System registers .............................................................. D8-1866
General system control registers ..................................................................... D8-1870
Debug registers ............................................................................................... D8-2077
Performance Monitors registers ...................................................................... D8-2134
Generic Timer registers ................................................................................... D8-2170
Generic Interrupt Controller CPU interface registers ....................................... D8-2194
The AArch32 Application Level Architecture
The AArch32 Application Level Programmers’ Model
E1.1
E1.2
E1.3
E1.4
E1.5
About the Application level programmers’ model ............................................ E1-2288
Additional information about the programmers’ model in AArch32 state ......... E1-2289
Advanced SIMD and floating-point instructions ............................................... E1-2303
Coprocessor support ....................................................................................... E1-2331
Exceptions and debug events ......................................................................... E1-2332
The AArch32 Application Level Memory Model
Address space ................................................................................................. E2-2334
E2.1
Memory type overview .................................................................................... E2-2336
E2.2
Caches and memory hierarchy ....................................................................... E2-2337
E2.3
Alignment support ........................................................................................... E2-2341
E2.4
Endian support ................................................................................................ E2-2343
E2.5
Atomicity in the ARM architecture ................................................................... E2-2346
E2.6
Memory ordering ............................................................................................. E2-2350
E2.7
Memory types and attributes ........................................................................... E2-2357
E2.8
E2.9
Mismatched memory attributes ....................................................................... E2-2366
E2.10 Synchronization and semaphores ................................................................... E2-2369
viii
Copyright © 2013 ARM Limited. All rights reserved.
Non-Confidential - Beta
ARM DDI 0487A.a
ID090413
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