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SystemVerilog for Design(Second Edition).pdf
Contents
chapter 1 introduction to systemverilog
1.1 SystemVerilog origins
1.2 Key enhancements for hardware design
1.3 summary
chapter 2 declaration spaces
2.1 package
2.2 $unit compilation
2.3 declarations in unnamed statement blocks
2.4 sumulation time units and precision
2.5 summary
chapter 3 liteeral values and built-in data types
3.1 enhanced literal value assignments
3.2 `define enhancements
3.3 systemverilog variables
3.4 using 2-state types in RTL models
3.5 relaxation of type rules
3.6 signed and unsigned modifiers
3.7 static and automatic variables
3.8 deterministic variable initialization
3.9 type casting
3.10 Constants
3.11 summary
chapter 4 user defined and enumerated types
4.1 user defined types
4.2 enumerated types
4.3 summary
chapter 5 arrays, structres and unions
5.1 structures
5.2 unions
5.3 arrays
5.4 the foreach array looping construct
5.5 array querying system functions
5.6 the $bits "sizeof" system function
5.7 synamic arrays, associative arrays, sparse arrays and strings
5.8 summary
chapter 6 procedural blocks, tasks and functions
6.1 verilog general purpose always procedural block
6.2 specialized procedural blocks
6.3 enhancements to tasks and functions
6.4 summary
Ch7 Procedural Statements
7.1 new operators
7.2 operand enhancements
7.3 enhanced for loops
7.4 bottom testing do...while loop
7.5 the foreach array looping construct
7.6 new jump statements - break, continue, return
7.7 enhanced block names
7.8 statement labels
7.9 enhanced case statements
7.10 enhanced if...else decisions
7.11 summary
chapter 8 modeling finit state machines with systemverilog
8.1 modeling state machines with enumerated types
8.2 using 2-state types in FSM models
8.3 summary
chapter 9 design hierarchy
9.1 module prototypes
9.2 named ending statements
9.3 nested(local) module declarations
9.4 simplified netlists of module instances
9.5 net aliasing
9.6 passing values through module ports
9.7 reference ports
9.8 enhanced port declarations
9.9 parameterized types
9.10 summary
chapter 10 interfaces
10.1 interface concepts
10.2 interface declarations
10.3 using interfaces as module ports
10.4 instantiating and connecting interfaces
10.5 referencing signals within an interface
10.6 interface modports
10.7 using tasks and functions in interfaces
10.8 using procedural blocks in interfaces
10.9 reconfigurable interfaces
10.10 verification with interfaces
10.11 summary
chapter 11 a complete design modeled with systemverilog
11.1 ATM example
11.2 data abstraction
11.3 interface encapsulation
11.4 design top level: squat
11.5 receivers and transmitters
11.6 testbench
11.7 summary
chapter 12 behavioral and transaction level modeling
12.1 behavioral modeling
12.2 what is a transaction
12.3 transaction level modeling in systemverilog
12.4 transaction level models via interfaces
12.5 bus arbitration
12.6 transactors, adapters, and bus functional models
12.7 more complex transactions
12.8 summary
appendix a the systemverilog formal definition
SystemVerilog
For Design
Second Edition
A Guide to Using SystemVerilog
for Hardware Design and Modeling
SystemVerilog
For Design
Second Edition
A Guide to Using SystemVerilog
for Hardware Design and Modeling
by
Stuart Sutherland
Simon Davidmann
Peter Flake
Foreword by Phil Moorby
1 3
Stuart Sutherland
Sutherland DHL, Inc.
22805 SW 92nd Place
Tualatin, OR 97062
USA
Simon Davidmann
The Old Vicerage
Priest End
Thame, Oxfordshire 0X9 3AB
United Kingdom
Peter Flake
Imperas, Ltd.
Imperas Buildings, North Weston
Thame, Oxfordshire 0X9 2HA
United Kingdom
SystemVerilog for Design, Second Edition
A Guide to Using SystemVerilog for Hardware Design and Modeling
Library of Congress Control Number: 2006928944
ISBN-10: 0-387-33399-1
ISBN-13: 9780387333991
e-ISBN-10: 0-387-36495-1
e-ISBN-13: 9780387364957
Printed on acid-free paper.
© 2006 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as to
whether or not they are subject to proprietary rights.
Printed in the United States of America.
9 8 7 6 5 4 3 2
springer.com
Dedications
To my wonderful wife, LeeAnn, and my children, Ammon, Tamara, Hannah, Seth and
Samuel — thank you for all your patience during the many long hours and late nights
while writing this book.
Stuart Sutherland
Portland, Oregon
To all of the staff of Co-Design and the many EDA colleagues that worked with me
over the years — thank you for helping to evolve Verilog and make its extension and
evolution a reality. And to Penny, Emma and Charles — thank you for allowing me
the time to indulge in language design (and in cars and guitars...).
Simon Davidmann
Santa Clara, California
To my wife Monique, for supporting me when I was not working, and when I was
working too much.
Peter Flake
Thame, UK
Table of Contents
Foreword ................................................................................................................. xxi
Preface ................................................................................................................... xxiii
Target audience...................................................................................................................... xxiii
Topics covered........................................................................................................................xxiv
About the examples in this book..............................................................................................xxv
Obtaining copies of the examples...........................................................................................xxvi
Example testing.......................................................................................................................xxvi
Other sources of information .................................................................................................xxvii
Acknowledgements..................................................................................................................xxx
Chapter 1: Introduction to SystemVerilog...............................................................1
1.1
SystemVerilog origins.......................................................................................................1
1.1.1 Generations of the SystemVerilog standard.......................................................2
1.1.2 Donations to SystemVerilog ..............................................................................4
1.2 Key SystemVerilog enhancements for hardware design...................................................5
1.3
Summary ...........................................................................................................................6
Chapter 2: SystemVerilog Declaration Spaces ........................................................7
Packages ...........................................................................................................................8
2.1
2.1.1
Package definitions ............................................................................................9
2.1.2 Referencing package contents..........................................................................10
2.1.3
Synthesis guidelines.........................................................................................14
$unit compilation-unit declarations.................................................................................14
2.2.1 Coding guidelines.............................................................................................17
SystemVerilog identifier search rules ..............................................................17
2.2.2
2.2.3
Source code order.............................................................................................17
2.2.4 Coding guidelines for importing packages into $unit......................................19
2.2.5
Synthesis guidelines.........................................................................................25
2.3 Declarations in unnamed statement blocks .....................................................................26
2.3.1 Local variables in unnamed blocks..................................................................27
Simulation time units and precision ................................................................................28
2.4.1 Verilog’s timescale directive............................................................................28
2.4.2 Time values with time units .............................................................................30
2.4.3
Scope-level time unit and precision .................................................................31
2.2
2.4
3.3
3.5
3.6
3.7
2.4.4 Compilation-unit time units and precision.......................................................32
2.5
Summary .........................................................................................................................34
Chapter 3: SystemVerilog Literal Values and Built-in Data Types.....................37
Enhanced literal value assignments.................................................................................38
3.1
‘define enhancements......................................................................................................39
3.2
3.2.1 Macro argument substitution within strings.....................................................39
3.2.2 Constructing identifier names from macros.....................................................41
SystemVerilog variables..................................................................................................42
3.3.1 Object types and data types..............................................................................42
3.3.2
SystemVerilog 4-state variables.......................................................................43
3.3.3
SystemVerilog 2-state variables.......................................................................44
3.3.4 Explicit and implicit variable and net data types .............................................47
3.3.5
Synthesis guidelines.........................................................................................48
3.4 Using 2-state types in RTL models .................................................................................48
2-state type characteristics ...............................................................................49
3.4.1
3.4.2
2-state types versus 2-state simulation.............................................................49
3.4.3 Using 2-state types with case statements .........................................................51
Relaxation of type rules...................................................................................................52
Signed and unsigned modifiers .......................................................................................55
Static and automatic variables.........................................................................................56
3.7.1
Static and automatic variable initialization ......................................................59
3.7.2
Synthesis guidelines for automatic variables ...................................................60
3.7.3 Guidelines for using static and automatic variables.........................................61
3.8 Deterministic variable initialization ................................................................................61
Initialization determinism ................................................................................61
3.8.1
3.8.2
Initializing sequential logic asynchronous inputs ............................................65
Type casting ....................................................................................................................67
3.9.1
Static (compile time) casting............................................................................67
3.9.2 Dynamic casting...............................................................................................69
Synthesis guidelines.........................................................................................70
3.9.3
3.10 Constants .........................................................................................................................71
3.11 Summary .........................................................................................................................72
Chapter 4: SystemVerilog User-Defined and Enumerated Types .......................75
4.1 User-defined types...........................................................................................................75
4.1.1 Local typedef definitions..................................................................................76
4.1.2
Shared typedef definitions................................................................................76
4.1.3 Naming convention for user-defined types ......................................................78
Enumerated types ............................................................................................................79
4.2.1 Enumerated type label sequences.....................................................................83
3.9
4.2
viii
4.2.2 Enumerated type label scope............................................................................83
4.2.3 Enumerated type values ...................................................................................84
4.2.4 Base type of enumerated types.........................................................................85
4.2.5 Typed and anonymous enumerations...............................................................86
4.2.6
Strong typing on enumerated type operations..................................................86
4.2.7 Casting expressions to enumerated types.........................................................88
4.2.8
Special system tasks and methods for enumerated types.................................89
4.2.9
Printing enumerated types................................................................................92
4.3
Summary .........................................................................................................................93
Chapter 5: SystemVerilog Arrays, Structures and Unions ..................................95
Structures.........................................................................................................................96
5.1
5.1.1
Structure declarations.......................................................................................97
5.1.2 Assigning values to structures..........................................................................98
5.1.3
Packed and unpacked structures.....................................................................101
Passing structures through ports.....................................................................104
5.1.4
Passing structures as arguments to tasks and functions .................................105
5.1.5
5.1.6
Synthesis guidelines.......................................................................................105
5.2 Unions ...........................................................................................................................105
5.2.1 Unpacked unions............................................................................................106
5.2.2 Tagged unions ................................................................................................108
5.2.3
Packed unions.................................................................................................109
5.2.4
Synthesis guidelines.......................................................................................111
5.2.5 An example of using structures and unions ...................................................111
5.3 Arrays ............................................................................................................................113
5.3.1 Unpacked arrays.............................................................................................113
5.3.2
Packed arrays .................................................................................................116
5.3.3 Using packed and unpacked arrays................................................................118
5.3.4
Initializing arrays at declaration.....................................................................119
5.3.5 Assigning values to arrays .............................................................................121
5.3.6 Copying arrays ...............................................................................................123
5.3.7 Copying arrays and structures using bit-stream casting.................................124
5.3.8 Arrays of arrays..............................................................................................125
5.3.9 Using user-defined types with arrays.............................................................126
5.3.10 Passing arrays through ports and to tasks and functions................................127
5.3.11 Arrays of structures and unions......................................................................128
5.3.12 Arrays in structures and unions......................................................................128
5.3.13 Synthesis guidelines.......................................................................................128
5.3.14 An example of using arrays............................................................................129
The foreach array looping construct..............................................................................130
5.4
ix
6.3
5.5 Array querying system functions ..................................................................................132
5.6
The $bits “sizeof” system function ...............................................................................134
5.7 Dynamic arrays, associative arrays, sparse arrays and strings ......................................135
5.8
Summary .......................................................................................................................136
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions ................137
6.1 Verilog general purpose always procedural block ........................................................138
SystemVerilog specialized procedural blocks...............................................................142
6.2
6.2.1 Combinational logic procedural blocks .........................................................142
6.2.2 Latched logic procedural blocks ....................................................................150
6.2.3
Sequential logic procedural blocks ................................................................152
6.2.4
Synthesis guidelines.......................................................................................152
Enhancements to tasks and functions............................................................................153
6.3.1
Implicit task and function statement grouping...............................................153
6.3.2 Returning function values ..............................................................................153
6.3.3 Returning before the end of tasks and functions............................................154
6.3.4 Void functions................................................................................................155
6.3.5
Passing task/function arguments by name .....................................................156
6.3.6 Enhanced function formal arguments ............................................................157
6.3.7
Functions with no formal arguments..............................................................158
6.3.8 Default formal argument direction and type ..................................................158
6.3.9 Default formal argument values.....................................................................159
6.3.10 Arrays, structures and unions as formal arguments .......................................160
6.3.11 Passing argument values by reference instead of copy..................................161
6.3.12 Named task and function ends .......................................................................165
6.3.13 Empty tasks and functions .............................................................................166
6.4
Summary .......................................................................................................................166
Chapter 7: SystemVerilog Procedural Statements..............................................169
7.1 New operators................................................................................................................170
7.1.1
Increment and decrement operators ...............................................................170
7.1.2 Assignment operators.....................................................................................173
7.1.3 Equality operators with don’t care wildcards.................................................176
7.1.4
Set membership operator — inside................................................................178
7.2 Operand enhancements..................................................................................................180
7.2.1 Operations on 2-state and 4-state types..........................................................180
7.2.2 Type casting ...................................................................................................180
7.2.3
Size casting.....................................................................................................181
7.2.4
Sign casting ....................................................................................................182
Enhanced for loops........................................................................................................182
7.3.1 Local variables within for loop declarations..................................................183
7.3
x
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