BCM89811 DATASHEET.pdf

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BCM89811 Preliminary Data Shee

Revision History

Table of Contents

List of Figures

List of Tables

About This Document

Purpose and Audience

Acronyms and Abbreviations

Document Conventions

References

Technical Support

Section 1: Functional Description

Overview

Media Independent Interface

Reduced Gigabit Media Independent Interface

Reduced Media Independent Interface

BroadR-Reach

Management Interface

Encoder

Link Monitor

Digital Adaptive Equalizer

Echo Canceler

Analog-to-Digital Converter

Clock Recovery/Generator

Baseline Wander Correction

Multimode Transmit Digital-to-Analog Converter

Stream Cipher and Radiated Emissions Control Features

BroadR-Reach Mode

Energy Detect

Power-Down Modes

IEEE 1588 Support

Event Message

Grandmaster Clock

SC Support

IEEE 1588 Frame Formats

Section 2: Hardware Signal Descriptions

Section 3: Pinout

Section 4: Operational Description

Reset

PHY Address

Isolate Mode

Standby Power-Down Mode

Sleep Mode

Wake and Sleep Functions

INH

WAKE

TRD+, TRD– (BroadR-Reach Dataline)

AVDD_PPD

Application Example

Internal Loopback Mode

RGMII Interface

MII Interface

RMII Interface

Broadcom Serial Control (BSC) Interface

Signal Quality Indicator

General-Purpose LED Programmability

36-Pin QFN Package Hardware Configuration

JTAG Mode

PHY Address

RGMII/MII-Lite/RMII Modes

Interrupt Function

LED Modes

Section 5: Register Overview

MII Management Interface Clause 22 Register Programming

Preamble (PRE)

Start of Frame (ST)

Operation Code (OP)

PHY Address (PHYAD)

Turnaround (TA)

Data

PHY Core Addressing Methods

IEEE Standard (0x00–0x0F) Registers

RDB Access Method

BroadR-Reach LRE Register Descriptions

Reset

Internal Loopback

Reserved

Power-Down

Isolate

Speed Selection

Pair Selection

Master/Slave Selection

100 Mbps One-Pair Capable

Extended Status

Support IEEE 802.3 PHY

Link Status

Receive Jabber Detect

Extended Capability

Test Mode Descriptions

Registers 04h, 06h–0Eh: Reserved

Local Receiver Status

Remote Receiver Status

Idle Error Count

Auxiliary Register Descriptions

BroadR-Reach Extended Control Register (RDB Register 0x00)

Transmit Disable

Interrupt Disable

Force Interrupt

Enable LED Traffic Mode

Force LEDs On

Force LEDs Off

BroadR-Reach PCS Transmit FIFO Elasticity (Copper Mode)

BroadR-Reach PHY Extended Status (RDB Register 0x01)

Interrupt Status

Remote Receiver Status

Local Receiver Status

Locked

Link Status

CRC Error Detected

Carrier Extension Error Detected

Bad SSD Detected (False Carrier)

Bad ESD Detected (Premature End)

Receive Error Detected

Transmit Error Detected

Lock Error Detected

BroadR-Reach Receive Error Counter (RDB Register 0x02)

Receive Error Counter

BroadR-Reach False Carrier Sense Counter (RDB Register 0x03)

False Carrier Sense Counter

BroadR-Reach Receiver NOT_OK Counter (RDB Register 0x04)

Local Receiver NOT_OK Counter

Remote Receiver NOT_OK Counter

Interrupt Status RDB Register 0x0A)

Energy Detect Change

Illegal Pair Swap

Exceeded High Counter Threshold

Exceeded Low Counter Threshold

Scrambler Synchronization Error

Remote Receiver Status Change

Local Receiver Status Change

Duplex Mode Change

Link Speed Change

Link Status Change

CRC Error

Interrupt Mask (RDB Register 0x0B)

Interrupt Mask Vector

RDB Access Registers

Clock Alignment Control (RDB Register 0x013)

Reserved bit 15

Shadow Register Selector

GTXCLK Clock Delay Enable

LED Status (RDB Register 0x018)

Reserved bit 15

Shadow Register Selector

INTR Indicator

LINKSPD Indicator

Transmit Indicator

Receive Indicator

LED Control (RDB Register 0x019)

Reserved bit 15

Shadow Register Selector

Activity/Link LED Enable

ACTIVITY LED Enable

External Control (RDB Register 0x01A)

Reserved bit 15

Shadow Register Selector

Freeze AGC at Link

RGMII Pad Configuration These two bits determine the operating voltage of the RGMII pads. The default values for these register bits are determined by the LED3 and LED2 pins during reset, as shown in Table 36. LED Selector 1 (RDB Register 0x01D)

Reserved bit 15

Shadow Register Selector

Reserved

LED1 Selector

Auxiliary Control Register (RDB Register 0x028)

External Loopback

Extended Packet Length

DSP Clock Enable

Transmit Mode

Shadow Register Select

Power/MII Control Register (RDB Register 0x02A)

Super Isolate

Shadow Register Select

Miscellaneous Test Register (RDB Register 0x02C)

Line-Side [Remote] Loopback Enable

Line-Side [Remote] Loopback Tristate

Shadow Register Select

Miscellaneous Control (RDB Register 0x02F)

Write Enable (Bits 11:3)

Shadow Register Read Selector

Packet Counter Mode

Bypass Wirespeed Timer

RGMII RXD to RXC Skew

RGMII Enable

Shadow Register Select

Expansion Register 90h: BroadR-Reach LRE Misc Control RDB Register 0x300

BroadR-Reach Enable

Reverse MII Control RDB Register 0x30F

Restart Reverse MII Receive FIFO

Restart Reverse MII Transmit FIFO

Reverse MII Mode Enable

COPPER_MISCELLANEOUS_CONTROL Register (RDB Register 0x02F)

RX_TX_PACKET_COUNTER Register (RDB Register 0x030)

SOFT_RESET Register (RDB Register 0x070)

BroadR-Reach LRE Misc Control (RDB Register 0x300)

Digital High Pass Filter

BroadR-Reach Force Link Control

BroadR-Reach Enable

Sleep Mode Control (RDB Register 0x07F)

EN Pin Disable

Sleep Mode Enable

RDB_ACCESS_MODE Register (RDB Register 0x087)

TIME_SYNC Register (RDB Register 0x0F5)

Enhanced Cable Diagnostic Register Set (RDB Registers 0x2A0–0x2AF)

ECD_CONTROL_AND_STATUS Register (RDB Register 0x2A0)

ECD_FAULT_TYPE Register (RDB Register 0x2A1)

ECD_PAIR_A_LENGTH_RESULTS Register (RDB Register 0x2A2)

Top Level Register Set (RDB Registers 0x800–0x8FF)

TOP_LEVEL_CONFIGURATION Register (RDB Register 0x810)

1588 Function Register Set (RDB Registers 0x200–0x2FF)

P1588_SLICE_ENABLE_CONTROL Register (RDB Register 0x210)

P1588_PORT0_TX_EVENT_MESSAGE_MODE_SELECTION Register (RDB Register 0x211)

P1588_PORT0_RX_EVENT_MESSAGE_MODE_SELECTION Register (RDB Register 0x219)

P1588_TX_SOP_TIMESTAMP_CAPTURE_ENABLE Register (RDB Register 0x221)

P1588_RX_SOP_TIMESTAMP_CAPTURE_ENABLE Register (RDB Register 0x222)

P1588_RX_AND_TX_OPTION Register (RDB Register 0x223)

P1588_PORT0_RX_LINK_DELAY_LSB Register (RDB Register 0x224)

P1588_PORT0_RX_LINK_DELAY_MSB Register (RDB Register 0x225)

P1588_PORT0_RX_TIMESTAMP_OFFSET_LSB Register (RDB Register 0x234)

P1588_PORT0_RX_TIMESTAMP_OFFSET_MSB Register (RDB Register 0x235)

P1588_PORT0_TX_TIMESTAMP_OFFSET_LSB Register (RDB Register 0x244)

P1588_PORT0_TX_TIMESTAMP_OFFSET_MSB Register (RDB Register 0x245)

P1588_ORIGINAL_TIME_CODE_0 Register (RDB Register 0x254)

P1588_ORIGINAL_TIME_CODE_1 Register (RDB Register 0x255)

P1588_ORIGINAL_TIME_CODE_2 Register (RDB Register 0x256)

P1588_ORIGINAL_TIME_CODE_3 Register (RDB Register 0x257)

P1588_ORIGINAL_TIME_CODE_4 Register (RDB Register 0x258)

P1588_DPLL_DEBUG_LSB Register (RDB Register 0x259)

P1588_DPLL_DEBUG_MSB Register (RDB Register 0x25A)

P1588_DPLL_DEBUG_SELECT Register (RDB Register 0x25B)

P1588_SHADOW_REGISTER_CONTROL Register (RDB Register 0x25C)

P1588_SHADOW_REGISTER_LOAD Register (RDB Register 0x25D)

P1588_INTERRUPT_MASK Register (RDB Register 0x25E)

P1588_INTERRUPT_STATUS Register (RDB Register 0x25F)

P1588_TRANSMIT_CONTROL Register (RDB Register 0x260)

P1588_RECEIVE_CONTROL Register (RDB Register 0x261)

P1588_RECEIVE_TRANSMIT_CONTROL Register (RDB Register 0x262)

P1588_VLAN_1TAGS_ITPID Register (RDB Register 0x263)

P1588_VLAN_2TAGS_OTPID Register (RDB Register 0x264)

P1588_VLAN_2TAGS_OTHER_OTPID Register (RDB Register 0x265)

P1588_NSE_DPLL_1 Register (RDB Register 0x266)

P1588_NSE_DPLL_2(0) Register (RDB Register 0x267)

P1588_NSE_DPLL_2(1) Register (RDB Register 0x268)

P1588_NSE_DPLL_2(2) Register (RDB Register 0x269)

P1588_NSE_DPLL_3_LSB Register (RDB Register 0x26A)

P1588_NSE_DPLL_3_MSB Register (RDB Register 0x26B)

P1588_NSE_DPLL _4 Register (RDB Register 0x26C)

P1588_NSE_DPLL _5 Register (RDB Register 0x26D)

P1588_NSE_DPLL _6 Register (RDB Register 0x26E)

P1588_NSE_DPLL_7(0) Register (RDB Register 0x26F)

P1588_NSE_DPLL_7(1) Register (RDB Register 0x270)

P1588_NSE_DPLL_7(2) Register (RDB Register 0x271)

P1588_NSE_DPLL_7(3) Register (RDB Register 0x272)

P1588_NSE_DPLL_NCO_1_LSB Register (RDB Register 0x273)

P1588_NSE_DPLL_NCO_1_MSB Register (RDB Register 0x274)

P1588_NSE_DPLL_NCO_2(0) Register (RDB Register 0x275)

P1588_NSE_DPLL_NCO_2(1) Register (RDB Register 0x276)

P1588_NSE_DPLL_NCO_2(2) Register (RDB Register 0x277)

P1588_NSE_DPLL_NCO_3(0) Register (RDB Register 0x278)

P1588_NSE_DPLL_NCO_3(1) Register (RDB Register 0x279)

P1588_NSE_DPLL_NCO_3(2) Register (RDB Register 0x27A)

P1588_NSE_DPLL_NCO_4 Register (RDB Register 0x27B)

P1588_NSE_DPLL_NCO_5(0) Register (RDB Register 0x27C)

P1588_NSE_DPLL_NCO_5(1) Register (RDB Register 0x27D)

P1588_NSE_DPLL_NCO_5(2) Register (RDB Register 0x27E)

P1588_NSE_DPLL_NCO_6 Register (RDB Register 0x27F)

P1588_NSE_DPLL_NCO_7(0) Register (RDB Register 0x280)

P1588_NSE_DPLL_NCO_7(1) Register (RDB Register 0x281)

P1588_TX_COUNTER Register (RDB Register 0x282)

P1588_RX_COUNTER Register (RDB Register 0x283)

P1588_RX_TX_1588_COUNTER Register (RDB Register 0x284)

P1588_TIMESTAMP_READ_START_END Register (RDB Register 0x285)

P1588_HEARTBEAT_0 Register (RDB Register 0x286)

P1588_HEARTBEAT_1 Register (RDB Register 0x287)

P1588_HEARTBEAT_2 Register (RDB Register 0x288)

P1588_TIME_STAMP_0 Register (RDB Register 0x289)

P1588_TIME_STAMP_1 Register (RDB Register 0x28A)

P1588_TIME_STAMP_2 Register (RDB Register 0x28B)

P1588_TIME_STAMP_INFO_1 Register (RDB Register 0x28C)

P1588_TIME_STAMP_INFO_2 Register (RDB Register 0x28D)

P1588_CONTROL_DEBUG Register (RDB Register 0x28E)

P1588_CPU_TX_AND_RX_PORT_ENABLE Register (RDB Register 0x28F)

P1588_DA1 Register (RDB Register 0x290)

P1588_DA2 Register (RDB Register 0x291)

P1588_DA3 Register (RDB Register 0x292)

P1588_RX_TX_CPU_1588_COUNTER Register (RDB Register 0x2BF)

P1588_TIMECODE_SEL Register (RDB Register 0x2C3)

P1588_TIME_STAMP_3 Register (RDB Register 0x2C4)

P1588_CONTROL_DEBUG Register (RDB Register 0x2C5)

P1588_DELAY_MEASURMENT_TX_CONTROL Register (RDB Register 0x2C6)

P1588_DELAY_MEASURMENT_RX_CONTROL Register (RDB Register 0x2C7)

P1588_DELAY_MEASURMENT_ETYPE1 Register (RDB Register 0x2C8)

P1588_DELAY_MEASURMENT_ETYPE2 Register (RDB Register 0x2C9)

P1588_DELAY_MEASURMENT_ETYPE3 Register (RDB Register 0x2CA)

P1588_DELAY_MEASURMENT_ETYPE4 Register (RDB Register 0x2CB)

P1588_DELAY_MEASURMENT_ETYPE5 Register (RDB Register 0x2CC)

P1588_DELAY_MEASURMENT_ETYPE6 Register (RDB Register 0x2CD)

P1588_DELAY_MEASURMENT_ETYPE7 Register (RDB Register 0x2CE)

P1588_DELAY_MEASURMENT_ETYPE8 Register (RDB Register 0x2CF)

P1588_DELAY_MEASURMENT_ETYPE9 Register (RDB Register 0x2D0)

P1588_DELAY_MEASURMENT_ETYPE10 Register (RDB Register 0x2D1)

P1588_DELAY_MEASURMENT_ETYPE11 Register (RDB Register 0x2D2)

P1588_DELAY_MEASURMENT_ETYPE12 Register (RDB Register 0x2D3)

P1588_DELAY_MEASURMENT_ETYPE13 Register (RDB Register 0x2D4)

P1588_DELAY_MEASURMENT_IETF_OFFSET Register (RDB Register 0x2D5)

P1588_NTP_COUNTER_TIME_STAMP0 Register (RDB Register 0x2D6)

P1588_NTP_COUNTER_TIME_STAMP1 Register (RDB Register 0x2D7)

P1588_NTP_COUNTER_TIME_STAMP2 Register (RDB Register 0x2D8)

P1588_NTP_COUNTER_TIME_STAMP3 Register (RDB Register 0x2D9)

P1588_NTP_NCO_FREQUENCY0 Register (RDB Register 0x2DA)

P1588_NTP_NCO_FREQUENCY1 Register (RDB Register 0x2DB)

P1588_NTP_DOWN_COUNTER_0 Register (RDB Register 0x2DC)

P1588_NTP_DOWN_COUNTER_1 Register (RDB Register 0x2DD)

P1588_NTP_ERR_LSB Register (RDB Register 0x2DE)

P1588_NTP_ERR_MSB Register (RDB Register 0x2DF)

P1588_DM_MAC_ADDRESS_LOCAL1_0 Register (RDB Register 0x2E0)

P1588_DM_MAC_ADDRESS_LOCAL1_1 Register (RDB Register 0x2E1)

P1588_DM_MAC_ADDRESS_LOCAL1_2 Register (RDB Register 0x2E2)

P1588_DM_MAC_ADDRESS_LOCAL2_0 Register (RDB Register 0x2E3)

P1588_DM_MAC_ADDRESS_LOCAL2_1 Register (RDB Register 0x2E4)

P1588_DM_MAC_ADDRESS_LOCAL2_2 Register (RDB Register 0x2E5)

P1588_DM_MAC_ADDRESS_LOCAL3_0 Register (RDB Register 0x2E6)

P1588_DM_MAC_ADDRESS_LOCAL3_1 Register (RDB Register 0x2E7)

P1588_DM_MAC_ADDRESS_LOCAL3_2 Register (RDB Register 0x2E8)

P1588_DM_MAC_CONTROL_0 Register (RDB Register 0x2E9)

P1588_DM_MAC_CONTROL_1 Register (RDB Register 0x2EA)

P1588_HEARTBEAT_3 Register (RDB Register 0x2EC)

P1588_HEARTBEAT_4 Register (RDB Register 0x2ED)

P1588_INBAND_CONTROL_PORT0 Register (RDB Register 0x2EE)

P1588_MEMORY_COUNTER Register (RDB Register 0x2F6)

P1588_TIMESTAMP_DELTA Register (RDB Register 0x2F7)

P1588_SOP_SELECTION Register (RDB Register 0x2F8)

P1588_TIME_STAMP_INFO_3 Register (RDB Register 0x2F9)

P1588_TIME_STAMP_INFO_4 Register (RDB Register 0x2FA)

P1588_TIME_STAMP_INFO_5 Register (RDB Register 0x2FB)

P1588_TIME_STAMP_INFO_6 Register (RDB Register 0x2FC)

P1588_TIME_STAMP_INFO_7 Register (RDB Register 0x2FD)

P1588_TIME_STAMP_INFO_8 Register (RDB Register 0x2FE)

P1588_INBAND_SPARE1 Register (RDB Register 0x2FF)

Receive/Transmit Packet Counter (RDB Register 0x030)

Packet Counter

Section 6: Timing and AC Characteristics

Clock Input Timing

Management Interface Timing

MII 100 Mbps Transmit Timing

MII 100 Mbps Receive Timing

RGMII Input Timing

RGMII Output Timing

Normal Mode

Delayed Mode

RMII Timing

Section 7: Electrical Characteristics

Section 8: Power Requirements

Section 9: Mechanical and Thermal

RoHS-Compliant Packaging

Mechanical Information

Thermal Information

Section 10: Ordering Information

Appendix A: Acronyms and Abbreviations

Preliminary Data Sheet BCM89811 BroadR-Reach® Single-Port Automotive Ethernet Transceiver GENERAL DESCRIPTION The Broadcom® BCM89811 is a 100 Mbps automotive Ethernet transceiver integrated into a single monolithic CMOS chip. The device performs all of the physical layer (PHY) functions for BroadR-Reach® encoded Ethernet packets over single-pair unshielded twisted-pair copper wire, such as FlexRay. The BCM89811 is designed to exceed automotive specifications for noise cancellation and transmission jitter, providing consistent and reliable operation over the broadest range of existing single twisted-pair automotive cable plants. The BCM89811 is based on Broadcom’s proven digital-signal processor technology, combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, and all other required support circuitry. The BCM89811 is designed to be fully compliant with RGMII, MII, and RMII interface specifications, allowing compatibility with industry-standard Ethernet media access controllers (MACs) and switch controllers. BroadR-Reach enables the BCM89811 to link up with BroadR-Reach compliant link partners. Integrated low-pass filter Integrated twisted-pair termination resistors FEATURES • Single-chip integrated Ethernet transceiver • Support for 100 Mbps single-pair BroadR-Reach • • Trace matched output impedance • • Line loopback • Low EMI emissions and high immunity • Automotive Cable Diagnostics support • Polarity detection and auto/manual correction • Robust cable ESD (CESD) tolerance • Support for packets up to 1.5 KB • Advanced low-power management with local and remote wake-up support Integrated LDO regulator allowing a single supply IEEE 1149.1 (JTAG) boundary scan • • • Super Isolate mode • 36-pin QFN package (with Wettable Flanks) • Automotive Temperature Range: –40°C to +125°C ambient (Grade 1) APPLICATIONS • Automotive Ethernet 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 7/18/2016 WNT2V 89811-DS104-R January 22, 2016

Figure 1: Functional Block Diagram TRD+ TRD- TX DAC Baseline Wander Correction Echo Canceler Symbol Encoder TXD[3:0] TX_EN GTXCLK PGA ADC Equalizer DFE Decoder Symbol Encoder/ Aligner RXD[3:0] RX_DV RXC XTALI XTALO TVCOI RDAC Clock Generator BIAS Generator Timing & Phase Recovery MII Registers LED Driver Int_n/LED MII Management Control MDC MDIO Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2016 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, and BroadR-Reach® are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON- INFRINGEMENT. 7/18/2016 WNT2V

“Energy Detect” on page 33 “Standby Power-Down Mode” on page 47 “Sleep Mode” on page 47 “EN” on page 48 “RGMII Interface” on page 53 “Signal Quality Indicator” on page 56 “General-Purpose LED Programmability” on page 57 Change Description Updated: • • Table 6: “Hardware Signal Descriptions,” on page 42 • Figure 6: “36-Pin QFN Pinout Diagram, Top View,” on page 45 • • • • • • • Table 13: “Programmable LEDs,” on page 57 • Figure 11: “Programmable LED Multiplexer,” on page 57 • • Table 19: “Register Map,” on page 64 • • • Table 50: “ECD_CONTROL_AND_STATUS Register,” on page 98 • Table 51: “ECD_FAULT_TYPE Register,” on page 99 • Table 109: “P1588_NSE_DPLL_NCO_6 Register,” on page 143 • Table 187: “MII 100 Mbps Transmit Timing,” on page 172 • Table 189: “RGMII Input Timing (Normal Mode): GTXCLK and TXD “Register Notations” on page 68 “RDB Access Registers” on page 82 “PHY Address” on page 58 BCM89811 Preliminary Data Sheet Revision History Revision History Revision BCM89811-DS104-R 01/22/16 Date [3:0],” on page 174 • Table 190: “RGMII Input Timing (Delayed Mode): GTXCLK and TXD [3:0],” on page 174 • Table 194: “Absolute Maximum Ratings,” on page 178 • Table 195: “DC Characteristics,” on page 178 • Table 197: “Sleep Mode,” on page 180 • Table 198: “IDDQ Mode,” on page 180 • • Table 201: “Ordering Information,” on page 184 Added: • “Thermal Information” on page 183 “RMII Interface” on page 54 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 3

BCM89811 Preliminary Data Sheet Revision History Revision BCM89811-DS103-R 07/10/15 Date Change Description Updated: • “Reduced Media Independent Interface” on page 11 • Table 6: “Hardware Signal Descriptions,” on page 24 • • Section 5 title from “Register Summary” • • Table 23: “LRE PHY Identifier Register (Addresses 02h and 03h),” “Register 02h and 03h: LRE PHY Identifier” on page 57 “Isolate Mode” on page 28 on page 57 “BroadR-Reach Extended Control Register (RDB Register 0x00)” on page 59 • • Table 26: “BroadR-Reach Extended Control Register,” on page 59 • “BroadR-Reach PHY Extended Status (RDB Register 0x01)” on page 60 • • Table 27: “BroadR-Reach Extended Status Register,” on page 60 • “BroadR-Reach Receive Error Counter (RDB Register 0x02)” on page 62 “BroadR-Reach False Carrier Sense Counter (RDB Register 0x03)” on page 63 “BroadR-Reach Receiver NOT_OK Counter (RDB Register 0x04)” on page 63 “Interrupt Status RDB Register 0x0A)” on page 63 “Interrupt Mask (RDB Register 0x0B)” on page 65 • • • Table 189: “RGMII Input Timing (Normal Mode): GTXCLK and TXD • [3:0],” on page 160 • Table 190: “RGMII Input Timing (Delayed Mode): GTXCLK and TXD [3:0],” on page 160 • Table 191: “RGMII Output Timing (Normal Mode): RXC and RXD [3:0],” on page 161 • Table 193: “Absolute Maximum Ratings,” on page 163 • Table 195: “BroadR-Reach One-Pair Operating Mode, 3.3V MII,” on page 165 Added: • • “PHY Core Addressing Methods” on page 46 “RDB Access Registers” on page 67 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 4

BCM89811 Preliminary Data Sheet Revision History Revision BCM89811-DS103-R (continued) Date 07/10/15 BCM89811-DS102-R 04/14/15 BCM89811-DS101-R 12/18/14 BCM89811-DS100-R 07/31/14 • Change Description Removed: • Register 17h, Register 18h, Register 18h Shadow 000, Register 18h Shadow 010, Register 18h Shadow 100, and Register 18h Shadow 111. “Register 1Ch Access”, “Register 1Ch (Shadow 00010): Spare Control 1”, “Register 1Ch (Shadow 00011): Clock Alignment Control”, “Register 1Ch (Shadow 00100): Spare Control 2”, “Register 1Ch (Shadow 01000): LED Status”, “Register 1Ch (Shadow 01001): LED Control”, “Register 1Ch (Shadow 01011): External Control”, “Register 1Ch (Shadow 01101): LED Selector 1”, “Register 1Ch (Shadow 01110): LED Selector 2” “Line-Side (Remote) Loopback Mode” “External Loopback Mode” “Register 1Eh: Test Register 1” “Expansion Register 91h: BroadR-Reach LRE Misc Control” “Expansion Register 92h: BroadR-Reach LRE Misc Control” “Expansion Register 9Fh: Reverse MII Control” • • • • • • Updated: • • Table 6: “Hardware Signal Descriptions,” on page 31 • • Table 23: “LRE Control Register (Address 00h),” on page 57 • Table 25: “LRE PHY Identifier Register (Addresses 02h and 03h),” “Power-Down Modes” on page 22 “Sleep Mode” on page 37 on page 61 “Expansion Register 7Fh: Sleep Mode Control” on page 96 • • Table 107: “DC Characteristics,” on page 123 Updated: • Changed PSD to INH, throughout. • Table 6: “Hardware Signal Descriptions,” on page 34 • Figure 6: “36-Pin QFN Pinout Diagram, Top View,” on page 38 • • Table 102: “Absolute Maximum Ratings,” on page 122 • Initial release. “Signal Quality Indicator” on page 44 “Ordering Information” on page 130 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 5

BCM89811 Preliminary Data Sheet Table of Contents Table of Contents About This Document ................................................................................................................................ 26 Purpose and Audience.......................................................................................................................... 26 Acronyms and Abbreviations................................................................................................................. 26 Document Conventions......................................................................................................................... 26 References............................................................................................................................................ 27 Technical Support ...................................................................................................................................... 27 Section 1: Functional Description ................................................................................... 28 Overview...................................................................................................................................................... 28 Media Independent Interface..................................................................................................................... 29 Reduced Gigabit Media Independent Interface ....................................................................................... 29 Reduced Media Independent Interface..................................................................................................... 29 BroadR-Reach............................................................................................................................................. 29 Management Interface................................................................................................................................ 29 Encoder ....................................................................................................................................................... 30 Link Monitor................................................................................................................................................ 30 Digital Adaptive Equalizer ......................................................................................................................... 30 Echo Canceler............................................................................................................................................. 30 Analog-to-Digital Converter....................................................................................................................... 31 Clock Recovery/Generator ........................................................................................................................ 31 Baseline Wander Correction ..................................................................................................................... 31 Multimode Transmit Digital-to-Analog Converter ................................................................................... 31 Stream Cipher and Radiated Emissions Control Features..................................................................... 32 BroadR-Reach Mode .................................................................................................................................. 32 Energy Detect ............................................................................................................................................. 33 Power-Down Modes ................................................................................................................................... 33 IEEE 1588 Support...................................................................................................................................... 34 Event Message...................................................................................................................................... 34 Grandmaster Clock ............................................................................................................................... 35 SC Support............................................................................................................................................ 35 IEEE 1588 Frame Formats.................................................................................................................... 36 Section 2: Hardware Signal Descriptions ....................................................................... 41 Section 3: Pinout ............................................................................................................... 45 Section 4: Operational Description.................................................................................. 46 Reset............................................................................................................................................................ 46 PHY Address............................................................................................................................................... 46 Isolate Mode................................................................................................................................................ 46 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 6

BCM89811 Preliminary Data Sheet Table of Contents Standby Power-Down Mode ...................................................................................................................... 47 Sleep Mode.................................................................................................................................................. 47 Wake and Sleep Functions ................................................................................................................... 47 INH................................................................................................................................................. 48 EN .................................................................................................................................................. 48 WAKE............................................................................................................................................. 49 TRD+, TRD– (BroadR-Reach Dataline)......................................................................................... 49 AVDD_PPD.................................................................................................................................... 50 Application Example.............................................................................................................................. 50 Internal Loopback Mode ............................................................................................................................ 52 RGMII Interface ........................................................................................................................................... 53 MII Interface................................................................................................................................................. 54 RMII Interface.............................................................................................................................................. 54 Broadcom Serial Control (BSC) Interface ................................................................................................ 55 Signal Quality Indicator ............................................................................................................................. 56 General-Purpose LED Programmability................................................................................................... 57 36-Pin QFN Package Hardware Configuration......................................................................................... 58 JTAG Mode ........................................................................................................................................... 58 PHY Address.................................................................................................................................. 58 RGMII/MII-Lite/RMII Modes ........................................................................................................... 58 Interrupt Function....................................................................................................................................... 59 LED Modes.................................................................................................................................................. 59 Section 5: Register Overview........................................................................................... 60 MII Management Interface Clause 22 Register Programming................................................................ 60 Preamble (PRE) .................................................................................................................................... 60 Start of Frame (ST) ............................................................................................................................... 60 Operation Code (OP) ............................................................................................................................ 60 PHY Address (PHYAD)......................................................................................................................... 60 Register Address (REGAD)................................................................................................................... 60 Turnaround (TA).................................................................................................................................... 60 Data....................................................................................................................................................... 61 PHY Core Addressing Methods ................................................................................................................ 62 IEEE Standard (0x00–0x0F) Registers ................................................................................................. 62 RDB Access Method ............................................................................................................................. 63 Register Map............................................................................................................................................... 64 Register Notations...................................................................................................................................... 68 BroadR-Reach LRE Register Descriptions .............................................................................................. 68 Register 00h: LRE Control .................................................................................................................... 69 Reset.............................................................................................................................................. 69 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 7

BCM89811 Preliminary Data Sheet Table of Contents Internal Loopback........................................................................................................................... 69 Reserved........................................................................................................................................ 69 Power-Down................................................................................................................................... 70 Isolate............................................................................................................................................. 70 Speed Selection............................................................................................................................. 70 Pair Selection................................................................................................................................. 70 Master/Slave Selection .................................................................................................................. 70 Register 01h: LRE Status...................................................................................................................... 70 100 Mbps One-Pair Capable.......................................................................................................... 71 Extended Status............................................................................................................................. 71 Support IEEE 802.3 PHY............................................................................................................... 71 Link Status ..................................................................................................................................... 71 Receive Jabber Detect................................................................................................................... 71 Extended Capability ....................................................................................................................... 71 Register 02h and 03h: LRE PHY Identifier............................................................................................ 72 Register 05h Test Mode Control ........................................................................................................... 72 Test Mode Descriptions ................................................................................................................. 72 Registers 04h, 06h–0Eh: Reserved ...................................................................................................... 73 Register 0Fh: LRE Extended Status ..................................................................................................... 73 Local Receiver Status .................................................................................................................... 73 Remote Receiver Status ................................................................................................................ 73 Idle Error Count.............................................................................................................................. 73 Auxiliary Register Descriptions ................................................................................................................ 74 BroadR-Reach Extended Control Register (RDB Register 0x00) ......................................................................................................................... 74 Transmit Disable ............................................................................................................................ 74 Interrupt Disable............................................................................................................................. 74 Force Interrupt................................................................................................................................ 74 Enable LED Traffic Mode............................................................................................................... 74 Force LEDs On .............................................................................................................................. 75 Force LEDs Off .............................................................................................................................. 75 BroadR-Reach PCS Transmit FIFO Elasticity (Copper Mode) ...................................................... 75 BroadR-Reach PHY Extended Status (RDB Register 0x01) ......................................................................................................................... 75 Interrupt Status............................................................................................................................... 76 Remote Receiver Status ................................................................................................................ 76 Local Receiver Status .................................................................................................................... 76 Locked............................................................................................................................................ 76 Link Status ..................................................................................................................................... 76 Broadcom® January 22, 2016 • 89811-DS104-R 7/18/2016 WNT2V Page 8

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