EDA基础实验总结报告.docx

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EDA 技术基础实验实验 1 4 选 1 数据选择器的设计一、原理图二、仿真波形三、管脚分配实验 2 四位比较器一、源代码

library ieee; use ieee.std_logic_1164.all; entity comp4 is port( A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); M,G,L: out std_logic); end comp4; architecture behave of comp4 is begin p1: process(A,B) begin if(A=B)then M<='1';G<='0';L<='0'; elsif(A>B)then M<='0';G<='1';L<='0'; elsif(A

实验 3 并行加法器设计一、源代码 library ieee; use ieee.std_logic_1164.all; entity add4 is port(a:in std_logic_vector(4 downto 1); b:in std_logic_vector(4 downto 1); cin:in std_logic; sum:out std_logic_vector(4 downto 1); cout:out std_logic); end add4; architecture behavioral of add4 is begin p1:process(a,b,cin) variable vsum:std_logic_vector(4 downto 1); variable carry:std_logic; begin carry:=cin;

for i in 1 to 4 loop vsum(i):=(a(i) xor b(i)) xor carry; carry:=(a(i) and b(i)) or (carry and (a(i) or b(i))); end loop; sum<=vsum; cout<=carry; end process p1; end behavioral; 二、仿真波形三、管脚分配实验 4 七人表决器一、源代码 Library ieee; Use ieee.std_logic_1164.all;

Use ieee.std_logic_unsigned.all; Entity bjq7 is Port(input:in std_logic_vector(7 downto 1); Y:out std_logic); End entity bjq7; Architecture behave of bjq7 is begin Process (input) variable Cnt:integer; Begin cnt:=0; For i in 1 to 7 loop If (input(i)='1')then cnt:=cnt+1; End if; End loop; If(cnt>3)then y<='1';else y<='0'; End if; End process; End behave; 二、仿真波形三、管脚分配七段数码管：一、源代码

LIBRARY IEEE; USE IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity BCD7 is port(Ain,Bin,Cin,Din:in std_logic; a,b,c,d,e,f,g:out std_logic); end BCD7; ARCHITECTURE ARCH of BCD7 is signal Q: std_logic_vector(3 downto 0); begin Q<=Din&Cin&Bin&Ain; process(Q) variable dout:std_logic_vector(6 downto 0); begin case Q is when "0000"=>Dout:="1000000";

when "0001"=>Dout:="1111001"; when "0010"=>Dout:="0100100"; when "0011"=>Dout:="0110000"; when "0100"=>Dout:="0011001"; when "0101"=>Dout:="0010010"; when "0110"=>Dout:="0000010"; when "0111"=>Dout:="1111000"; when "1000"=>Dout:="0000000"; when "1001"=>Dout:="0011000"; when others=>Dout:="1111111"; end case; a<=Dout(0); b<=Dout(1); c<=Dout(2); d<=Dout(3); e<=Dout(4); f<=Dout(5); g<=Dout(6); end process; end arch; 二、管脚分配分频器：一、源代码

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fenpin is port( clk:in std_logic; clk1:out std_logic ); end fenpin; architecture mix of fenpin is signal count:integer range 0 to 49999999; begin fenpin:process(clk) begin if rising_edge(clk)then if count=49999999 then count<=0; else count<=count+1; end if; if count>24999999 then clk1<='1';

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