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MSP432详细文档.pdf
1 Device Overview
1.1 Features
1.2 Applications
1.3 Description
1.4 Functional Block Diagram
Table of Contents
2 Revision History
3 Device Comparison
3.1 Related Products
4 Terminal Configuration and Functions
4.1 Pin Diagrams
4.2 Pin Attributes
4.3 Signal Descriptions
4.4 Pin Multiplexing
4.5 Buffer Types
4.6 Connection for Unused Pins
5 Specifications
5.1 Absolute Maximum Ratings
5.2 ESD Ratings
5.3 Recommended Operating Conditions
5.4 Recommended External Components
5.5 Operating Mode VCC Ranges
5.6 Operating Mode CPU Frequency Ranges
5.7 Operating Mode Peripheral Frequency Ranges
5.8 Operating Mode Execution Frequency vs Flash Wait-State Requirements
5.9 Current Consumption During Device Reset
5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
5.11 Current Consumption in DC-DC-Based Active Modes – Dhrystone 2.1 Program
5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
5.16 Typical Characteristics of Active Mode Currents for While(1) Program
5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
5.18 Current Consumption in LDO-Based LPM0 Modes
5.19 Current Consumption in DC-DC-Based LPM0 Modes
5.20 Current Consumption in Low-Frequency LPM0 Modes
5.21 Current Consumption in LPM3, LPM4 Modes
5.22 Current Consumption in LPM3.5, LPM4.5 Modes
5.23 Current Consumption of Digital Peripherals
5.24 Thermal Resistance Characteristics
5.25 Timing and Switching Characteristics
5.25.1 Reset Timing
5.25.2 Mode Transition Timing
5.25.3 Clock Specifications
5.25.4 Power Supply System
5.25.5 Digital I/Os
5.25.5.1 Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
5.25.5.2 Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
5.25.5.3 Typical Characteristics, Pin-Oscillator Frequency
5.25.6 14-Bit ADC
5.25.6.1 Typical Characteristics of ADC
5.25.7 REF_A
5.25.8 Comparator_E
5.25.9 eUSCI
5.25.10 Timers
5.25.11 Memories
5.25.12 Emulation and Debug
6 Detailed Description
6.1 Overview
6.2 Processor and Execution Features
6.2.1 Floating-Point Unit
6.2.2 Memory Protection Unit
6.2.3 Nested Vectored Interrupt Controller (NVIC)
6.2.4 SysTick
6.2.5 Debug and Trace Features
6.3 Memory Map
6.3.1 Code Zone Memory Map
6.3.1.1 Flash Memory Region
6.3.1.2 SRAM Region
6.3.1.3 ROM Region
6.3.2 SRAM Zone Memory Map
6.3.2.1 SRAM Region
6.3.2.2 SRAM Bit-Band Alias Region
6.3.3 Peripheral Zone Memory Map
6.3.3.1 Peripheral Region
6.3.3.2 Peripheral Bit Band Alias Region
6.3.4 Debug and Trace Peripheral Zone
6.4 Memories on the MSP432P401x
6.4.1 Flash Memory
6.4.1.1 Flash Main Memory (0x0000_0000 to 0x0003_FFFF)
6.4.1.2 Flash Information Memory (0x0020_0000 to 0x0020_3FFF)
6.4.1.3 Flash Operation
6.4.2 SRAM
6.4.2.1 SRAM Bank Enable Configuration
6.4.2.2 SRAM Bank Retention Configuration and Backup Memory
6.4.3 ROM
6.5 DMA
6.5.1 DMA Source Mapping
6.5.2 DMA Completion Interrupts
6.5.3 DMA Access Privileges
6.6 Memory Map Access Details
6.6.1 Master and Slave Access Priority Settings
6.6.2 Memory Map Access Response
6.7 Interrupts
6.7.1 NMI
6.7.2 Device-Level User Interrupts
6.8 System Control
6.8.1 Device Resets
6.8.1.1 Power On/Off Reset (POR)
6.8.1.2 Reboot Reset
6.8.1.3 Hard Reset
6.8.1.4 Soft Reset
6.8.2 Power Supply System (PSS)
6.8.2.1 VCCDET
6.8.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
6.8.2.3 Core Voltage Regulator
6.8.3 Power Control Manager (PCM)
6.8.4 Clock System (CS)
6.8.4.1 LFXT
6.8.4.2 HFXT
6.8.4.3 DCO
6.8.4.4 Very Low-Power Low-Frequency Oscillator (VLO)
6.8.4.5 Low-Frequency Reference Oscillator (REFO)
6.8.4.6 Module Oscillator (MODOSC)
6.8.4.7 System Oscillator (SYSOSC)
6.8.4.8 Fail-Safe Mechanisms
6.8.5 System Controller (SYSCTL)
6.9 Peripherals
6.9.1 Digital I/O
6.9.1.1 Glitch Filtering on Digital I/Os
6.9.2 Port Mapping Controller (PMAPCTL)
6.9.2.1 Port Mapping Definitions
6.9.3 Timer_A
6.9.3.1 Timer_A Signal Connection Tables
6.9.4 Timer32
6.9.5 Enhanced Universal Serial Communication Interface (eUSCI)
6.9.6 Real-Time Clock (RTC_C)
6.9.7 Watchdog Timer (WDT_A)
6.9.8 ADC14
6.9.9 Comparator_E (COMP_E)
6.9.10 Shared Reference (REF_A)
6.9.11 CRC32
6.9.12 AES256 Accelerator
6.9.13 True Random Seed
6.10 Code Development and Debug
6.10.1 JTAG and SWD Based Development, Debug, and Trace
6.10.2 Peripheral Halt Control
6.10.3 Bootloader (BSL)
6.10.4 Device Security
6.11 Performance Benchmarks
6.11.1 ULPBench Performance: 192.3 ULPMark-CP
6.11.2 CoreMark/MHz Performance: 3.41
6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
6.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
6.12.2 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
6.12.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
6.12.4 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
6.12.5 Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
6.12.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
6.12.7 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
6.12.8 Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
6.12.9 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
6.12.10 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
6.12.11 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
6.12.12 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
6.12.13 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
6.12.14 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
6.12.15 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
6.12.16 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
6.12.18 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
6.12.19 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
6.12.20 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
6.12.21 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
6.12.22 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
6.12.23 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
6.13 Device Descriptors (TLV)
6.14 Identification
6.14.1 Revision Identification
6.14.2 Device Identification
6.14.3 ARM Cortex-M4F ROM Table Based Part Number
7 Applications, Implementation, and Layout
7.1 Device Connection and Layout Fundamentals
7.1.1 Power Supply Decoupling and Bulk Capacitors
7.1.2 External Oscillator
7.1.3 General Layout Recommendations
7.1.4 Do's and Don'ts
7.2 Peripheral and Interface-Specific Design Information
7.2.1 ADC14 Peripheral
7.2.1.1 Partial Schematic
7.2.1.2 Design Requirements
7.2.1.3 Layout Guidelines
8 Device and Documentation Support
8.1 Getting Started and Next Steps
8.2 Device and Development Tool Nomenclature
8.3 Tools and Software
8.4 Documentation Support
8.5 Related Links
8.6 Community Resources
8.7 Trademarks
8.8 Electrostatic Discharge Caution
8.9 Export Control Notice
8.10 Glossary
9 Mechanical, Packaging, and Orderable Information
Important Notice
MSP432P401R, MSP432P401M SimpleLink™ Mixed-Signal Microcontrollers
MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
1 Device Overview
Features
1.1
• Core
1
• Flexible Clocking Features
– Tunable Internal DCO (up to 48 MHz)
– 32.768 kHz Low-Frequency Crystal Support
– High-Frequency Crystal Support (HFXT) up to
– Low-Frequency Internal Reference Oscillator
(LFXT)
48 MHz
(REFO)
– Very Low-Power Low-Frequency Internal
Oscillator (VLO)
– Module Oscillator (MODOSC)
– System Oscillator (SYSOSC)
• Code Security Features
– JTAG and SWD Lock
– IP Protection (up to Four Secure Flash Zones,
Each With Configurable Start Address and Size)
• Enhanced System Features
– Programmable Supervision and Monitoring of
Supply Voltage
– Multiple-Class Resets for Better Control of
Application and Debug
– 8-Channel DMA
– RTC With Calendar and Alarm Functions
• Timing and Control
– Up to Four 16-Bit Timers, Each With up to Five
Capture, Compare, PWM Capability
– Two 32-Bit Timers, Each With Interrupt
Generation Capability
• Serial Communication
– Up to Four eUSCI_A Modules
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI (up to 16 Mbps)
– Up to Four eUSCI_B Modules
– I2C (With Multiple-Slave Addressing)
– SPI (up to 16 Mbps)
• Flexible I/O Features
– Ultra-Low-Leakage I/Os (±20 nA Maximum)
– All I/Os With Capacitive-Touch Capability
– Up to 48 I/Os With Interrupt and Wake-up
Capability
– Up to 24 I/Os With Port Mapping Capability
– Eight I/Os With Glitch Filtering Capability
– ARM® 32-Bit Cortex®-M4F CPU With Floating-
Point Unit and Memory Protection Unit
– Frequency up to 48 MHz
– ULPBench™ Benchmark:
– 192.3 ULPMark™-CP
– Performance Benchmark:
– 3.41 CoreMark/MHz
– 1.22 DMIPS/MHz (Dhrystone 2.1)
• Advanced Low-Power Analog Features
– 14-Bit 1-MSPS SAR ADC With 13.2 ENOB
Native and Capability to Reach 16 ENOB With
Oversampling, Differential and Single-Ended
Inputs
– Internal Voltage Reference With 10-ppm/°C
Typical Stability
– Two Analog Comparators
• Memories
– Up to 256KB of Flash Main Memory (Organized
Into Two Banks Enabling Simultaneous
Read/Execute During Erase)
– 16KB of Flash Information Memory (Used for
BSL, TLV, and Flash Mailbox)
– Up to 64KB of SRAM (Including 6KB of Backup
– 32KB of ROM With MSP432™ Peripheral Driver
Memory)
Libraries
• Ultra-Low-Power Operating Modes
– Active: 80 µA/MHz
– Low-Frequency Active: 83 µA at 128 kHz
– LPM3 (With RTC): 660 nA
– LPM3.5 (With RTC): 630 nA
– LPM4: 500 nA
– LPM4.5: 25 nA
• Development Kits and Software (See Tools and
Software)
– MSP-EXP432P401R LaunchPad™
Development Kit
– MSP-TS432PZ100 100-Pin Target Board
– SimpleLink™ MSP432 Software Development
Kit (SDK)
• Operating Characteristics
– Wide Supply Voltage Range: 1.62 V to 3.7 V
– Temperature Range (Ambient): –40°C to 85°C
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ProductFolderOrderNowTechnicalDocumentsTools &SoftwareSupport &Community
MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
• Encryption and Data Integrity Accelerators
– 128-, 192-, or 256-Bit AES Encryption and
Decryption Accelerator
– 32-Bit Hardware CRC Engine
1.2 Applications
•
Industrial and Automation
– Glass Breakage Detectors
– Smart Thermostats
– Access Panels
– Gas Monitors
– Field Transmitters
– Process Automation
– Home Automation
• Metering
– Flow Meters
– Electric Meters
– Communication Modules
1.3 Description
www.ti.com
• JTAG and Debug Support
– 4-Pin JTAG and 2-Pin SWD Debug Interfaces
– Serial Wire Trace
– Power Debug and Profiling of Applications
• Test and Measurement
– Digital Multimeters
– Wireless Digital Multimeters
– Contactless and Hand-Held Digital Meters
• Health and Fitness
– Watches
– Activity Monitors
– Fitness Accessories
– Blood Glucose Meters
• Consumer Electronics
– Mobile Devices
– Sensor Hubs
The SimpleLink MSP432P401x microcontrollers (MCUs) are optimized wireless host MCUs with an
integrated 14-bit analog-to-digital converter (ADC) capable of up to 16 ENOB delivering ultra-low-power
performance including 80 µA/MHz in active power and 660 nA in standby power with FPU and DSP
extensions. As an optimized wireless host MCU, the MSP432P401x allows developers to add high-
precision analog and memory extension to applications based on SimpleLink wireless connectivity
solutions.
The MSP432P401x devices are part of the SimpleLink microcontroller (MCU) platform, which consists of
Wi-Fi®, Bluetooth® low energy, Sub-1 GHz, and host MCUs. All share a common, easy-to-use
development environment with a single core software development kit (SDK) and rich tool set. A one-time
integration of the SimpleLink platform lets you add any combination of devices from the portfolio into your
design. The ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your
design requirements change. For more information, visit www.ti.com/simplelink.
MSP432P401x devices are supported by a comprehensive ecosystem of tools, software, documentation,
training, and support
to get your development started quickly. The MSP-EXP432P401R LaunchPad
development kit or MSP-TS432PZ100 target socket board (with additional MCU sample) along with the
free SimpleLink MSP432 SDK is all you need to get started.
PART NUMBER
Device Information(1)
PACKAGE
BODY SIZE(2)
MSP432P401RIPZ
MSP432P401MIPZ
MSP432P401RIZXH
MSP432P401MIZXH
MSP432P401RIRGC
MSP432P401MIRGC
(1) For the most current part, package, and ordering information for all available devices, see the Package
14 mm × 14 mm
5 mm × 5 mm
9 mm × 9 mm
VQFN (64)
LQFP (100)
NFBGA (80)
Option Addendum in Section 9, or see the TI website.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
2
Device Overview
Copyright © 2015–2017, Texas Instruments Incorporated
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MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
1.4
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the MSP432P401R and MSP432P401M devices.
Figure 1-1. MSP432P401R, MSP432P401M Functional Block Diagram
The CPU and all of the peripherals in the device interact with each other through a common AHB matrix.
In some cases,
there are bridges between the AHB ports and the peripherals. These bridges are
transparent to the application from a memory map perspective and, therefore, are not shown in the block
diagram.
Copyright © 2015–2017, Texas Instruments Incorporated
Device Overview
3
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Product Folder Links: MSP432P401R MSP432P401M
PCMPowerControlManagerPSSPowerSupplySystemCSClockSystemRTC_CReal-TimeClockWDT_AWatchdogTimerI/O PortsP1 to P1078 I/OsI/O PortsPJ6 I/OsFlash256KB128KBRSTCTLResetControllerSYSCTLSystemControllerAES256SecurityEncryption,DecryptionCRC32ADC1414 bit,1 Msps,SARA/DComp_E0,Comp_E1AnalogComparatorREF_A,VoltageReferenceTA0,TA1,TA2,TA3Timer_A16 Bit5 CCRTimer322 x 32-bitTimerseUSCI_A0,eUSCI_A1,eUSCI_A2,eUSCI_A3(UART,IrDA, SPI)eUSCI_B0,eUSCI_B1,eUSCI_B2,eUSCI_B3(IC, SPI)2BusControlLogicDMA8 ChannelsCapacitiveTouch IO 0,CapacitiveTouch IO 1AddressDataLFXIN,HFXINLFXOUT,HFXOUTDCORLPM3.5 DomainP1.x to P10.xPJ.xBackupMemorySRAM6KBCPUMPUNVIC, SysTickFPB, DWTARMCortex™-M4F®ITM,TPIUJTAG, SWDSRAM(includesBackupMemory)64KB32KBROM(PeripheralDriverLibrary)32KBCopyright © 2016,Texas Instruments Incorporated
MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
www.ti.com
Table of Contents
1.1
1.2
1.3
1.4
4
5
1 Device Overview ......................................... 1
Features .............................................. 1
Applications........................................... 2
Description............................................ 2
Functional Block Diagram ............................ 3
2 Revision History ......................................... 5
3 Device Comparison ..................................... 6
Related Products ..................................... 7
3.1
Terminal Configuration and Functions.............. 8
Pin Diagrams ......................................... 8
4.1
Pin Attributes........................................ 11
4.2
Signal Descriptions.................................. 17
4.3
Pin Multiplexing ..................................... 27
4.4
Buffer Types......................................... 27
4.5
Connection for Unused Pins ........................ 27
4.6
Specifications........................................... 28
Absolute Maximum Ratings ........................ 28
5.1
ESD Ratings ........................................ 28
5.2
Recommended Operating Conditions............... 28
5.3
Recommended External Components ............. 29
5.4
Operating Mode VCC Ranges ....................... 29
5.5
Operating Mode CPU Frequency Ranges ......... 30
5.6
Operating Mode Peripheral Frequency Ranges .... 30
5.7
5.8
Operating Mode Execution Frequency vs Flash
Wait-State Requirements ........................... 31
Current Consumption During Device Reset......... 31
Modes – Dhrystone 2.1 Program ................... 31
Modes – Dhrystone 2.1 Program ................... 32
Modes – Dhrystone 2.1 Program ................... 32
CoreMark Program.................................. 33
Prime Number Program............................. 34
Fibonacci Program .................................. 35
While(1) Program ................................... 36
5.17 Typical Characteristics of Low-Frequency Active
Mode Currents for CoreMark Program.............. 37
5.18 Current Consumption in LDO-Based LPM0 Modes. 38
5.9
5.10 Current Consumption in LDO-Based Active
5.13 Typical Characteristics of Active Mode Currents for
5.14 Typical Characteristics of Active Mode Currents for
5.15 Typical Characteristics of Active Mode Currents for
5.16 Typical Characteristics of Active Mode Currents for
5.11 Current Consumption in DC-DC-Based Active
5.12 Current Consumption in Low-Frequency Active
5.19 Current Consumption in DC-DC-Based LPM0
Modes ............................................... 38
5.20 Current Consumption in Low-Frequency LPM0
Modes ............................................... 38
5.21 Current Consumption in LPM3, LPM4 Modes ...... 39
5.22 Current Consumption in LPM3.5, LPM4.5 Modes .. 39
5.23 Current Consumption of Digital Peripherals ........ 40
5.24 Thermal Resistance Characteristics ................ 40
5.25 Timing and Switching Characteristics............... 41
6 Detailed Description ................................... 90
Overview ............................................ 90
6.1
Processor and Execution Features ................. 90
6.2
6.3 Memory Map ........................................ 91
6.4 Memories on the MSP432P401x .................. 111
DMA................................................ 114
6.5
6.6 Memory Map Access Details ...................... 115
Interrupts........................................... 117
6.7
System Control..................................... 119
6.8
Peripherals......................................... 124
6.9
6.10 Code Development and Debug.................... 134
6.11 Performance Benchmarks ......................... 136
6.12 Input/Output Diagrams............................. 138
6.13 Device Descriptors (TLV).......................... 176
6.14 Identification........................................ 178
7 Applications, Implementation, and Layout ...... 180
Device Connection and Layout Fundamentals .... 180
Peripheral and Interface-Specific Design
Information ......................................... 181
8 Device and Documentation Support.............. 183
Getting Started and Next Steps ................... 183
8.1
Device and Development Tool Nomenclature..... 183
8.2
Tools and Software ................................ 184
8.3
Documentation Support............................ 186
8.4
Related Links ...................................... 187
8.5
Community Resources............................. 188
8.6
Trademarks ........................................ 188
8.7
Electrostatic Discharge Caution ................... 188
8.8
Export Control Notice.............................. 188
8.9
8.10 Glossary............................................ 188
Information............................................. 188
9 Mechanical, Packaging, and Orderable
7.1
7.2
4
Table of Contents
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Product Folder Links: MSP432P401R MSP432P401M
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MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 26, 2016 to March 7, 2017
Page
• Added "SimpleLink" branding, including updates to the titles of referenced documents.................................... 1
• Reorganized contents of Section 1.1, Features .................................................................................. 1
• Updated Section 1.2, Applications ................................................................................................. 2
• Updated Section 1.3, Description................................................................................................... 2
• Updated lists of software and tools in Section 8.3, Tools and Software.................................................... 185
Copyright © 2015–2017, Texas Instruments Incorporated
Revision History
5
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MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
3 Device Comparison
Table 3-1 summarizes the features of the MSP432P401x microcontrollers.
Table 3-1. Device Comparison(1)
eUSCI
DEVICE
FLASH
(KB)
SRAM
(KB)
ADC14
(Channels)
COMP_E0
(Channels)
COMP_E1
(Channels)
Timer_A(2)
CHANNEL
A:
UART,
IrDA, SPI
CHANNEL
B:
SPI, I2C
www.ti.com
20-mA
DRIVE I/O
TOTAL
I/Os
PACKAGE
MSP432P401RIPZ
MSP432P401MIPZ
MSP432P401RIZXH
MSP432P401MIZXH
MSP432P401RIRGC
MSP432P401MIRGC
256
128
256
128
256
128
64
32
64
32
64
32
24 ext, 2 int
24 ext, 2 int
16 ext, 2 int
16 ext, 2 int
12 ext, 2 int
12 ext, 2 int
8
8
6
6
2
2
8
8
8
8
4
4
5, 5, 5, 5
5, 5, 5, 5
5, 5, 5
5, 5, 5
5, 5, 5
5, 5, 5
4
4
3
3
3
3
4
4
4
4
3
3
4
4
4
4
4
4
84
84
64
64
48
48
100 PZ
100 PZ
80 ZXH
80 ZXH
64 RGC
64 RGC
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
6
Device Comparison
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3.1 Related Products
MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers Low-power and high-performance MCUs, with wired and wireless
connectivity options.
Products for SimpleLink MSP432 MCUs SimpleLink MSP432 MCUs with an ultra-low-power ARM
Cortex-M4 core are optimized for Internet-of-Things sensor node applications. With an
integrated 14-bit ADC,
the family enables acquisition and processing of high-precision
signals without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless
connectivity solutions.
Companion Products for MSP432P401R Review products that are frequently purchased or used with
this product.
Reference Designs for MSP432P401R The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Copyright © 2015–2017, Texas Instruments Incorporated
Device Comparison
7
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MSP432P401R, MSP432P401M
SLAS826F –MARCH 2015–REVISED MARCH 2017
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout of the 100-pin PZ package.
www.ti.com
A.
The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default
mapping. See Section 6.9.2 for details.
B. A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
C. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
D. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
E.
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-1. 100-Pin PZ Package (Top View)
8
Terminal Configuration and Functions
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1P10.1/UCB3CLK2P10.2/UCB3SIMO/UCB3SDA3P10.3/UCB3SOMI/UCB3SCL4P1.0/UCA0STE5P1.1/UCA0CLK6P1.2/UCA0RXD/UCA0SOMI7P1.3/UCA0TXD/UCA0SIMO8P1.4/UCB0STE9P1.5/UCB0CLK10P1.6/UCB0SIMO/UCB0SDA11P1.7/UCB0SOMI/UCB0SCL12VCORE13DVCC114VSW15DVSS116P2.0/PM_UCA1STE17P2.1/PM_UCA1CLK18P2.2/PM_UCA1RXD/PM_UCA1SOMI19P2.3/PM_UCA1TXD/PM_UCA1SIMO20P2.4/PM_TA0.121P2.5/PM_TA0.222P2.6/PM_TA0.323P2.7/PM_TA0.424P10.4/TA3.0/C0.725P10.5/TA3.1/C0.626P7.4/PM_TA1.4/C0.527P7.5/PM_TA1.3/C0.428P7.6/PM_TA1.2/C0.329P7.7/PM_TA1.1/C0.230P8.0/UCB3STE/TA1.0/C0.131P8.1/UCB3CLK/TA2.0/C0.032P3.0/PM_UCA2STE33P3.1/PM_UCA2CLK34P3.2/PM_UCA2RXD/PM_UCA2SOMI35P3.3/PM_UCA2TXD/PM_UCA2SIMO36P3.4/PM_UCB2STE37P3.5/PM_UCB2CLK38P3.6/PM_UCB2SIMO/PM_UCB2SDA39P3.7/PM_UCB2SOMI/PM_UCB2SCL40AVSS341PJ.0/LFXIN42PJ.1/LFXOUT43AVSS144DCOR45AVCC146P8.2/TA3.2/A2347P8.3/TA3CLK/A2248P8.4/A2149P8.5/A2050P8.6/A1951P8.7/A1852P9.0/A1753P9.1/A1654P6.0/A1555P6.1/A1456P4.0/A1357P4.1/A1258P4.2/ACLK/TA2CLK/A1159P4.3/MCLK/RTCCLK/A1060P4.4/HSMCLK/SVMHOUT/A961P4.5/A862P4.6/A763P4.7/A664P5.0/A565P5.1/A466P5.2/A367P5.3/A268P5.4/A169P5.5/A070P5.6/TA2.1/VREF+/VeREF+/C1.771P5.7/TA2.2/VREF-/VeREF-/C1.672DVSS273DVCC274P9.2/TA3.375P9.3/TA3.476P6.2/UCB1STE/C1.577P6.3/UCB1CLK/C1.478P6.4/UCB1SIMO/UCB1SDA/C1.379P6.5/UCB1SOMI/UCB1SCL/C1.280P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.181P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.082DVSS383RSTn/NMI84AVSS285PJ.2/HFXOUT86PJ.3/HFXIN87AVCC288P7.0/PM_SMCLK/PM_DMAE089P7.1/PM_C0OUT/PM_TA0CLK90P7.2/PM_C1OUT/PM_TA1CLK91P7.3/PM_TA0.092PJ.4/TDI93PJ.5/TDO/SWO94SWDIOTMS95SWCLKTCK96P9.4/UCA3STE97P9.5/UCA3CLK98P9.6/UCA3RXD/UCA3SOMI99P9.7/UCA3TXD/UCA3SIMO100P10.0/UCB3STE
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