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Marvel交换芯片88E6083数据手册.pdf
Link Street™ 88E6083 and 88E6083-I Datasheet
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM, Transceivers
Section 1. Signal Description
1.1 88E6083 216-Pin LQFP Package
1.2 Pin Description
1.2.1 Pin Type Definitions
Section 2. Application Examples
2.1 Configuration Options for the 88E6083 Device
2.2 Example Configurations
Section 3. Functional Description
3.1 Switch Data Flow
3.2 MII/SNI/RMII
3.2.1 MII PHY Mode
3.2.2 MII MAC Mode
3.2.3 SNI PHY Mode
3.2.4 RMII PHY Mode
3.2.5 MII/SNI Configuration
3.2.6 Enabling the MII/SNI Interfaces
3.2.7 Port Status Registers
3.2.8 MII 200 Mbps Mode
3.3 Media Access Controllers (MAC)
3.3.1 Backoff
3.3.2 Half-Duplex Flow Control
3.3.3 Full-Duplex Flow Control
3.3.4 Forcing Flow Control
3.3.5 Statistics Counters
3.3.6 Extensive RMON/Statistics Counters
3.4 Address Management
3.4.1 Address Translation Unit
3.4.2 Address Searching or Translation
3.4.3 Address Learning
3.4.4 Address Aging
3.4.5 Address Translation Unit Operations
3.5 Ingress Policy
3.5.1 Forward Unknown/Secure Port
3.5.2 Quality of Service (QoS) Classification
3.5.3 VLANs
3.5.4 VLAN Translation Unit Operations
3.5.5 Switching Frames Back to their Source Port
3.5.6 IGMP/MLD Snooping
3.5.7 Port States
3.5.8 Ingress Double VLAN Tagging
3.5.9 Ingress Rate Limiting
3.5.10 Switch’s Ingress Header
3.5.11 Switch’s Ingress Trailer
3.6 Queue Controller
3.6.1 Frame Latencies
3.6.2 No Head-of-Line Blocking
3.6.3 QoS with and without Flow Control
3.6.4 Guaranteed Frame Delivery without Flow Control
3.6.5 Fixed or Weighted Priority
3.6.6 The Queues
3.6.7 Queue Manager
3.6.8 Output Queues
3.6.9 Multicast Handler
3.6.10 WatchDog
3.7 Egress Policy
3.7.1 Tagging and Untagging Frames
3.7.2 Priority Override
3.7.3 VID 0x000 and VID Override
3.7.4 Egress Double VLAN Tagging
3.7.5 Egress Rate Limiting
3.7.6 Switch’s Egress Header
3.7.7 Switch’s Egress Trailer
3.8 Spanning Tree Support
3.9 Embedded Memory
3.10 Interrupt Controller
3.11 Port Monitoring Support
3.12 Port Trunking Support
Section 4. Physical Interface (PHY) Functional Description
4.1 Transmit PCS and PMA
4.1.1 100BASE-TX Transmitter
4.1.2 4B/5B Encoding
4.1.3 Scrambler
4.1.4 NRZ to NRZI Conversion
4.1.5 Pre-Driver and Transmit Clock
4.1.6 Multimode Transmit DAC
4.2 Receive PCS and PMA
4.2.1 10-BASE-T/100BASE-TX Receiver
4.2.2 AGC and Baseline Wander
4.2.3 ADC and Digital Adaptive Equalizer
4.2.4 Digital Phased Locked Loop (DPLL)
4.2.5 NRZI to NRZ Conversion
4.2.6 Descrambler
4.2.7 Serial-to-Parallel Conversion and 5B/4B Code-Group Alignment
4.2.8 5B/4B Decoder
4.2.9 Setting Cable Characteristics
4.2.10 Scrambler/Descrambler
4.2.11 Digital Clock Recovery/Generator
4.2.12 Link Monitor
4.2.13 Auto-Negotiation
4.2.14 Register Update
4.2.15 Next Page Support
4.2.16 Status Registers
4.3 Far End Fault Indication (FEFI)
4.4 Virtual Cable Tester™
4.5 Auto MDI/MDIX Crossover
4.6 LED Interface
4.6.1 Parallel LED Interface
4.6.2 Serial LED Interface
4.7 Serial Management Interface (SMI)
4.7.1 MDC/MDIO Read and Write Operations
Section 5. Register Description
5.1 Register Types
5.2 Switch Core Registers
5.2.1 Switch Core Register Map
5.2.2 Switch Port Registers
5.2.3 Switch Global Registers
Section 6. PHY Registers
Section 7. EEPROM Programming Format
7.1 EEPROM Programming Details
Section 8. Electrical Specifications
8.1 Absolute Maximum Ratings
8.2 Recommended Operating Conditions
8.3 Package Thermal Information
8.3.1 Thermal Conditions for 216-pin LQFP Package
8.4 AC Electrical Specifications
8.4.1 Reset and Configuration Timing
Section 9. Package Mechanical Dimensions
9.1 Ordering Part Numbers and Package Markings
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Link Street™ 88E6083 and 88E6083-I
Datasheet
Integrated 10-Port 10/100 Ethernet Switch with
QoS, RAM, Transceivers
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
Doc. No. MV-S100968-00 Rev. A
December 22, 2003
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Document Status
Advanced
Information
Preliminary
Information
Final
Information
Revision Code: Rev. A
Advanced
This document contains design specifications for initial product development. Specifications may change
without notice. Contact Marvell Field Application Engineers for more information.
This document contains preliminary data, and a revision of this document will be published at a later date.
Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
This document contains specifications on a product that is in final release. Specifications may change without
notice. Contact Marvell Field Application Engineers for more information.
Technical Publications: 0.64A
88E6083
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM, Transceivers
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express
written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard
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accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell makes no commitment either to update or to keep current the information
contained in this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not
use Marvell products in these types of equipment or applications. The user should contact Marvell to obtain the latest specifications before finalizing a product design. Marvell assumes no
responsibility, either for use of these products or for any infringements of patents and trademarks, or other rights of third parties resulting from its use. No license is granted under any patents,
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Copyright © 12/26/03. Marvell. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, and GalNet are registered trademarks of Marvell. Discovery, Fastwriter, GalTis,
Horizon, Libertas, Link Street, NetGX, PHY Advantage, Prestera, Raising The Technology Bar, UniMAC, Virtual Cable Tester, and Yukon are trademarks of Marvell. All other trademarks are
the property of their respective owners.
Disclaimer
This document provides preliminary information about the products described, and such information should not be used for purpose of final design. Visit the Marvell® web site at www.mar-
vell.com for the latest information on Marvell products.
Doc. No. MV-S100968-00 Rev. A
Page 2
Copyright © 2003 Marvell
December 22, 2003, Advanced
Document Classification: Proprietary Information
CONFIDENTIAL
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OVERVIEW
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88E6083
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM,
Transceivers
Auto-Crossover, Auto-Polarity and Auto-Negotiation in
all the PHYs, along with network loop prevention. The
many operating modes of the 88E6083 device can be
configured using SMI (serial management interface -
MDC/MDIO) and/or a low cost serial EEPROM
(93C46, C56 or C66). A stand-alone QoS mode is also
supported. Each PHY supports Marvell’s Virtual Cable
Tester™ (VCT) feature for testing cables and connec-
tors using TDR.
FEATURES
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
The 88E6083 device is a single chip integrated 10-port
Fast Ethernet switch with Quality of Service (QoS)
support, integrating eight PHY ports and two MII ports.
The device contains ten independent Fast Ethernet
media access controllers (MACs); eight 10BASE-T/
100BASE-TX copper PHY transceivers, all eight of
which can be configured as 100BASE-FX fiber; a high-
speed non-blocking QoS switch fabric with four traffic
classes, a high-performance address lookup engine,
and a 1 Mbit frame buffer memory. The 88E6083 Fast
Ethernet switch integrates special support for WAN/
LAN firewall isolation, Quality of Service, dynamic
VLANs, and SNMP/ RMON.
The 88E6083 device utilizes the latest Marvell® Qual-
ity of Service switch architecture with non-blocking
switching performance in all traffic environments.
Packets are directed into one of four traffic class prior-
ity queues based on Port priority, IEEE 802.1p, IPv4’s
TOS or Diff-Serv or IPv6’s Traffic Class, and MAC
address. The 88E6083 device also integrates IGMP/
MLD snooping capability (IPv4/IPv6).
The 88E6083 device supports truly isolated WAN vs.
LAN firewall applications. Ports 9 and 10 are Media
Independent Interfaces (MIIs) that support direct con-
nection to a Router or Management CPU. These can
be configured in either RMII, MII PHY or MAC Mode,
or SNI. This interface, along with BPDU handling, pro-
grammable per port VLAN configurations, and Port
States, supports Spanning Tree and truly isolated
WAN vs. LAN firewall.
The 88E6083 device includes complete IEEE 802.1Q
VLAN ID processing per port, to process dynamic
VLAN membership and VLAN tagging. The device
also integrates extensive RMON network manage-
ment capability, including 40 RMON statistics counters
per port (twenty 32-bit counters each for ingress and
egress on every port).
The PHYs in the 88E6083 device are designed with
Marvell cutting-edge mixed-signal processing technol-
ogy for digital implementation of adaptive equalization
and clock data recovery. Special power management
techniques are used to facilitate low power dissipation
and high port count integration. Both the PHY and
MAC units in the 88E6083 device comply fully with the
applicable sections of IEEE 802.3, IEEE 802.3u, and
IEEE 802.3x standards.
The 88E6083 device is designed to work in all cable
environments. True Plug-n-Play is supported with
Single chip integration of a 10-port Fast Ethernet
QoS switch, eight PHY ports plus 2 MII ports, in a
216-pin LQFP package
Integrates ten independent media access control-
lers (MACs) fully compliant with the applicable
sections of IEEE802.3, IEEE802.3u and
IEEE802.3x
Integrates eight independent Fast Ethernet trans-
ceivers (PHYs) fully compliant with the applicable
sections of IEEE802.3 and IEEE802.3u
Automatic MDI/MDIX crossover for 100BASE-TX
and 10BASE-T ports
All eight PHY ports can be configured as copper
ports (100BASE-TX or 10BASE-T) or fiber
(100BASE-FX)
QoS support with four traffic classes, typically
supporting prioritized packet streams for manage-
ment, voice, video, and data
Full IEEE 802.1Q VLAN ID processing per port,
with dynamic VLAN membership, and VLAN tag-
ging for up to 64 VIDs
High performance lookup engine with support for
2048 MAC address entries with address lock
options, automatic learning and aging
Extensive RMON Statistics Counters, 40 Stat
Counters Per Port (20 Each for Ingress and
Egress)
QoS determined by Port, IEEE 802.1p tagged
frames, IPv4’s Type of Service (TOS) & Differenti-
ated Services (DS) or IPv6’s Traffic Class, DA
MAC address
IGMP (IPv4) and MLD (IPv6) Snooping
Fixed priority and weighted fair queuing
Port based VLANs supported in any combination
Virtual Cable Tester™ (VCT) capability
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S100968-00 Rev. A
December 22, 2003, Advanced
Copyright © 2003 Marvell
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P0_TX
10BASE-T
Transceiver
10BASE-T
Transceiver
10BASE-T
Transceiver
10BASE-T
Transceiver
P1_RX
P1_TX
P3_RX
P3_TX
P2_RX
P2_TX
Port States
& Tag
Processing
Port 3's
MAC
Port 2's
MAC
Port States
& Tag
Processing
Port 1's
MAC
Port States
& Tag
Processing
Port 0's
MAC
Port States
& Tag
Processing
Register Loader
100BASE-TX/FX
100BASE-TX/FX
100BASE-TX/FX
100BASE-TX/FX
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
EE_CS
EE_CLK
EE_DIN
EE_DOUT
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Fiber Enable
and Controls
for Ports 7:0
P0_RX
FEATURES (continued)
Link Street™88E6083
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM, Transceivers
MIIs support both a MAC Mode (Forward MII) or
PHY Mode (Reverse MII), 7-Wire SNI, or
Reduced MII (RMII)
Flexible LED support for Link, Speed, Duplex
Mode, Collision, and Tx/Rx Activities
Supports a low cost 25 MHz XTAL clock source
CMOS low power dissipation
Available with Commercial grade (88E6083 part)
or Industrial grade (88E6083-I part) temperature
specifications
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
DISABLE_P9
MAC or PHY Mode
MII/RMII/SNI Interface
ENABLE_P8
MAC or PHY Mode
MII/RMII/SNI Interface
P[7:0]_LED0
P[7:0]_LED1
P[7:0]_LED2
LEDCLK
LEDENA
LEDSER
Document Classification: Proprietary Information
December 22, 2003,
Advanced
CONFIDENTIAL
Doc. No. MV-S100968-00 Rev. A
Copyright © 2003 Marvell
XTAL_IN
XTAL_OUT
32-bit RMON
Counters per
MDC
MDIO
INTn
802.1Q
VLAN
Table
SW_MODE[1:0]
Controller
with Four
Address
Database
CPU/Reg
Interface
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
100BASE-TX/FX
100BASE-TX/FX
100BASE-TX/FX
100BASE-TX/FX
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Look-up
Engine
Traffic
Classes
1 Mbit
Embedded
Memory
Switch
Fabric
&
Page 4
Port States
& Tag
Processing
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Port States
& Tag
Processing
Port 8's
MAC
Port States
& Tag
Processing
Port States
& Tag
Processing
Port 4's
MAC
Port 5's
MAC
Port States
& Tag
Processing
Port 9's
MAC
Port States
& Tag
Processing
LED
Controller
P4_RX
P4_TX
P5_RX
P5_TX
P7_RX
P7_TX
P6_RX
P6_TX
40
port
10BASE-T
Transceiver
10BASE-T
Transceiver
10BASE-T
Transceiver
10BASE-T
Transceiver
Port 6's
MAC
Port 7's
MAC
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1.1
1.3
Table of Contents
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Table of Contents
216-Pin LQFP Pin Assignment List—by Signal Name...........................................................26
88E6083 216-Pin LQFP Package................................................................................................7
3.1 Switch Data Flow ......................................................................................................................33
2.2 Example Configurations...........................................................................................................30
2.1 Configuration Options for the 88E6083 Device......................................................................30
SECTION 3. FUNCTIONAL DESCRIPTION.................................................................... 33
SECTION 2. APPLICATION EXAMPLES....................................................................... 30
SECTION 1. SIGNAL DESCRIPTION ............................................................................. 7
1.2 Pin Description............................................................................................................................8
Pin Type Definitions ....................................................................................................................8
1.2.1
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3.2 MII/SNI/RMII ...............................................................................................................................34
MII PHY Mode ...........................................................................................................................34
MII MAC Mode ..........................................................................................................................36
SNI PHY Mode ..........................................................................................................................37
RMII PHY Mode ........................................................................................................................38
MII/SNI Configuration ................................................................................................................39
Enabling the MII/SNI Interfaces.................................................................................................39
Port Status Registers ................................................................................................................39
MII 200 Mbps Mode...................................................................................................................40
3.4 Address Management...............................................................................................................47
Address Translation Unit ...........................................................................................................48
Address Searching or Translation .............................................................................................49
Address Learning ......................................................................................................................49
Address Aging ...........................................................................................................................50
Address Translation Unit Operations ........................................................................................50
3.3 Media Access Controllers (MAC) ............................................................................................41
Backoff ......................................................................................................................................41
Half-Duplex Flow Control ..........................................................................................................41
Full-Duplex Flow Control ...........................................................................................................42
Forcing Flow Control .................................................................................................................43
Statistics Counters ....................................................................................................................43
Extensive RMON/Statistics Counters........................................................................................43
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Ingress Policy............................................................................................................................56
Forward Unknown/Secure Port .................................................................................................56
Quality of Service (QoS) Classification .....................................................................................56
VLANs .......................................................................................................................................59
3.5.1
3.5.2
3.5.3
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
Document Classification: Proprietary Information
CONFIDENTIAL
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Doc. No. MV-S100968-00 Rev. A
December 22, 2003, Advanced
Copyright © 2003 Marvell
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Link Street™88E6083
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM, Transceivers
3.7 Egress Policy............................................................................................................................ 78
Tagging and Untagging Frames .............................................................................................. 78
Priority Override........................................................................................................................ 79
VID 0x000 and VID Override .................................................................................................... 79
Egress Double VLAN Tagging.................................................................................................. 79
Egress Rate Limiting ................................................................................................................ 80
Switch’s Egress Header ........................................................................................................... 81
Switch’s Egress Trailer ............................................................................................................. 82
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
VLAN Translation Unit Operations ........................................................................................... 63
3.5.4
Switching Frames Back to their Source Port ............................................................................ 68
3.5.5
IGMP/MLD Snooping................................................................................................................ 68
3.5.6
Port States................................................................................................................................ 70
3.5.7
Ingress Double VLAN Tagging ................................................................................................. 70
3.5.8
3.5.9
Ingress Rate Limiting................................................................................................................ 71
3.5.10 Switch’s Ingress Header........................................................................................................... 72
3.5.11 Switch’s Ingress Trailer ........................................................................................................... 73
3.6 Queue Controller ...................................................................................................................... 75
Frame Latencies....................................................................................................................... 75
3.6.1
No Head-of-Line Blocking......................................................................................................... 75
3.6.2
QoS with and without Flow Control .......................................................................................... 75
3.6.3
Guaranteed Frame Delivery without Flow Control.................................................................... 75
3.6.4
Fixed or Weighted Priority ........................................................................................................ 76
3.6.5
The Queues.............................................................................................................................. 76
3.6.6
Queue Manager........................................................................................................................ 76
3.6.7
Output Queues ......................................................................................................................... 77
3.6.8
3.6.9
Multicast Handler...................................................................................................................... 77
3.6.10 WatchDog................................................................................................................................. 77
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
4.1 Transmit PCS and PMA............................................................................................................ 89
100BASE-TX Transmitter ......................................................................................................... 89
4B/5B Encoding........................................................................................................................ 89
Scrambler ................................................................................................................................. 89
NRZ to NRZI Conversion.......................................................................................................... 89
Pre-Driver and Transmit Clock ................................................................................................. 89
Multimode Transmit DAC ......................................................................................................... 89
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2 Receive PCS and PMA ............................................................................................................. 90
10-BASE-T/100BASE-TX Receiver.......................................................................................... 90
AGC and Baseline Wander ...................................................................................................... 90
4.2.1
4.2.2
SECTION 4. PHYSICAL INTERFACE (PHY) FUNCTIONAL DESCRIPTION ....................... 86
3.10 Interrupt Controller................................................................................................................... 84
3.11 Port Monitoring Support .......................................................................................................... 84
3.8 Spanning Tree Support............................................................................................................ 84
3.12 Port Trunking Support ............................................................................................................. 85
3.9 Embedded Memory .................................................................................................................. 84
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S100968-00 Rev. A
December 22, 2003, Advanced
Copyright © 2003 Marvell
Page 2
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Table of Contents
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4.4 Virtual Cable Tester™...............................................................................................................95
4.3 Far End Fault Indication (FEFI)................................................................................................95
4.5 Auto MDI/MDIX Crossover .......................................................................................................96
4.7 Serial Management Interface (SMI) .......................................................................................103
MDC/MDIO Read and Write Operations .................................................................................103
4.7.1
4.6 LED Interface.............................................................................................................................96
Parallel LED Interface ...............................................................................................................97
Serial LED Interface ..................................................................................................................98
4.6.1
4.6.2
ADC and Digital Adaptive Equalizer..........................................................................................90
4.2.3
Digital Phased Locked Loop (DPLL) .........................................................................................90
4.2.4
NRZI to NRZ Conversion ..........................................................................................................90
4.2.5
Descrambler ..............................................................................................................................90
4.2.6
Serial-to-Parallel Conversion and 5B/4B Code-Group Alignment .............................................91
4.2.7
5B/4B Decoder ..........................................................................................................................91
4.2.8
Setting Cable Characteristics ....................................................................................................93
4.2.9
4.2.10
Scrambler/Descrambler............................................................................................................93
4.2.11 Digital Clock Recovery/Generator .............................................................................................93
4.2.12
Link Monitor...............................................................................................................................93
4.2.13 Auto-Negotiation........................................................................................................................94
4.2.14 Register Update ........................................................................................................................94
4.2.15 Next Page Support ....................................................................................................................94
4.2.16
Status Registers .......................................................................................................................94
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MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
8.3 Package Thermal Information................................................................................................171
Thermal Conditions for 216-pin LQFP Package......................................................................171
DC Electrical Characteristics...................................................................................................172
5.2 Switch Core Registers............................................................................................................107
Switch Core Register Map.......................................................................................................108
Switch Port Registers ..............................................................................................................110
Switch Global Registers ..........................................................................................................121
5.2.1
5.2.2
5.2.3
SECTION 5. REGISTER DESCRIPTION ..................................................................... 105
SECTION 8. ELECTRICAL SPECIFICATIONS.............................................................. 169
SECTION 7. EEPROM PROGRAMMING FORMAT..................................................... 167
SECTION 6. PHY REGISTERS ................................................................................ 140
8.2 Recommended Operating Conditions ..................................................................................170
7.1 EEPROM Programming Details .............................................................................................167
5.1 Register Types ........................................................................................................................107
8.1 Absolute Maximum Ratings...................................................................................................169
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S100968-00 Rev. A
December 22, 2003, Advanced
Copyright © 2003 Marvell
8.3.1
8.3.2
Page 3
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8.3.4
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Link Street™88E6083
Integrated 10-Port 10/100 Ethernet Switch with QoS, RAM, Transceivers
Digital Operating Conditions................................................................................................... 173
IEEE DC Transceiver Parameters.......................................................................................... 174
8.4 AC Electrical Specifications.................................................................................................. 175
Reset and Configuration Timing ............................................................................................. 175
8.4.1
Clock Timing when using a 25 MHz Oscillator ....................................................................... 176
8.4.2
MII Receive TimingPHY Mode ............................................................................................... 177
8.4.3
MII Transmit Timing—PHY Mode........................................................................................... 178
8.4.4
MAC Mode Clock Timing........................................................................................................ 179
8.4.5
MII Receive Timing—MAC Mode ........................................................................................... 180
8.4.6
MII Transmit Timing—MAC Mode .......................................................................................... 181
8.4.7
MAC Mode Clock Timing, 200 Mbps ...................................................................................... 182
8.4.8
8.4.9
MII Receive Timing—PHY Mode, 200 Mbps .......................................................................... 183
8.4.10 MII Transmit Timing—PHY Mode, 200 Mbps ......................................................................... 184
8.4.11 MII Receive Timing—MAC Mode, 200 Mbps ......................................................................... 185
8.4.12 MII Transmit Timing—MAC Mode, 200 Mbps ........................................................................ 186
8.4.13 SNI Falling Edge Receive Timing........................................................................................... 187
8.4.14 SNI Falling Edge Transmit Timing.......................................................................................... 188
8.4.15 SNI Rising Edge Receive Timing ........................................................................................... 189
8.4.16 SNI Rising Edge Transmit Timing .......................................................................................... 190
8.4.17 RMII Receive Timing .............................................................................................................. 191
8.4.18 RMII Transmit Timing ............................................................................................................. 192
8.4.19 Serial LED Timing................................................................................................................... 193
8.4.20 Serial Management Interface Clock Timing............................................................................ 194
8.4.21 Serial Management Interface Timing...................................................................................... 195
8.4.22 EEPROM Timing .................................................................................................................... 196
IEEE AC Parameters.............................................................................................................. 197
8.4.23
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
1st40sfouilpl-e3mniopd * Wintech Microelectronics Co. Ltd. - China
MARVELL CONFIDENTIAL, UNDER NDA# 12102018
SECTION 9. PACKAGE MECHANICAL DIMENSIONS................................................... 198
9.1 Ordering Part Numbers and Package Markings .................................................................. 200
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S100968-00 Rev. A
December 22, 2003, Advanced
Copyright © 2003 Marvell
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