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占空比可变分频器.docx
1、这个是主模块，我给它命名为 divandpmw
`timescale 1ns/1ns
module divandpmw(clk_in,rst,div,pmw,clk_out);
input clk_in;
input rst;
input [1:0]div;
input [1:0]pmw;
output clk_out;
reg [3:0]cnt_two;
reg [3:0]cnt_three;
reg [3:0]cnt_five;
reg clk_two;
reg clk_three;
reg clk_five;
reg clk_out1;
reg clk_out2;
reg clk_out3;
reg clk_out4;
reg clk_out;
initial
begin
cnt_two=4'b0;
cnt_three=4'b0;
cnt_five=4'b0;
clk_two=0;
clk_three=0;
clk_five=0;
clk_out1=1;
clk_out2=1;
clk_out3=1;
clk_out4=1;
end
always@(posedge clk_in)
case(pmw)
2'b00:
begin
#15 clk_out1<=0;
#15 clk_out1<=1;
end
2'b01:
begin
#10 clk_out1<=0;
#20 clk_out1<=1;
end
2'b10:
begin
#20 clk_out1<=0;
#10 clk_out1<=1;
end
2'b11:
begin
#18 clk_out1<=0;
#12 clk_out1<=1;
end
endcase
always@(posedge clk_in)
begin
if(!rst)
cnt_two<=4'b0000;
else if(cnt_two>=4'b0001)
cnt_two<=4'b0000;
else
cnt_two<=cnt_two+4'b0001;
end
always@(negedge clk_in)
begin
if(!rst)
clk_two<=1'b1;
else if(cnt_two==4'b0001)
clk_two<=1'b0;
else
clk_two<=1'b1;
end
always@(posedge clk_two)
case(pmw)
2'b00:
begin
#30 clk_out2<=0;
#30 clk_out2<=1;
end
2'b01:
begin
#20 clk_out2<=0;
#40 clk_out2<=1;
end
2'b10:
begin
#40 clk_out2<=0;
#20 clk_out2<=1;
end
2'b11:
begin
#36 clk_out2<=0;
#24 clk_out2<=1;
end
endcase
always@(posedge clk_in)
begin
if(!rst)
cnt_three<=4'b0000;
else if(cnt_three>=4'b0010)
cnt_three<=4'b0000;
else
cnt_three<=cnt_three+4'b0001;
end
always@(negedge clk_in)
begin
if(!rst)
clk_three<=1'b1;
else if(cnt_three==4'b0001)
clk_three<=1'b0;
else if(cnt_three==4'b0010)
clk_three<=clk_in;
else
clk_three<=1'b1;
end
always@(posedge clk_three)
case(pmw)
2'b00:
begin
#45 clk_out3<=0;
#45 clk_out3<=1;
end
2'b01:
begin
#30 clk_out3<=0;
#60 clk_out3<=1;
end
2'b10:
begin
#60 clk_out3<=0;
#30 clk_out3<=1;
end
2'b11:
begin
#54 clk_out3<=0;
#36 clk_out3<=1;
end
endcase
always@(posedge clk_in)
begin
if(!rst)
cnt_five<=4'b0000;
else if(cnt_five>=4'b0100)
cnt_five<=4'b0000;
else
cnt_five<=cnt_five+4'b0001;
end
always@(negedge clk_in)
begin
if(!rst)
clk_five<=1'b1;
else if(cnt_five==4'b0001||cnt_five==4'b0010)
clk_five<=1'b0;
else if(cnt_five==4'b0011)
clk_five<=clk_in;
else
clk_five<=1'b1;
end
always@(posedge clk_five)
case(pmw)
2'b00:
begin
#75 clk_out4<=0;
#75 clk_out4<=1;
end
2'b01:
begin
#50 clk_out4<=0;
#100 clk_out4<=1;
end
2'b10:
begin
#100 clk_out4<=0;
#50 clk_out4<=1;
end
2'b11:
begin
#90 clk_out4<=0;
#60 clk_out4<=1;
end
endcase
always@(*)
case(div)
2'b00:
begin
clk_out<=clk_out1;
end
2'b01:
begin
clk_out<=clk_out2;
end
2'b10:
begin
clk_out<=clk_out3;
end
2'b11:
begin
clk_out<=clk_out4;
end
endcase
endmodule
2、这个是测试激励模块，我给它命名为 testbench
`timescale 1ns/1ns
module t;
reg Clk_in;
reg Rst;
reg [1:0]Div;
reg [1:0]Pmw;
wire Clk_out;
initial
begin
Clk_in=1'b0;
Rst=0;
Div=2'b11;
Pmw=2'b11;
end
always
begin
#15 Clk_in=~Clk_in;
end
divandpmw dandp(.clk_in(Clk_in),.div(Div),.pmw(Pmw),.clk_out(Clk_out),.rst(Rst));
initial
begin
#60 Div=2'b00;
Pmw=2'b00;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b01;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b10;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b11;
Rst=1;
#800 Rst=0;
#60 Div=2'b01;
Pmw=2'b00;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b01;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b10;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b11;
Rst=1;
#800 Rst=0;
#60 Div=2'b10;
Pmw=2'b00;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b01;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b10;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b11;
Rst=1;
#800 Rst=0;
#60 Div=2'b11;
Pmw=2'b00;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b01;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b10;
Rst=1;
#800 Rst=0;
#60 Pmw=2'b11;
Rst=1;
#800 Rst=0;
end
endmodule
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