深 圳 大 学 实 验 报 告
课程名称:
数字系统现场集成技术
实验项目名称: VGA 控制器设计实现显示器屏幕保护模块
学院:
信息工程学院
专业:
集成电路与集成系统设计
指导教师:
邓小莺
报告人: 学号: 2013800369 班级: 集成 2 班
实验时间:
2016 年 4 月 19 日
教务部制
基本要求:通过 FPGA 板的 VGA 接口在显示器上分别显示不同颜色的横向、竖直条纹图案,
横向条纹和竖直条纹的切换通过 FPGA 板上的按键实现。
横向条纹要求是一幅 640*480 由 8 条不同颜色的横向条纹组成的图像,从上到下
颜色分别为:红,蓝,绿,蓝,红,绿,红,蓝;
竖直条纹要求是一幅 640*480 由 8 条不同颜色的竖直条纹组成的图像,从左到右
颜色分别为:红,蓝,绿,蓝,红,绿,红,蓝。
高级要求(可选):通过 VGA 控制器,在屏幕上显示 640*480 的单色背景,并在该背景上叠
加一个小方块,该小方块能够再屏幕上上下左右移动,实现屏幕保护的效果。VGA
单色的背景色自定,小方块的大小自定;以视觉上合适为佳;该小方块要能够按
照一定的轨迹在屏幕上运行,速度适中。
ASM 流程图
VHDL 代码
工程文件包括下面
调用 IP 时钟,产生 25M 时钟,写个按键消抖
--下面是按键消抖程序
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
key_in : in STD_LOGIC;
key_out : out STD_LOGIC);
end key;
architecture key of key is
begin
process(clk,reset,key_in)
variable count:integer range 0 to 2000000;
begin
if(reset='1')then
key_out<='0';
elsif(key_in='0')then
count:=0;
key_out<='0';
elsif(clk'event and clk='1')then
count:=count+1;
if(count=2000000)then
count:=0;
key_out<='1';
end if;
end if;
end process;
end key;
------------------------下面是 color.vhd 文件----------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2016/04/18 16:21:46
-- Design Name:
-- Module Name: color - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity color is
--系统时钟输入
--复位
--按键切换显示
Port (
clk:in std_logic;
reset:in std_logic;
key_c:in std_logic;
vs,hs:out std_logic;
rgb:out std_logic_vector(11 downto 0)
);
end color;
architecture Behavioral of color is
signal clk_25:std_logic;
signal h,v:std_logic;
signal locked:std_logic;
signal rgbs:std_logic_vector(11 downto 0);
signal blank:integer range 0 to 1;
signal state:integer range 0 to 2;
signal h_count:integer range 0 to 800:=0;
signal v_count:integer range 0 to 525:=0;
signal key_out:std_logic;
--调用 clk IP----------------
component clk_wiz_0 is
port(
clk_in1:in std_logic;
clk_out1:out std_logic;
reset:in std_logic;
locked:out std_logic
);
end component;
----------------调用按键--------------------
component key is
port(
clk:in std_logic;
reset:in std_logic;
key_in:in std_logic;
key_out:out std_logic
);
end component;
begin
U1:clk_wiz_0 port map(clk,clk_25,reset,locked);
KEY1:key port map(clk,reset,key_c,key_out);
--实例化时钟
--实例化按键
process(clk_25)
begin
if(clk_25'event and clk_25='1') then
if(h_count=800) then
h_count<=0;
if(v_count=525)then
v_count<=0;
else v_count<=v_count+1;
end if;
else h_count<=h_count+1;
end if;
if (blank =0) then
rgb<=rgbs;
else
rgb<="ZZZZZZZZZZZZ";
end if;
if(
v_count
>= 480 or v_count < 0)then
blank <= 1;
else
if( h_count < 640 and h_count
>= 0) then
else
blank <= 0;
blank <= 1;
end if;
end if;
if(h_count>=656 and h_count<752) then --根据 640x480
hs<='0';
else hs<='1';
end if;
if(v_count>=490 and v_count<492) then
vs<='0';
else vs<='1';
end if;
end if;
end process;
process(reset,key_out)
begin
if(reset='1')then
state<=0;
elsif(key_out'event and key_out='1')then
case state is
when 0=> state<=1;
when 1=> state<=2;
when 2=> state<=0;
when others=>null;
end case;
end if;
end process;
process(clk,state,h_count,v_count)
variable count1:integer range 0 to 640;
variable count2:integer range 0 to 480;
variable count4:integer range 0 to 640:=320;
variable count5:integer range 0 to 480:=240;
variable s:integer range 0 to 1;
--记录状态
--记录转态
variable t:integer range 0 to 1;
--记录转态
variable x:integer range 0 to 1;
variable y:integer range 0 to 1;
--记录转态
variable co:integer range 0 to 20;
--显示颜色
variable count3:integer range 0 to 2000000;
begin
--控制移动快慢
if(clk'event and clk='1')then
if(count3=2000000)then
count3:=0;
if(co>=8)then
co:=0;
end if;
if(count1=40)then
s:=0;
co:=co+1;
elsif(count1=600)then
s:=1;
co:=co+1;
end if;
if(count2=40)then
t:=0;
co:=co+1;
elsif(count2=440)then
t:=1;
co:=co+1;
end if;
if(count4=40)then
x:=0;
co:=co+1;
elsif(count4=600)then
x:=1;
co:=co+1;
end if;
if(count5=40)then
y:=0;
co:=co+1;
elsif(count5=440)then
y:=1;
co:=co+1;
end if;
case s is
when 0 =>
when 1 =>
end case;
case t is
when 0 =>
when 1 =>
end case;
case x is
when 0 =>
when 1 =>
end case;
case y is
when 0 =>
when 1 =>
end case;
count1:=count1+1;
count1:=count1-1;
count2:=count2+1;
count2:=count2-1;
count4:=count4+1;
count4:=count4-1;
count5:=count5+1;
count5:=count5-1;
else count3:=count3+1;
end if;
if(state=0)then
if(v_count<60)then rgbs<="001100000000";